JPS60156146A - Bus connection controlling system - Google Patents

Abstract

PURPOSE:To enable simultaneous writing in two memory systems of present use and spare, and access only to the spare system in a duplex system and to make the titled system small in size and inexpensive by identifying a signal of a processor side for access discriminating by a bus switching controlling circuit and switching to a specified circuit. CONSTITUTION:In a duplex system of a present use system and a spare system, a switching circuit 5 of processor buses 15, 15' on own system and other system and its switching controlling circuit 7 are provided between a spare memory 1 and a spare memory 2 in present use and spare memories 2, and a function code generating circuit 6 that discriminates access of program and data is provided in the processor 1. Further, a function code identifying circuit 8, an access mode FF9, an access route controlling circuit 11, etc. are provided in the circuit 7. An address bit signal that designates a memory system to be accessed out of the circuit 8, FF9, bus 15, etc. is inputted by the circuit 11 to enable outputting of a controlling signal 17 of the circuit 5. Thus, a conventional bus coupler is made unnecessary.

Description

[Detailed Description of the Invention] [Usage of the Invention] The present invention relates to a bus connection control system, and particularly to a duplex 4t bus connection control system.
Bus connection control method when writing to both systems of memory at the same time in a processor and memory that is connected to the computer In the system, a method for the active processor to access the spare memory is via bus couplers 3 and 3', as shown in FIG. That is, a bus that connects the active processor l and the active memory 2, and a bus that connects the active processor l and the active memory 2, and
The buses connecting the memory 2' and the spare memory 2' are connected by bus couplers 3, 3', and the memories of other systems are accessed through this route. However, in the system shown in FIG. 1, in order to access the spare memory 2' from the active processor 1, it is necessary to activate the bus couplers 3, 3' to form a route. here,
For example, the bus coupler 3゜3' can transmit signals only in the right direction.
A configuration is used in which drivers that allow passage only in the left direction are connected in parallel, and one of the drivers is turned on by an activation signal.

On the other hand, for access from the active processor 1 to the active memory 2, there is no need to activate the bus coupler 3'3'.

Therefore, in this method, different procedures are required for accessing the active system memory 2 and accessing the backup system memory 2', and the access time to the backup system memory 2', which requires a complicated procedure, becomes long. .

Generally, the purpose of duplicating equipment is to improve the reliability of the system by switching to a standby system in the event of equipment failure, but in the case of Hinoki, continuity of processing is maintained when switching systems. In other words, the current and standby memory 2
, 2' must always match. However, in the method shown in Figure 1, the memory access procedures for the active system and the backup system are different, so the system always uses the backup system memory.
The contents of ' are delayed in time from the contents of the active memory 2, and therefore continuity of processing cannot be maintained in many cases. For example, when writing the same contents to the active memory 2 and the backup memory 2' to make the contents match, the active memory 2 performs the next write after the writing is completed, but during that period, the backup memory The previous write is still being executed in the memory 2', and at the time when the spare memory 2' has finished writing.

This means that the active memory 2 is in the process of writing or has finished writing the next content.

Furthermore, conventionally, in order to eliminate the discrepancy between the memory contents of the active system and the backup system due to the difference in procedures as described above, a system with a duplex configuration as shown in FIG. 2 has also been used.

In this configuration, a bus switching circuit 4.4' is provided between the dual processor 1.1' and the memories 2, 2', and a bus switching circuit 4.4' is provided between the dual processor 1.1' and the memories 2 and 2'.

1', connect any three buses to memory 2.2.
By connecting the current processor 1 to the memory 2 and 2', the current processor 1 can write the numbers to both memories 2 and 2' at the same time. Although not shown in the figure, when controlling the bus switching circuits 4 and 4', the current processor 1 performs control using separate control signal lines.
In addition to accessing 2' in parallel, in some cases, the current processor 1 and the current memory 2 and the standby processor 1' and the standby memory 2' may be connected to operate each prefecture independently. It becomes possible.

However, although the system shown in Figure 2 solves the problem of mismatch between the memory contents of the active and backup systems (a drawback of the system shown in Figure 1), the system only accesses the spare memory 2' from the active processor 1. becomes impossible. The reason i has to do with reading from memory 2,2. That is,
Memory i to be read only from spare memory 2' is data J.
j (operand), and the program (instruction) must always be read from the current memory 2. However, in the conventional system, the current processor 1 controls only one of the bus switching circuits 4 and 4'. This is because it cannot be separated.

Other examples of wanting to access only the spare memory 2' include the following. In other words, when a failure occurs in the standby system, the details of the failure are recorded in the standby system, so if you want to access only the standby system, or when diagnosing the standby system, you can save the diagnostic program from the current memory 2. The data is transferred to the spare memory 2', but in this case as well, it is necessary to write the contents read from the active system only to the spare system.

Therefore, in the past, the methods shown in Figures 1 and 2 were combined to create a third
A configuration as shown in the figure has been proposed. However, this method requires both bus couplers 3, 3' and bus switching circuits 4, 4', which increases the amount of hardware, which goes against the demands for smaller size and lower cost. Become.

[Purpose of the invention]

The purpose of the present invention is to eliminate these conventional drawbacks and provide a small and economical bus connection control system that allows simultaneous writing to both active and backup memories and access to only the backup memory. It's about doing.

[Summary of the invention]

In order to achieve the above object, the bus connection control method of the present invention provides an information processing system in which processors and memories are duplicated into active and standby, and is equipped with a bus switching circuit that switches the bus connection route between each processor and memory. On the processor side, there is a means for outputting a signal that distinguishes between program and data accesses, and on the memory side, means is provided to identify the above-mentioned access distinction signals and output signals to the current memory if it is a program, or to the preset memory if it is data. The present invention is characterized in that it includes means for outputting a switching signal for accessing each memory.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to FIG.

In FIG. 4, only one of the systems in which the processor and memory are duplicated is shown, and the overall configuration is shown on the right side in line-symmetrical relation with respect to the one-dot chain line.

1 is a current processor, 2 is a spare memory, 5 is a bus switching circuit, 6 is a function code generation circuit, 8 is a function code identification circuit, 9 is an access mode flip-flop, 10 is a current and spare display slip-flop, 11 is an access route control circuit, 16 is a system designated address pin, and 6.18. Yotsua, Yotsu-1-1
'(l!-1 Yes, (As in the past, between the processor 1 and the memory 2, there is a link between the processor bus 15 of the own system and the processor bus 15' of the other system) to select one. A bus switching circuit 5 and a bus switching control circuit 7 for controlling the switching circuit 5 are provided.

The processor 1 includes a function code generation circuit 6 that distinguishes whether the current access is to read a program (instruction) or read or write data (operands), and the bus switching control circuit 7 includes the above-mentioned function code generation circuit 6. Circuit 8 for identifying faction code
, an access mode flip-flop 9 that determines an access route that can be rewritten by a command from the active processor 1, and a flip-flop 10 that displays whether the own processor 1 and memory 2 are active or spare; Function code identification circuit 8, access mode
Flip flop9. An access route that inputs an address bit signal 16 specifying the memory system to be accessed among the current/standby display flip-flop 10 and the processor bus 15 and outputs a signal 17 controlling the bus switching circuit 5. A control circuit 11 is provided.

On the other hand, from the active/standby display flip-flop 10,
The active standby signal of the processor is output, and controls the selector 12 which selects the active system signal from the own system function code signal 18 and the other system function code signal 18'. Similarly, the signals controlling the access mode flip-flop 9 and the active reserve display slip prop 10 are also connected to their respective selectors 13.14.
Selected by

In such a configuration, normally both memory systems 2, 2
Since the access mode flip-flop 9 is set to a mode in which data is simultaneously written to ', the system designated address bit signal 16 is ignored within the access route control circuit 11.

On the other hand, when the access mode flip-flop 9 is set to access either the active or the backup, the access route control circuit 11 controls the data (operand) determines the access route.

In any of the above cases, the access/route control circuit 11 always accesses the active memory 2 for programs (instructions).

In the conventional system, processor l,1' and memory 2.2'
If the active system processor determines the current and standby systems of the system and sets the bus connection mode in advance, such as writing to memory 2゜2' simultaneously or operating each prefecture independently, the access route can be changed. remained constant unless the settings were changed. In contrast, in FIG. 4, the bus switching control circuit 7 switches the access route each time the memories 2, 2' are accessed. Therefore, in FIG. 4, a signal is generated on the processor L side to distinguish whether the access from the processor 1 to the memory 2゜2' is for a program (instruction) or data (operand). By identifying this signal, the program (instruction) always accesses the active system, and the data (operand) accesses the previously set system.

Furthermore, conventional bus couplers have required a large number of signal lines to connect processors and buses, and have required approximately three A4-sized printed circuit boards. Based on this, the function code generation circuit 6 shown in FIG.
Many of them are built into microprocessors, so if a processor like -2 is used, there is no need for additional hardware. In addition, the function code identification circuit 6
The access/route control circuit 11 can be made smaller by using a ROM or an LSI.

〔Effect of the invention〕

As explained above, according to the present invention, it is provided with a function of writing to both the current and standby memory systems simultaneously, a function of accessing any one system, and an optical bus coupler, which was conventionally necessary, is provided. Since this is not necessary, the bus connection control section can be made smaller and more economical.

[Brief explanation of the drawing]

1, 2, and 3 are block diagrams of a conventional duplex information processing device, and FIG. 4 is a block diagram of a bus connection control section showing an embodiment of the present invention. 1.1'...processor, 2,2'...memory, 3
゜3'... Bus coupler, 4.4', '5... Bus switching circuit, 6... Function code generation circuit, 8... Function code identification circuit, 9...
Access mode flip-flop, 1O... Current/standby display flip-flop, 11... Access mode flip-flop,
Route control circuit, 16... System designation address/bit signal ■1 Figure l2 Figure π3 Figure 4 Procedural amendments Showa 545/1 1 also indicates the case of the Commissioner of the Japan Patent Office 1988 Patent application No. 10069 Title of the invention Relationship with the case of the person making amendments to the bus connection control system Patent applicant name (510) Hitachi Manufacturing Co., Ltd. Agent address: 5-1 Marunouchi-chome, Chiyoda-ku, Tokyo 100 Hitachi Manufacturing Co., Ltd. 1. [Detailed Description of the Invention] column, ``Brief Description of Drawings'' column, and drawings. Contents of amendment 1: The scope of claims on pages 1 and 2 of the specification of the present application is amended as shown in the attached sheet. 2. Add "and bus switching control circuit" after "bus switching circuit" on page 7, line 16 of the same document above. 3. Ibid., page 7, line 19, "memory side" is corrected to "bus switching control circuit." 4. Ibid., page 10, 1st line, add "19" after "working reserve signal". 5. Ibid., page 13, line 9 [Code signal. ”
is corrected to "code signal, 19...processor's active standby signal." 6. The drawing, Figure 4, is amended as per the attached amended drawing (number 18 is amended to 19). Attachment Claims ■: A bus switching circuit for duplicating processors and memories into active and backup, and switching bus connection routes between each processor and memory. , ? J iF III
#In an information processing system equipped with a shell, the processor side is equipped with a means for outputting a signal that distinguishes between program and data accesses, and the S2S transfer control circuit is equipped with means for identifying the above-mentioned access distinction signal. A bus connection control system comprising means for outputting a switching signal for accessing a current memory for a program and a preset memory for data. 2. The switching signal output means is equipped with a circuit that displays whether the processor and memory are currently in use or spare, and when accessing a program, a switching signal is provided so that the current memory displayed by the current or spare display circuit is accessed. The bus connection control system according to claim 1, wherein the bus connection control system outputs the following. 3. The switching signal output means is equipped with a circuit for specifying an access mode, and inputs address bits of a processor bus specifying a memory system using arbitrary bits, and when accessing data, the above-mentioned access mode is selected. 2. The bus connection control system according to claim 1, wherein a switching signal is outputted to access the designated memory according to the designation of the designated circuit and the contents of the address bits.

Claims (1)

[Claims] 1. The processor and memory are dually used for current use and for backup. In an information outer ring system5 equipped with a path switching circuit that switches the bus connection between each processor and memory,
On the processor side, there is a means for outputting a signal that distinguishes between program and data accesses, and on the memory side, means is provided to identify the above-mentioned access distinction signal and set it in advance in the current memory if it is a program or if it is data. may have been done
1. A bus connection control system characterized by comprising means for outputting a switching signal for accessing each bus. 2. The switching signal output means is equipped with a circuit that displays whether the processor and memory are currently in use or spare, and when accessing a program, a switching signal is provided so that the current memory displayed by the current or spare display circuit is accessed. The bus connection control system according to claim 1, wherein the bus connection control system outputs the following. -3, Said! The change signal output means number specifies the access mode, specifies the memory system with arbitrary bits, inputs the address bits of the processor path, and accesses the data. , according to the designation of the access mode designation circuit and the contents of the address bits, a switching signal is output so as to access the designated memory. method.