JPS60155238U - stereo multiplex circuit - Google Patents
stereo multiplex circuitInfo
- Publication number
- JPS60155238U JPS60155238U JP1984042913U JP4291384U JPS60155238U JP S60155238 U JPS60155238 U JP S60155238U JP 1984042913 U JP1984042913 U JP 1984042913U JP 4291384 U JP4291384 U JP 4291384U JP S60155238 U JPS60155238 U JP S60155238U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- oscillation
- detection circuit
- forced voltage
- differential amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stereo-Broadcasting Methods (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
呻を示す回路図、第2図は本考案の一実施例を示+嵩=
−景ばi″″°”*1°8“1°5″″f″G″″ I
主な図番の説明、1・・・VCO15・・・同期検波回
路、工・・・差動増幅回路、8・・・外部電源、1o・
・・ス ゛イッチ、13・・・電源、24・・・検出回
路、27,28・・・検出トランジスタ、29・・・正
帰還トランジスタ、30・・・NPNトランジスタ。Figure 2 shows an embodiment of the present invention.
-View i″″°”*1°8″1°5″″f″G″″I
Explanation of main drawing numbers, 1...VCO15...Synchronous detection circuit, Engineering...Differential amplifier circuit, 8...External power supply, 1o...
...Switch, 13...Power source, 24...Detection circuit, 27, 28...Detection transistor, 29...Positive feedback transistor, 30...NPN transistor.
Claims (1)
レオパイロツト信号を検波する同期検波回路と、該同期
検波回路の出力信号を増幅する差動増幅回路と、該差動
増幅回路の一方の入力に強制電圧を印加する強制電圧印
加手段と、前記差動増幅回路の両入力間の電位差を検出
する正帰・連室の検出回路と、該検出回路の出力信号に
応じて作動し、副搬送波再生用のPLL回路中に含まれ
るVCOの発振を停止させる発振停止回路とから成り、
前記強制電圧印加手段から強制電圧が印加さ杆たことを
前記検出回路で検出し、前記発振停止回路を動作させて
VCOの発振停止を行う様にしたことをi徴きするステ
レオマルチプレックス回路。A synchronous detection circuit that detects a 19KHz stereo pilot signal included in one stereo component signal, a differential amplifier circuit that amplifies the output signal of the synchronous detection circuit, and a forced voltage applied to one input of the differential amplifier circuit. a forced voltage application means to apply; a positive return/continuous chamber detection circuit for detecting a potential difference between both inputs of the differential amplifier circuit; and a PLL for subcarrier regeneration which operates according to the output signal of the detection circuit. It consists of an oscillation stop circuit that stops the oscillation of the VCO included in the circuit,
A stereo multiplex circuit characterized in that the detecting circuit detects that a forced voltage is not applied from the forced voltage applying means, and operates the oscillation stop circuit to stop oscillation of the VCO.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984042913U JPS60155238U (en) | 1984-03-26 | 1984-03-26 | stereo multiplex circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1984042913U JPS60155238U (en) | 1984-03-26 | 1984-03-26 | stereo multiplex circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60155238U true JPS60155238U (en) | 1985-10-16 |
JPH04603Y2 JPH04603Y2 (en) | 1992-01-09 |
Family
ID=30554092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1984042913U Granted JPS60155238U (en) | 1984-03-26 | 1984-03-26 | stereo multiplex circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60155238U (en) |
-
1984
- 1984-03-26 JP JP1984042913U patent/JPS60155238U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPH04603Y2 (en) | 1992-01-09 |
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