JPS60154361A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To reduce noise by controlling output signals of prescribed pitches so that they overlap each other when they are outputted from delay circuits and switching output signals in the overlap period by fade-in and fade-out. CONSTITUTION:Frequencies of clock signals phi1 and phi2 are different by octave, and a ratio of switching times Ta and Tb is set to 2:1. In signals outputted from the first and the second delay circuits 11 and 12, signals where the pitch of an input signals is reduced to 1/2 and signals having a two-fold frequency are repeated. In the time Ta when a lower clock frequency fa is switched from a higher clock frequency, signals are so supplied that they overlap each other in delay circuits 11 and 12 only for a fixed period, and therefore, output signals of omega/2 are outputted from delay circuits 11 and 12 in this period. In this signal processing circuit, the overlap period is used to switch output signals by fade-in and fade-out techniques, and output signals of omega/2 components are synthesized by a soft switching circuit 13 and are outputted. This synthesized signal rises and falls with the same time constant to improve considerably the phase distortion.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a signal processing circuit capable of converting the pitch of a distorted wave alternating signal that is continuously supplied.
In particular, the present invention relates to a signal processing circuit suitable for converting the pitch of an audio signal.

[Background technology and its problems]

If a magnetic tape on which an audio signal is recorded can be played back at a speed faster than the normal tape speed and this can be heard, it is possible to hear the audio signal corresponding to the screen even when playing a VTR at double speed, for example. It is extremely convenient.

The circuit shown in Figure 1 is known as a signal processing circuit that can reduce the pitch of an audio signal, which is considered to be a type of distorted wave, to 1/2 and output the original audio information (waveform). ing.

In this figure, 1. and 2 are the first . and a second delay circuit, and 3 indicates a changeover switch.

This first. As is well known, the second delay circuits 1 and 2 are constructed by connecting n junction capacitors formed of transistors in series, and forming a gate circuit between each junction capacitor. Therefore, when the gate circuit is sequentially controlled to open and close by the clock signals (φ1, φ2), the signal input from the input terminal Ti is outputted by transferring the junction capacitance.

The transfer time at this time, that is, the delay time (τ), is in contact with the frequency f of the clock signal (φ1, φ2).

Therefore, in FIG. 1, the period of the clock signal φ1 supplied to the first delay circuit 1 is initially set to 10 KHz.
If you switch to 5KHz later with the delay time at that time, the input signal St(ω) will change as shown in Figure 2.
After switching from 10KHz to 5KHz, it is output as an output signal Sol whose frequency is 1/2, and when the clock signal φl is switched to 10KHz again,
Initially, the frequency of ω is output, and then the frequency of 2ω is output.

Therefore, when the second delay circuit 2 is similarly supplied with a clock signal φ2 having a period equal to the delay time τ and changing between l0KHz and 5KHz in a period opposite to that of the clock signal φl, the second delay circuit 2 2, the frequency is ω/2. ω,
An output signal SO2 varying with 2ω is obtained.

Therefore, if the changeover switch 3 is controlled to selectively output only the period of the signal that is ω/2, the output terminal To will receive an output signal S61+SO2 whose pitch is half that of the input signal Si(ω). is obtained.

In this case, if the input signal St(ω) is an audio signal, only the pitch can be reduced to 1/2 while the audio waveform is maintained.

In terms of dispersion, this method produces a signal in which the audio information input for the switching period (τ) is omitted, but as long as this switching period is within 20 m5, the quality of the audio does not deteriorate significantly.

However, the junction between the output signal Sol and the output signal S02 by the switch is not necessarily connected in a continuous waveform, as seen in the waveforms of So and +S◇2 in Figure 2. There is a problem in that the phase distortion caused by the noise is large and deteriorates the sound quality.

[Purpose of the invention]

The present invention provides a signal processing circuit capable of reducing the influence of phase distortion occurring in switching lines.

[Summary of the invention]

This invention supplies input signals to at least two or more delay circuits, switches the frequency of a clock signal supplied to the delay circuits at a constant cycle, and outputs signals with different pitches from each delay circuit. Select ``The period of the clock signal that is being supplied when the signal processing circuit configured to output the peak A is output from the delay circuit with a predetermined signal strength.'' are set to overlap with each other, and the output signal of the delay circuit is switched by an analog switch having a time constant during this overlap period.

Therefore, even when the output signal is switched, the output waveform can be made into a continuous signal, which has the advantage of reducing noise due to phase model number and not degrading the signal quality.

〔Example〕

FIG. 3 is a block diagram of a signal processing circuit showing an embodiment of the present invention. Similar to FIG. 1, the input signal St(ω) is
The output signal S is down to 2. This is a circuit that obtains (ω/2).

In this figure, 11.12 is the first. a second delay circuit;
13 is a soft switching circuit composed of an analog switch/Sochi circuit; 14 is the first . Second delay circuit 11.12
For the clock signal φ1.

This is a control signal generating circuit which supplies the switching signal φ2 and also supplies the switching signal φ3 to the soft switching circuit 13j.

15.16 indicates a low-pass filter that suppresses the clock signal component, and is a 17ii band-pass filter (200 to 5000 Hz).

Hereinafter, the operation of the signal processing circuit of the present invention will be explained based on the waveform diagram of FIG. 4.

The frequencies of the clock signals φ1 and φ2 are two clock frequencies fa and f that differ by an octave as in the case of FIG.
b, and 2fa=fb. By the way, the switching periods Ta and Tb of the clock signals φ1 and φ2 of the present invention are set at a ratio of approximately 2:1 as shown in the figure, and the period Tb is the first . The delay time (τ) is selected to be equal to the delay time (τ) of the second delay circuit 11°12.

Therefore, the input signal Si(ω) captured at the higher clock frequency fb is
The input signal S which is output when the switch is switched to , and which is captured in the period Ta and the period Tb of the clock frequency fa.
i(ω) is output.

Therefore, the first. The output signal S'Ol + "02 output from the second delay circuit 11.12 is twice the signal ω/2 which is the input signal Si(ω) pitched down to l/2 as shown in FIG. is repeated at a frequency of 2ω.

By the way, the period Ta of the lower clock frequency fa is the 1st. t to each other in the second delay circuit 11.12. Since the supplies are supplied so that they overlap by the period of
During this overlap period (70), the first. Both the second delay circuits 11 and 12 output signals S' of ω/2. 1. S'.

2 is output.

Therefore, in the signal processing circuit of the present invention, using this period to, the output signal S'Ol + S'02 is switched by fade-out and fade-in techniques, and ω/
Two-component output signal S. I+"02 to soft switching circuit 13
Compose and output.

The junction of this composite output signal SO1+SO2 is.

Since the signals rise and fall with the same time constant, phase distortion is significantly improved.

Figure 5 shows an enlarged example of the waveform at the joint.
The solid line shows the waveform 9 in the conventional example shown in FIG. 1, and the dashed-dotted line shows the waveform in the case of providing an overlap period to and connecting by an analog switch according to the present invention.

In the above explanation, two clock frequencies fa, ! fb
Although we have explained the case where the supply period T a and T b are 2:1, as can be seen from the above explanation,
This ratio may be made even smaller, as long as it is a ratio that allows the overlap period to to be obtained.

FIG. 6 shows an embodiment in which the soft switching circuit 13 is formed of two transistors T, , T2 which are alternately driven on and off.

13a and 13b surrounded by a dashed line are transistors T,
Fade out to T2's switching.

and a time constant circuit for providing fade-in characteristics, and are supplied with switching signals φ3 having mutually opposite phases. The soft rising and falling signals are formed by the time constant of capacitor C1 and resistor rl + r2, diodes D, D2 are connected to transistors T,
, the rise and fall time constants that vary depending on the voltage-radio wave characteristics between the base and emitter of T2 are set by the resistor rI+.
It is used for individual adjustment by r2.

Further, 13c is a buffer amplifier consisting of an emitter follower, and 13d is an inverter.

The switching element is a transistor T1.

A field effect transistor can also be used in place of T2.

In the above embodiment, the case where the pitch of the input signal Si(ω) is reduced to 1/2 was explained, but the pitch is reduced to 1/3.
The signal processing circuit of the present invention can also be applied to the case of scaling down.

In this case, the ratio of the two clock frequencies f a and f b may be tripled, and the respective supply periods may be set at a ratio of approximately 1:3.

However, as described above, as the pitch reduction rate of the signal increases, the missing portion of information in the audio signal increases, and the clarity of the signal decreases.

Moreover, conversely, the signal processing circuit of the present invention has an input signal St(ω
It is also possible to obtain a signal (2ω) that is twice the pinch of ).

In this case, the output signal “OI + S” is shown in the waveform diagram in Figure 4.
It is sufficient to selectively extract the 2ω component signal from '02.

Therefore, the third. A fourth delay circuit is provided to generate a new output signal S' as shown in FIG. Clock frequencies f a and f b are supplied so that 3°3'04 is obtained.

Then, the output signal is changed to So by the software switching circuit 13.
1"So 4 "So 2 "So s" and the 2ω component can be extracted.

〔Effect of the invention〕

As explained above, the signal processing circuit of the present invention controls the output signals having a predetermined pitch so that they overlap each other when outputting them from the delay circuit, and
Since switching is performed by fade-out and fade-in during the over-amplified period, there is an advantage that noise due to phase distortion that is likely to occur in an output signal whose pitch has been changed can be significantly reduced. Therefore, especially when used to pitch down an audio signal recorded on a magnetic tape, the sound quality is significantly improved.

[Brief explanation of drawings]

2 is a main waveform diagram of FIG. 1, FIG. 3 is a block diagram of a signal processing circuit showing an embodiment of the present invention, and FIG.
The figure shows the main waveforms in Fig. 3, Fig. 5 shows the waveforms at the junction of the output signal, Fig. 6 is a circuit diagram showing one embodiment of the soft switching circuit, and Fig. 7 shows the waveforms when obtaining the 2ω component. It is an explanatory diagram. In the figure, 11.12 is the 1st. In the second delay circuit, 13 is a soft switching circuit, φ2 is a clock signal, φ3 is a switching signal, and Si(ω) is an input signal. Figure 1 ψ2 Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] 1st. and a signal processing circuit that supplies an input signal to at least two or more delay circuits to which a second clock signal is alternately supplied, and outputs signals with different pitches by alternately switching outputs of the delay circuits. Supplying the first clock signals so that they overlap each other when a predetermined signal is output from the delay circuit, and
A signal processing circuit characterized in that the output of the delay circuit is controlled to be switched with a predetermined time constant during the overlap period.