JPS60153156A - Semiconductor ic device - Google Patents

Abstract

PURPOSE:To enable the fluctuation in characteristic of IC action to be compensated simply and securely by a method wherein an ROM region is provided in an IC chip, the actual processing conditions for each manufacturing process or the deviation of the actual processing conditions from the design value are kept written fixedly to this memory region for every chip in the connected manufacturing processes. CONSTITUTION:A p type Si wafer 1 is prepared, and an inversion-preventing layer 2 is formed by selective field ion implantation (process S1). Next, a field oxide film 3 is formed by selective oxidation (process S2). A gate oxide film 4 caused by high-temperature thermal oxidation is formed (process S3), and channel ions are implanted (process S4) to control the threshold value; then, a gate electrode 5 is formed by deposition and patterning of polycrystalline Si (process S5). In a series of processes so far, the deviating information of the ion implantation conditions for the field ion implanting process S1 from the design value is written to the region (1) of a region 13 as ''1'', ''0'' according to the presence of channel implantation in the later channel ion implanting process S4.

Description

DETAILED DESCRIPTION OF THE INVENTION [6] Field of the Invention This invention relates to a semiconductor integrated circuit device that takes into account variations in manufacturing process and metering due to miniaturization and higher density of elements.

[Technical background of the invention and its problems]

As half-damaged circuits become larger in size and have a higher M1 length, the integrated circuit chips have smaller integrated circuit elements and the chip size increases, and the diameter of substrate wafers also increases accordingly. .

Correspondingly, the processing conditions of the manufacturing process for the wafer, within the wafer, or within the chip may differ slightly from preset values. In large-scale integrated circuits made up of minute elements, changes in the operating characteristics of individual elements often result in large fluctuations in the operating characteristics of the entire chip due to subtle differences in processing conditions. This becomes a bigger problem as miniaturization and larger scale ratios progress.

For example, in MO8 integrated circuits, an important process in the element isolation process! Consider the ion implantation bar and field oxidation thickness on the substrate surface of the isolation region, which are considered to be parameters.

These design values are respectively 2 x 10”7cm2 and 0
．． The one actually processed as 9μ is 2.05X
Assuming that the thickness is 107 cm and 0.875 μ, the characteristics of the individual MOSFETs constituting the integrated circuit metal will be slightly different from the designed values. Also, MOSFE
Important process parameters that determine the threshold value of T include the ion implantation lid in the channel region, the torsional thickness of the gate insulation, and the length of the dart electrode. Even if the difference is about 5 inches, the threshold value may be shifted by about 20 inches.

If deviations from the design values of such important process parameters are accumulated throughout the entire process, the optimum operating conditions of the integrated circuit may deviate significantly from the design values. Therefore, it is necessary to accurately store information regarding the delivery of such important meters from the installation Lf+M. However, it is difficult to use a skewer to store this in an external storage device for a long period of time, and to use a skewer to remove it when used, which is nearly impossible in reality.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device that can simply and reliably compensate for changes in integrated circuit operating characteristics due to manufacturing process and meter variations.

, [Importance of the Invention] The first gist of the present invention is to provide a ROM area in the circuit chip, and store actual processing conditions of each manufacturing process or design values of the actual processing conditions in this memory area. It is characterized in that the deviation from the chip is fixedly accounted for for each chip in the subsequent manufacturing process. When operating as an integrated circuit, the characteristics of the 91st period are realized by changing the operating conditions according to the chip information in this memory area.

The second gist of the present invention is to incorporate, in addition to the memory area, a circuit function that extracts the information and automatically adjusts the operating conditions of the circuit into the chip. This allows the integrated circuit to
Even if there are fluctuations in the actual manufacturing process or the actual meter, by externally applying operating conditions based on design values, it is possible to dynamically operate the meter under the optimum operating conditions.

In a normal MO8 type identification storage device (mask ROM), information to be stored is stored in an array of MOSFEs.
The thickness of the r-1 oxide film of T, the presence or absence of ion implantation in the channel region, the presence or absence of a contact hole for forming a contact with the drain electrode, etc. are determined in the ROM chip manufacturing process. However, in this case, the information to be stored is given in advance and has nothing to do with the processing conditions given to the ROM manufacturing process. The fixed storage information of the ROM area in the present invention is not predetermined, but is actual processing conditions in the manufacturing process of the integrated circuit or deviation from its design value,
In this respect, it is fundamentally different from a normal ROM.

In this specification, it is assumed that chip information relates to a manufacturing process that is treated as being uniform at least within the chip. In this case, the chip information is normally uniform within the wafer, but if there are variations in manufacturing conditions within the wafer, it may be made different for each chip area within the wafer depending on the variations. Also, Mask R
OiV includes not only those that use processing masks such as ordinary resists, but also those where the mask function is achieved isometrically through the manufacturing process, such as with or without channel ion implantation performed by selective irradiation with an ion beam. shall be held. Mask ROMs include the following MOSFETs, pi-puller transistors, wires cut by υρ with radar, resistor elements, etc.
It is ire.

〔Effect of the invention〕

According to the present invention, an integrated circuit in which finely divided elements are integrated at high density can be operated with desired characteristics on a chip-by-chip basis, regardless of variations in the manufacturing process or motherboard. Furthermore, when a mask ROM is used as the ROM, fixed storage is performed in such an integrated circuit before chip division, so it is extremely easy to correspond between the chip and the information to be stored.

In addition, in particular, if you incorporate the aoMm area as well as the circuit functionality that automatically changes and sets the circuit's operation conditions by processing it inside the 16-information chip, you can achieve the desired operation without requiring any external operations. It is advantageous to be able to obtain certain characteristics.

[Practice of the invention]

The present invention will now be described in detail with reference to an actual JM array that is applicable to MO8 integrated circuits.

FIG. 1 shows a completed integrated circuit chip 11.
In addition to the circuit body J2, there is also a memory area (mask ROM area) 13 in which deviations from the design values of processing conditions for each manufacturing process are written as fixed storage information.
has. As shown in FIG. 2, this memory area has four divided areas (1) to (4). This memory area 13 is M
This is a ROM using O8li'ET, and stores information as 0'' when current flows under normal bias and 1# when current does not flow.However, information in areas (2) to ■ is stored in the integrated circuit. They are written in different processes in a series of manufacturing processes of the main body 12, and therefore, as described below, the element structures for distinguishing between n1n and ltg# are different in regions (2) to (2). Note that the areas ■ and ■ are written using a circular process.

3 and 4 are diagrams for explaining the assembly process of the integrated circuit main body 12 and the memory composition J3. This section explains how information is written. The integrated circuit main body 12 and the memory area J3 are manufactured by the same process. That is, the pWsi wafer 81 is first subjected to selective field ion implantation (process SJ) to form the anti-inversion layer 2. Next, a field ratio film 3 is formed by selective oxidation (Norocess S2). After this, an r-t oxide film 4 is formed by high-temperature thermal oxidation (process S3),
Channel ion implantation (Norocess S) for threshold control
4), and then deposit polycrystalline Si and turn the base to form the r-tooth 5 (Norocess S5).

In the series of steps up to this point, information on the deviation from the design value of the ion implantation conditions of the field ion witness process S1 is stored in the area (■) of the memory area J3 for channel ion implantation in the later channel injection process S4. 1” depending on the presence or absence.

For example, set the MO8FIDT to 11#, which has a threshold value that does not turn on with the iJ1 rich bias by performing JP colon ion implantation at high speed, and set the MOSFET that does not perform channel ion madness to 0". do.

In the area ■, the feeding information @i from the set Jf value of the oxidation conditions of the field oxidation process s2 is written as "1" llo, whether or not channel ion implantation is performed in the channel ion implantation process s4, as in the area ■. It's crowded.

After this series of steps, the source 6 and drain 7 are formed by, for example, arsenic ion implantation (process S, 6
). Then, a CVD oxide film 8 is deposited on the entire surface (norocess 7).
), contact hole 9 is formed (norocess SR), k
Place area wiring JO using l etc. (Norocess s9)
.

In the above process 8vC, in the area ■ of the memory area 13,
The deviation information of the oxidation conditions from the designed value in the dirt oxidation process S3 is written as III'', '0'' depending on the presence or absence of a contact hole in the contact hole formation process S8. For example, fvlIO8 with no contact hole formed and therefore no current flowing even if a bias is applied.
MO with FET of 11# and contact hole formed
Let SFET be 0#. In the area (■), information about the deviation from the design value of the ion implantation conditions in the channel ion implantation process is entered as 1. '1'' *On depending on the presence or absence of the drain wiring in the metal wiring process S9. This information is stored by setting the Q/10sFET, which has no current and therefore does not allow current to flow even when a bias is applied, as 1#, and the MOSFET with a predetermined metal wiring as "'0".

°'1", '
The element structure of θ'' is summarized in FIG.

In this way, each of the areas (1) to (2) fixedly stores deviation information from the design value of processing conditions of the inexpensive Noroseth as a ROM. After this, integrated circuit chips are cut out from the wafer. That is, the chips are divided. In order to operate the 12 circuit bodies of the integrated circuit chip, the information in this memory area 13 is exported to the outside, and based on this FW information, the operating conditions of the chip, the source pressure, the substrate/ ? bias, changes the period and phase of the clock.

This makes it possible to easily compensate for variations in the operating characteristics of the integrated circuit body 12 due to manufacturing process and meter variations.

Areas ■ to ■ can be configured with 1 bit each so that "1" and '0' are stored depending on whether or not the tolerance +i is exceeded, as in the case of the dart length described later, but detailed control is possible. In order to have this, it is best to configure it with multiple bits.If each area is configured with 8 M5FETs, it will be 8 bits.For example, if you want to store it fixedly as a difference of 1JiIi, you can set the dart acid ratio film thickness. For example, for the design value of 200x, the case of -150X is "0001)0001"
, -14-o, l as "00000010", etc., and the deviation of e or ■, or the deviation 0 (-pyro) is stored in the parent turn. It is also possible to permanently store the actual processing conditions as they are. In each region (1) to (2), for example, a gate and a source wiring are common, and a voltage of, for example, 5V is applied to the source to form a memory region 13. Then, when the valley dirt is input to the switch and arm, it is connected to the first control grid via a delay circuit that switches the switch selected at predetermined time intervals, and the drain is also grouped into corresponding bits in each area. , this may be connected to one resistor/f rad via a switch, and the drain switch may also be connected to the second control pad via a delay circuit. That is, while detecting the drain pressure vD with the readout frad, the first. When a pulse is applied to the second fl+II control and rad, 1# and ``0# of each IViO8FET become 1.
(You can get the information from a chip by giving you the μ next letter.

The switch can also be controlled by a decoder.

For example, in the above example, regions (1) and (2) are nine rammeters for varying the threshold value. If it is read from the memory area 13 that the dirt oxide film is as set as the value d1 and the channel ion implantation is 8 times less than the designed value, this corresponds to a 0.5V drop in the threshold voltage, so the substrate's 1-3V
to -3,25V, i.e. substrate bias (source...
In order to increase kO (expressed as a reverse bias value from ground) by 25V, change the pressure applied to the chip's substrate, IA, and IA, or use a signal to control the substrate bias.
Give a signal to Grado to activate the chip.

This prevents (~threshold oscillations. Area ■.

■If a deviation is detected from both sides, add the amount of change. Touseiyama (2.1 field ion implantation, field oxidation 1 cow) can also be read out outside the meeting and operated optimally. In addition, the memory area 13 contains 6.
It is also possible to permanently store information regarding the dart length of 0SF'ET. Dart length chopper IJ is used for dart machining (s5
) Varies depending on no-over etching time (= undercut eagle). In this case, the fixed record method shown in area ■l■ in FIG. 5 can be applied for the process. For example, the overetching time is increased. For example, when it is found that the J5 silicon groove length is 0.2μ shorter than the 81 value of 1.2μ, the voltage should be increased to prevent the drain voltage from causing a negative effect and the generation of hot electrons. 5v to 4.6V, and to this, the train voltage v5v is reduced by 4.6v vc. Since the dart length also affects the threshold value, the substrate bias is changed in the same way as described above.

In the above embodiment, the process parameter memory area 13
This information was once exported to the outside of the chip to instruct changes to the operating conditions, but we proceeded further to move to operation 5P! It is desirable to automatically change the distance within the chip. The second embodiment will be explained with reference to FIG. 6. Figure 6 schematically shows the Sakaki development of the entire integrated circuit chip.
In addition to the integrated circuit main body No. 2 and the same process, main meter, and memory 'trQN<13 as in the previous example, Case 1 circuit 14. Standard table 5. Detection circuit J6 and drive circuit 17 are included. Standard table No. 5 records information on how much the processing and machining conditions of each mounting floss deviate from the design 11, and how much the operation conditions will be changed.1. I regret it. Further, the drive circuit 17 incorporates a circuit that changes all the operating conditions of the integrated circuit main body 12.

As this simple configuration, when the circuit chip purple is operated,
City II fill l! ! I/J4 reads out the 1H information from memory head J3, reads the contents of the 1H information from standard table No. 5, and supplies it to drive circuit J7. Due to this, the integrated circuit h'6 main body 12 is automatically set to the optimum M without any operation from outside the chip.
It can be operated with J-Sakuei condition.

Memory 1 reconnaissance area 3 dirt oxidation, channel ion implantation r
(The operation will be explained for the case consisting of the above ① and ②. In other words, in the process/zerameter memory area 13,
If so, 8-bit information is fixedly recorded as deviation information such as the Gutron ratio, the deviation of channel ion implantation (1) or e, or the deviation of 0. An actual circuit array is shown in FIG. Here, the MO8FgT in the area ■, ■08 bits is
It is constructed by connecting the gate Gs+Ga and the source wiring in common. Further, the source wiring between ■ and ■ is commonly connected and 5V is applied. Further, the drain wirings of the corresponding bits are commonly connected, and the D1% and D8 terminals are provided. Hereinafter, explanation will be given with reference to the flowchart of FIG. 8. The music J rise circuit 14 turns on the memory area.

That is, G is turned on. Next, the detection circuit J6 detects D.

～Start all drain voltages of D8 at once～to 1 +
″.

II Read from the 8-bit information area (■) of O#. The control circuit 14 takes in the deviation information generated by the detection circuit 6, extracts circuit operation change information corresponding to this deviation from the standard table 15, and latches it into the latch circuit 18. If it is correct, the amount of change in substrate bias +0.2v is latched. The latch circuit! IjI11 Process for determining merits: Not necessary if there is only one meter. When the change amount corresponding to the area (■) is latched, the adjustment of the area (■) is performed in the same way.0Then, the control circuit 14 extracts the change amount corresponding to the VC from the standard daple 15 and adds it to the latched contents. Actual change) Make a decision. When such a change amount of 1a is given to the drive circuit J7 from the tlj control circuit 14, the drive circuit J7 accordingly deviates the substrate bias from the design value and supplies the substrate bias applied to the integrated circuit body 12. (The voting table 15 is made up of 1 piece of ROM, but in addition to the method of storing the changes in the areas ■ and ■ for >n times as described above, it is also possible to combine the information in the areas ■ and ■. On the other hand, it is also possible to try the change as described below.In this case, until the peaks and troughs of the area ■ are read out from the detection circuit J6, all latch circuits for all 16 signals read from the detection circuit 16 of the area ■ 18 is set to 2, and when both ``8'' reaches 110, the corresponding change amount is read out from the standard Cheagle J5.Also, the change is not recorded as an actual operating condition in the standard table number 5. 6 You can also leave it to 1. Ha.

Figure t1!9 is a diagram of the drive circuit J7, and shows a substrate bias generation circuit incorporating circuit elements that change the operating conditions.

691 showing the substrate bias generation circuit in FIG. 9(a):
Ring oscillator with AIJS inverter connected in several stages, 9.2a and 92b are clock generators,
93a and 93b are charge pump circuits.

When the drain voltage VDD and the source power supply voltage Vl18 are turned on, the oscillator 9 is activated.

If the phase is different, the two types of tilting oscillator outputs φA and φB are clocked into clock generators 92a and 92b.
When manually applied to each, the clock generator 92a,
Output waveform rr of valley output nodes Na and Nb of 92b! It is output with a phase of approximately 1800. Therefore, the capacitors Ca and Cb of the charge pump circuits 93a and 93b repeatedly charge and discharge each other to keep the output voltage VBB of the substrate bias generation circuit constant. Ca and cb
Takashi Tani is a temple.

FIG. 9(b) shows a device equipped with a CaK adjustment function.

The same applies to cb. In Figure 9 (b), in parallel with Kiya Gushita C1, Kya Gushita C2 + C3, which is sufficiently smaller than Kiya Gushita C1;, 1110SN'E
Connected via 'r. For normal operation, the timing φε is fully ON and C1+C2, when decreasing the capacitance, φc lr OFF, and when increasing the capacitance, φC2φ
If both D are turned on, the substrate bias will be set. If you further increase the number of keys and bases, it will be finer 1lflJ 11I41
jI: The ink to be done is made.

In addition, 92a and 92b in the lower row of FIG. 9(,).

93a #93b may be prepared, the node vBB may be set in common, and the number of blocks connected to the node VBnVcm by an appropriate lock may be changed.

Changing the operating conditions can be completed in a short time, so it can be started at the same time as the power is turned on to the integrated circuit main body J2, or it can be latched until the changing of the operating conditions of the drive circuit 17 is completed, and then the change can be made from the drive circuit. Power may be supplied to the integrated circuit body 12 at the same time as the substrate bias is supplied to the integrated circuit body 12. - If the power supply voltage manually applied from the motherboard is changed according to the present invention, the former method is the same.

In this example, compensation of the threshold voltage based on dirt oxidation and channel ion implantation conditions was explained as an example, but as in the previous example, in addition to this, field ion implantation,
Other process parameters such as field oxidation, gate length, etc. can also be implemented.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications. For example, if the integrated circuit uses a multilayer dart structure,
MOSFET with first layer dirt as a mnemonic for parameters
The threshold information of the ET can be stored in the MOSFET of the second layer DART, and the threshold information of the MOSFET of the second layer DART can be stored in the MOSFET of the third layer DART.

FIG. 10 shows an embodiment of such a stacked integrated circuit. That is, the first layer IC5o is formed on the St substrate, an insulating film is deposited thereon, a semiconductor film is formed thereon, this is made into a single crystal by beam annealing, and the 21st fiIC is formed thereon.

Similarly, the (N-1)th layer IC51 and the eighth layer IC5
Up to 2 are formed. Each layer includes a process parameter memory area (mask ROM) 501 . . . 511 , 521 and an optimum operation circuit 502 . ...512,522.

The optimal operation circuit is composed of the control circuit 14) standard table 15, detection circuit 16, drive circuit 17, and latch circuit 18 described in FIG. In this embodiment, in the process parameter memory area of each layer, process information from the first layer IC to that layer is fixedly stored in the manner described in FIG. For example, the above-mentioned substrate bias and voltage are process information related to voltage. Also, the standard table is the same as FIG. 6 in that the amount of change in operating conditions corresponding to process information is fixedly stored. Basically, the operating conditions for each layer are set as described in FIG. However, when one circuit block is divided into multiple layers, it is necessary to match operating conditions. For example, ``The power supply voltage must be shared. Therefore, when one circuit block is divided into an (N-1) layer and an (N-3) layer IC, the optimal operating conditions are controlled in the (N-1) layer. That is, since the process information of the (N-3) layer is also fixedly stored in the main meter memory area of the (N-1) layer, the detection circuit 16 in the (N-1) layer
The process information of the (N-3) layer is read from the standard table 15, and the amount of change is read from the standard table 15, and this is sent to the latch circuit 18.
Latch it to . Next, from the detection circuit 16 (N-
1) Read the process information of the layer. Control circuit 14
The amount of change is read from the standard table 15 via. Both amounts of change are then combined (averaged) in the control circuit 14. The above is performed in the meter memory area 511 and the optimal operation circuit 512 of the (N-1) layer. Then, the amount of change in the synthesized operating conditions is sent to the drive circuit 17 of the optimal operation circuit 512 of the (N-1) layer for the (N-1) layer, and to the drive circuit 17 of the optimal operation circuit 512 for the (N-3) layer. The voltage is applied to the layer drive circuit so that the (N-1) layer and the (N-3) layer have the same operating conditions. For example, set the power supply voltage.

Which layer and which layer should be used to form a circuit block may be programmed in advance into the control circuit as described above.

Further, in this embodiment, from the (N-1) layer control circuit 14 to (
The amount of change is transmitted to the drive circuit of the (N-, 3) layer, but the power supply line of the (N-3) layer is drawn into the drive circuit 17 of the ('N-1) layer in advance, 3) The power supply voltage of the layer may be directly controlled from the (N-1) layer.

In this way, the method of matching operating conditions when layers are separated can also be applied when building an integrated circuit in which the circuit changes over time, such as a microprocessor, using a multilayer integrated circuit. For example, when a circuit block consisting of (N-1) and (N-3) layers changes over time to a circuit block consisting of (N-1) and (N-2) layers, each time All you have to do is set the amount of change in the operating conditions. Process parameter memory areas according to such a matching method can be stored in different layers, for example (
The information on the (N-1) layer may be fixedly stored in the (N-1) layer, and the information on the (N-3) layer may be fixedly stored in the process parameter memory area of the (N-3) layer.

Although the above embodiment shows a case in which information about a skipped layer is fixedly stored, information about that layer and the next layer below may be fixedly stored in the process parameter memory area. In this case, the operating conditions of only adjacent layers are matched. stop"
In C1 data processing, only signal lines and 9 are performed between ICs with skipped layers. Other stacked integrated circuits can be implemented with various modifications. For example, N
It is also possible to store only the information of the N-m-1 layer in the -m layer (the top layer is used as a pad area and no circuit IC is made), and to change the operating conditions from the layer one layer above. Furthermore, information regarding the crystallinity of the semiconductor and the interface level between the semiconductor and the gate barrier film can be stored. In history, a test MO8FET was made in the (N-1) layer, and after the electrodes of the (N-1) layer were formed, the threshold value was actually measured, and this threshold information was used as the process parameter for the N layer. It can also be fixedly stored in a memory area.

Above are some examples of rice. For example, the fixed storage in FIG. 5 is performed using a mask ROM method.

For example, dirt oxidation, channel ion implantation, contact hole opening, and the presence or absence of wiring can be determined by applying resist to the wafer and forming a mask A turn on it by direct writing using an electron beam or direct writing using an ion beam. It is possible. Furthermore, channel ion implantation can also be performed by directly implanting scanning ions into the channel. Alternatively, only the mask ROM area may be directly drawn, and the rest may be formed using a photomask.For example, when forming contact holes, after forming the contact holes in the integrated circuit body, the mask is replaced and the contacts in the mask ROM area are formed. A hole may be opened. In addition, the process parameter information for each process is temporarily stored in an external storage device, and in the process closest to the end of the manufacturing process, such as the contact hole forming process, all processes are stored together as fixed memory in the chip depending on the presence or absence of a contact hole. You can also do that. At that stage, external storage is no longer required and long-term storage of process parameters is no longer necessary. In this case, "1", "O" in the area ■ to ■ of the example
The element structure representing , is the same K. Furthermore, permanent storage can also be achieved by burning out the wiring with a laser after all steps of integrated circuit manufacturing are completed.

Next, we will discuss the uniqueness of the information regarding the differences between the Zorosesno maternal maternity meters. If there is no substantial difference in the degree of difference depending on location within the wafer, the same information may be stored in all chips within the wafer. If there is a difference within the wafer, the difference may be divided into stages, the wafer may be divided accordingly, and the same information may be stored in chips within the same division.

In addition, the information fixedly stored in the process parameter memory area is not limited to the above example, but the amount of change in the actual operating conditions or the operating conditions themselves may be used as information regarding deviations in the actual processing conditions of the integrated circuit manufacturing process. It is also possible to permanently store data in the process parameter memory area. In this case, the standard table 15 in FIG. 6 becomes unnecessary.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an integrated circuit chip according to an embodiment of the present invention;
Fig. 2 shows the process parameters and memory area, Figs. 3 and 4 show the manufacturing process of the MO8 integrated circuit of this example, and Fig. 5 shows the element structure of the memory area of Fig. 2. 6 is a diagram showing the configuration of another embodiment of the present invention, FIG. 7 is an equivalent circuit diagram of the memory area, FIG. 8 is a flowchart showing the operation of the embodiment of the present invention, and FIG. 9 is a diagram showing the configuration of another embodiment of the present invention. A circuit diagram of the drive circuit, FIG. 10 is a perspective view illustrating another embodiment of the present invention. 1 No.. Integrated circuit chip, 12.. Integrated circuit body,
13... Process parameter memory (ROM) area, 14... Control circuit, 15... Standard table, 16...
...Detection circuit, 17...Drive circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 5rX1 Figure 6r■

Claims (1)

[Scope of Claims] (1) Chip information regarding the actual processing conditions of the integrated circuit manufacturing process or deviations from their design values is written on a semiconductor chip on which an integrated circuit is formed in a fixed manner. (2) A semiconductor integrated circuit device characterized by the provision of a ROM area. (3) A ROM in which chip information regarding actual processing conditions of the integrated circuit manufacturing process or deviations from design values is written as a fixed memory in a semiconductor chip on which an integrated circuit is formed. (4) Actual processing of integrated circuit manufacturing process. A patented device characterized in that chip information regarding deviations of processing conditions from design values is a chip operating condition head corrected based on the deviation or a half that is a change cover thereof. (5) A semiconductor on which an integrated circuit is formed. The chip has a process parameter memory area consisting of i''{CMJ, which stores chip information regarding the actual processing conditions of the integrated circuit manufacturing process or deviations from its design values as fixed memory, and this process parameter memory area. A detection circuit reads out the stored contents from the memory area, and a detection circuit that reads the stored contents from the memory area and a
The operating conditions of the chip corresponding to the memory contents read out from the Rom H area and the Rom H area in which the operating conditions of the tyranno or the amount of change thereof are stored for each value read out from the ROI [area are stored. 44. A semiconductor integrated circuit device characterized by having a circuit IA function and a circuit IA function that adjusts the operating condition of the chip according to the read operating condition or its parent history. (6) 4J integrated circuit through an insulating layer! ．． Multiple levels of chip 1# information regarding the actual processing conditions of the integrated circuit manufacturing process or deviations from their design values are written as fixed memory in a semiconductor chip in which a stacked integrated circuit is formed by providing several layers. However, a ROM area formed across the same layer or different layers, and a circuit function for adjusting the operating conditions of the integrated circuit chip based on the chip information of this ROM area are provided, and the integrated circuit of the multiple layers is provided with a circuit function that adjusts the operating conditions of the integrated circuit chip. A semiconductor integrated circuit device characterized in that operating conditions are set in a consistent manner.