JPS60152025A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60152025A
JPS60152025A JP807684A JP807684A JPS60152025A JP S60152025 A JPS60152025 A JP S60152025A JP 807684 A JP807684 A JP 807684A JP 807684 A JP807684 A JP 807684A JP S60152025 A JPS60152025 A JP S60152025A
Authority
JP
Japan
Prior art keywords
film
substrate
recess
mask
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP807684A
Other languages
Japanese (ja)
Inventor
Akio Nakamura
彰男 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP807684A priority Critical patent/JPS60152025A/en
Publication of JPS60152025A publication Critical patent/JPS60152025A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02579—P-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To form a recess having favorable productivity when a buried region is to be formed at manufacture of a semiconductor device by a method wherein the recess is formed by etching previously a substrate using the mask pattern of the buried region thereof. CONSTITUTION:A silicon dioxide film 2 is formed as a film 2 for mask on the surface of a P type silicon substrate 1. Then an opening is provided to the film 2. Then the surface of the substrate 1 is etched using the film 2 as a mask to form a recess 5. After then, an N<+> type impurity region 3 is formed selectively at the position of the recess 5. Then the film 2 is removed, and a P type epitaxial growth layer 6 is formed on the surface of the substrate 1 and the region 3. A recess 5 appears nearly in the same shape reflecting the shape of the surface of the substrate on the surface of the layer 6. Accordingly, the recess 5 thereof can be utilized as a mark for mask alignment at the next process.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、埋込み領域を有する半導体装置の製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a buried region.

従来例の構成とその問題点 一般に、半導体集積回路装置の製造過程で、例えば、Ｐ
型半導体基板にＮ＋型の埋込み領域を形成するＫは、予
め、Ｐ型半導体基板にＮ＋型の不純物を拡散導入したの
ち、この基板上にエピタキシャル成長層を形成する工程
が用いられる。この場合、次工程で、エピタキシャル成
長層に能動領域を形成するマスク合せのために、同エピ
タキシャル成長層の表面から、埋込み領域の面積が認識
できることが必要である。Conventional configurations and their problems In general, in the manufacturing process of semiconductor integrated circuit devices, for example, P
To form an N+ type buried region in a type semiconductor substrate, a process is used in which an N+ type impurity is diffused into a P type semiconductor substrate in advance, and then an epitaxial growth layer is formed on this substrate. In this case, it is necessary to be able to recognize the area of the buried region from the surface of the epitaxial growth layer for mask alignment to form an active region in the epitaxial growth layer in the next step.

従来例では、この認識手段として、第１図ａ〜ｄの工程
順断面図で示すように、基板の一部に窪みを設ける方法
がとられていた。すなわち、第１図ｄのように、例えば
、Ｐ型半導体基板１０表面に絶縁膜、例えば、第１の二
酸化シリコン膜２を形成し１次いで、この二酸化シリコ
ン膜２に、第１図すのように、所定面積の開口を形成し
、この開口を通して、Ｎ＋型不純物領域３を選択的に形
成する。次に、熱酸化法によって、半導体基板の全域を
酸化処理することによって、第１図Ｃに示すように、熱
酸化生成膜、すなわち、第２の二酸化／リコン膜４を形
成する。このとき、Ｎ＋型不純物領賊３の表面が少し深
く酸化される条件に設定される。そして、第１図ｄのよ
う傾、第１および第２の二酸化シリコン膜を除去するこ
とにより、Ｎ＋型不純物領域３の表面部に窪み５を形成
し、この上に、Ｐ型エピタキシャル成長層６を形成する
と、窪み５がエピタキシャル成長層６０表面に現われる
。In the conventional example, as this recognition means, a method has been adopted in which a depression is provided in a part of the substrate, as shown in the step-by-step cross-sectional views of FIGS. 1A to 1D. That is, as shown in FIG. 1d, for example, an insulating film, for example, a first silicon dioxide film 2 is formed on the surface of the P-type semiconductor substrate 10, and then this silicon dioxide film 2 is coated with a film as shown in FIG. An opening with a predetermined area is formed, and N+ type impurity region 3 is selectively formed through this opening. Next, the entire area of the semiconductor substrate is oxidized by a thermal oxidation method to form a thermal oxidation film, that is, a second dioxide/recon film 4, as shown in FIG. 1C. At this time, conditions are set such that the surface of the N+ type impurity region 3 is oxidized a little deeper. Then, by removing the first and second silicon dioxide films at an angle as shown in FIG. Once formed, depressions 5 appear on the surface of epitaxial growth layer 60.

吉ころで、上述の従来法によれば、窪み５を形成するた
めに、基板１の熱酸化処理が不可欠であり、とりわけ、
段差の大きい窪みを得るためには、熱酸化処理条件を複
イイｆに制御しなければならないので、製造工程の管理
が煩わしく、製造能率を低下さぜるという間）１η点が
ある。Fortunately, according to the above-mentioned conventional method, thermal oxidation treatment of the substrate 1 is indispensable in order to form the depressions 5, and in particular,
In order to obtain a depression with a large step difference, the thermal oxidation treatment conditions must be controlled in multiple ways, which makes the management of the manufacturing process troublesome and reduces the manufacturing efficiency.

発明の目的 本発明は、上述の従来例にみられた問題点を解消するも
のであり、製造外よく、エピタキシャル成長層上に窪み
を形成する半導体装置の製造方法を提供するものである
。OBJECTS OF THE INVENTION The present invention solves the problems seen in the above-mentioned conventional example, and provides a method for manufacturing a semiconductor device in which a recess is formed on an epitaxially grown layer even outside the manufacturing process.

発明の構成 本発明は、要約するに、半導体基板の表面に、開口を有
する絶縁膜のマスクを形成し、前記開口を通して、前記
半導体基板の表面を選択的に食刻する工程、前記絶縁膜
のマスクを介して、所定の不純物を導入して、同開口部
に所定の不純物領域を選択的に形成する工程、および前
記絶縁膜のマスクを除去したのち、前記半導体基板上に
エピタキシャル成長層を形成する工程をそなえた半導体
装置の製造方法であり、これにより、食刻工程でその食
刻の深さを制御するだけで、所望の窪みが得られ、エピ
タキシャル成長層表面での狸込み領域の認識が容易に可
能である。SUMMARY OF THE INVENTION In summary, the present invention comprises a step of forming an insulating film mask having an opening on the surface of a semiconductor substrate, and selectively etching the surface of the semiconductor substrate through the opening; A step of introducing a predetermined impurity through a mask to selectively form a predetermined impurity region in the opening, and after removing the insulating film mask, forming an epitaxial growth layer on the semiconductor substrate. This is a method for manufacturing semiconductor devices that includes a process, whereby a desired depression can be obtained by simply controlling the depth of the etching process, and it is easy to recognize the etched areas on the surface of the epitaxial growth layer. possible.

実施例の説明 第２図ａ−ｄは、本発明実施例の二［稈順断面図であり
、同図を参照して、本発明を詳しく述べる。DESCRIPTION OF THE EMBODIMENTS Figures 2a to 2d are cross-sectional views of an embodiment of the present invention, and the present invention will be described in detail with reference to the figures.

まず、第１図のように、Ｐ型シリコン基板１の表面に、
マスク用被膜、例えば、二酸化シリコン膜２を２０００
人〜１００００人の厚さに形成する。First, as shown in FIG. 1, on the surface of a P-type silicon substrate 1,
A film for a mask, for example, a silicon dioxide film 2, is
Form to a thickness of 10,000 to 10,000 people.

ここで、マスク用被膜としての二酸化シリコン膜２は、
窒化／リコン膜あるいはレジスト膜で置き換えることも
できる。Here, the silicon dioxide film 2 as a mask film is
It can also be replaced with a nitride/resist film or a resist film.

つきて、第２図すのように、二酸化シリコン膜２に所定
の開Ｌ１を形成する。この開口形成には、通常の）Ａト
リノグラフィ技術が利用され、例えば、７オトレジスト
膜マスクを用いて、二酸化シリコン膜２を、ぶつ酸系の
食刻液により、もしくけ、塩素系のガスにより、選択的
に開口する。Then, as shown in FIG. 2, a predetermined opening L1 is formed in the silicon dioxide film 2. To form this opening, the usual (A) trinography technique is used. For example, using a 7-photoresist film mask, the silicon dioxide film 2 is etched with a butic acid-based etching solution, and then with a chlorine-based gas. , selectively opening.

次いで、第２図Ｃのように、二酸化シリコン膜２をマス
クにして、その開口下のＰ型シリコン基板１の表面を、
酢酸系の食刻液により、もしくは、塩素系のガスにより
、深さ約５００人〜３０００人に食刻して、窪み５を形
成する。その後、イオン注入法および拡散法によって、
同窪み５の位置にＮ＋型不純物領域３を選択的に形成す
る。この不純物導入工程でも、二酸化シリコン膜２は不
純物導入阻止のマスク材になる。Next, as shown in FIG. 2C, using the silicon dioxide film 2 as a mask, the surface of the P-type silicon substrate 1 under the opening is
The recesses 5 are formed by etching to a depth of approximately 500 to 3,000 depths using an acetic acid-based etching solution or a chlorine-based gas. After that, by ion implantation method and diffusion method,
An N+ type impurity region 3 is selectively formed at the position of the depression 5. In this impurity introduction step as well, the silicon dioxide film 2 serves as a mask material for preventing impurity introduction.

次に、二酸化シリコン膜２を除去して、Ｐ型シリコン基
板１およびＮ＋型不純物領域３の全表面に、Ｐ型エピタ
キシャル成長゛層６を形成する。これにより、Ｐ型エピ
タキシャル成長層６０表面にけ、基板面の形状を反映し
て、窪み５がほぼ同形で現われる。したがって、この窪
み６を、次工程におけるマスク合せマークとして利用す
ることにより、正確なマスク合せが可能である。Next, silicon dioxide film 2 is removed and a P-type epitaxial growth layer 6 is formed on the entire surface of P-type silicon substrate 1 and N+ type impurity region 3. As a result, the depressions 5 appear on the surface of the P-type epitaxial growth layer 60 in substantially the same shape, reflecting the shape of the substrate surface. Therefore, by using this depression 6 as a mask alignment mark in the next step, accurate mask alignment is possible.

発明の効果 本発明によれば、半一導体基板の所定表面に埋込み領域
を形成する際に、そのマスクパターンを用いて、同基板
を、予め、食刻して、これに窪みを形成しておくことに
より、この上に形成されるエピタキシャル成長層にも、
同形パターンの窪みが現われる。したがって、この窪み
を基礎に埋込み領域の平面位置を確認することができ、
これを次工程のマスク合せに利用するととア（できる。Effects of the Invention According to the present invention, when forming a buried region on a predetermined surface of a semiconductor substrate, the substrate is etched in advance using the mask pattern to form a recess in it. By placing the
A hollow pattern of the same shape appears. Therefore, the planar position of the embedded area can be confirmed based on this depression.
This can be used for mask matching in the next process.

本発明の方法は、単に食刻工程を導入するのみであり、
製造性において、従来例の酸化処理工程より、はるかに
簡単であり、実効性が犬である。The method of the present invention simply introduces an etching step,
In terms of manufacturability, it is much simpler and more effective than the conventional oxidation treatment process.

明実施例の工程順断面図である。FIG. 3 is a step-by-step cross-sectional view of a bright example.

１・・・・・Ｐ型シリコン基板、２・・・・・・二酸化
シリコン１７；４．３　Ｎ＋型不純物領域、４・・・・
熱酸化生１人（−門セ化シリコン）１１莫、６・・・・
・窪み、６・・・・・・Ｐ型−１−ビタキンヤル成長層
。1... P type silicon substrate, 2... Silicon dioxide 17; 4.3 N+ type impurity region, 4...
Thermal oxidation 1 person (-monochemical silicon) 11 mo, 6...
- Hollow, 6...P-type-1-Vitaquinyal growth layer.

代１ｊ１１人の氏名　弁３１１１士　中　１−Ｆ、敏　
男　ほか１名品　１　（２）Names of 11 1st graders Ben 3111 Junior High 1-F, Satoshi
Man and 1 other masterpiece 1 (2)

Claims (2)

【特許請求の範囲】[Claims] （１）半導体基板の表面に、開口を有する絶縁膜のマス
クを形成し、前記開口を通して、前記半導体基板の表面
を選択的に食刻する工程、前記絶縁膜のマスクを介して
、所定の不純物を導入して、同開口部に所定の不純物領
域を選択的に形成する工程、および前記絶縁膜のマスク
を除去したのち、前記半導体基板上にエピタキシャル成
長層を形成する工程をそなえた半導体装置の製造方法。(1) A step of forming an insulating film mask having an opening on the surface of the semiconductor substrate, selectively etching the surface of the semiconductor substrate through the opening, and etching a predetermined impurity through the insulating film mask. and selectively forming a predetermined impurity region in the opening, and forming an epitaxial growth layer on the semiconductor substrate after removing the insulating film mask. Method. （２）食刻の深さが、５００人〜３０００人でなる昔ｒ
Ｕ請求の範囲第１項に記載の半導体装置の製造方法。(2) In the past, the etching depth was between 500 and 3000 people.
A method for manufacturing a semiconductor device according to claim 1.
JP807684A 1984-01-19 1984-01-19 Manufacture of semiconductor device Pending JPS60152025A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP807684A JPS60152025A (en) 1984-01-19 1984-01-19 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP807684A JPS60152025A (en) 1984-01-19 1984-01-19 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60152025A true JPS60152025A (en) 1985-08-10

Family

ID=11683244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP807684A Pending JPS60152025A (en) 1984-01-19 1984-01-19 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60152025A (en)

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