JPS60150137A - Microcomputer system - Google Patents

Abstract

PURPOSE:To reduce the variations of the circuit state inside a microcomputer system consisting of a CMOS.IC and to reduce the power consumption, by reducing the speed of the clock which is given to a CPU while an idle routine is executed. CONSTITUTION:An address monitor circuit 5 decides the execution of an idle routine and delivers this execution mode to an AND gate 10 when the address which is presently executed by a CPU2 is within the upper and lower address ranges set by dip switches 8A and 8B. Thus an address bus 4 of the CPU2 is monitored by the circuit 5 and at the same time high-speed and low-speed clocks are produced from a clock generating circuit 6 according to the monitor result. In other words, a switch circuit 7 which switches the output of the circuit 6 is controlled by the output of the circuit 5. Then the speed of the clock supplied to the CPU2 is reduced while the CPU2 is executing a program of a low priority like a case where the CPU2 is executing an idle routine. This can reduce the variations of the circuit state as well as the power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a microcomputer system comprised of a CPU and its peripheral circuitry.

(Background Art) In a general microcomputer system, its peripheral circuits are usually configured with TTL, but in order to achieve low power consumption, the peripheral circuits including the CPU must be configured with CM'0.
8-IC is commonly used. When such a CMO8 IC is used, since it is voltage-driven, it consumes almost no power to maintain a certain state, and the goal of reducing power consumption can be effectively achieved. However, on the other hand, there is a problem in that a relatively large amount of power is consumed when the internal state of the circuit changes.

On the other hand, in a conventional microcomputer system, as shown in Fig. 1, a clock of about IOMHz is normally generated from a few MHz to IOMHz in the case of a fast clock.
) is supplied to the CPU 121, and this CPU
The data bus (3) and atreo bus (4) of f21 are configured to be coupled to a peripheral circuit section (not shown). In this way, since the input clock of the CPU (21) is fast, the operating speed of the CPU (21) is fast, and the state IΩ changes inside the circuit occurs frequently. Even if a circuit was constructed using the above, there was a problem in that it was not possible to achieve a sufficiently low power consumption.

(Purpose of Starting Point 1) The present invention provides a system for the purpose of
For example, by slowing down the speed of the θ torque applied to the CPU while executing an idle routine when the system is not doing anything, changes in the circuit state inside the system composed of CΔ■O8 ICs can be reduced. The object of the present invention is to provide a microcomputer system that achieves low power consumption.

(Disclosure of the Invention) (Embodiment 1) Embodiment 1 of the present invention shown in FIG. Generate a seed clock
A check generation circuit (6) is provided, and the address monitoring circuit (6) described above is provided.
By controlling the switching interval 1i'J[71 that switches the output of 6), the CPU (21 is running a program with a low priority) as if it were running an idle routine. In this case, the clock input to the CPU (2) K is slowed down.The address monitoring circuit (5) includes DZ switches (8A) and (8B) for setting the upper and lower limit values of the address, respectively. , comparators (9A), (9B) and S that compare the outputs of these dip switches (8'A) and (8B) with the address value on the address bus (4), respectively, and a comparator for both of them ( It consists of an AND gate (10) that produces an output only when an output is produced from 9A) (9B), and the address currently being executed by the CPU [21] on the address bus (4) is connected to both DIP switches. (8A) (8B)
When the address is within the upper and lower limit address range set in It is something that occurs. Next, the D-tock generation circuit (6) not only directly outputs the output of the D-tock generator (1) as in the conventional example, but also divides the output of this clock generator (tl) by a counter (river) to generate a low-speed clock. Both outputs of this clock generation circuit (6) are input to the switching interval btd7). 9+ replacement circuit (7) is gate circuit θ 03)
,! - an inverter (14);
U (While 2+ is running a program with low priority, C
The output of the PU (21 is input to the counter (low speed output), and the CPU (2) is operated at low speed; otherwise, the output of the d 0 output is input to the generator it). CP [ 1t2) and CPU t2)
operates at normal operating speed.

Here, I will explain idle routines (+:, Normally, computer system programs are created to perform a series of tasks using some kind of human power, but for example, when there is no input, idle routines are as “
f. “I don’t do anything.”

It looks like you are running Crum. However, even during the execution of such an idle routine, the CPU (
Since the 21 itself is performing a block operation based on this idle routine, it consumes the same amount of power as when it is performing some actual processing operation. When running low-priority idle routines like this idle routine, it is wasteful to consume the same amount of power as normal, so we reduce the clock speed and
Power consumption is reduced by slowing down the processing speed of the PU (2).

(Embodiment 2) FIG. 3 shows Embodiment 2 of the present invention, in which the above-mentioned Embodiment 1 is replaced with a low-priority "jO sill" such as an idle routine when dip switches (8A) and (8B) are used. The address range of Party B is set in advance, and when the address on the address bus (4) falls within this address range, the CPU (2)
In contrast, in this second embodiment, the CPU (2
) NozuOjiram operation itself sets a programmable range with a low priority such as an idle routine, and when the CPU f2+ performs a zero programmation operation of the Konozurojiram range, it is input to the CPU (21). However, in the circuit W of the second embodiment shown in FIG. An I10 port (15) is provided to input the WT multiplier signal to realize the above operation.
The logic ram itself outputs a 0-switching signal, and immediately before this process ends, it operates to eliminate the 0-switching signal.

(Embodiment 3) FIG. 4 shows a third embodiment in which no occurrence occurred. In the above-mentioned embodiment 2, when an interrupt is made to CPUf21, for a certain period of time from the time when this interrupt signal is input, for example, Even if the input state is low speed and low speed, the low speed is switched to the high speed side. However, in the circuit shown in FIG. 4, when an interrupt is made to the CPU [2+], the interrupt response signal output from the CPU (2) is input to the one-shot circuit (+) and its output is opened only at a predetermined time. %L".For this reason, even if the I10 boat (the national output is ttH) and the switching circuit (7) is switched to the low speed side, the output of the AND gate 07 will be "1, 1, 3.
The output of the cut circuit θ6) becomes 1L only during -L“,
Therefore, only during this time, a high-speed signal is input to the CPU f21, and interrupt processing is performed at high speed.

(Effects of the Invention) As described above, the present invention enables the CPU and its peripheral circuits to be CM
In a microcomputer system configured with O5-IC, the CPU is
The CPU's operation processing speed is slowed down by inputting D-tsku to low-speed 0-tsuku, which reduces the changes in the circuit state of the circuits in the system during execution of low-priority z0jiram. This has the effect of achieving lower power consumption.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the conventional example, Fig. 2 is a block diagram of Embodiment 1 of the present invention, Fig. 3 is a block diagram of Embodiment 2 of the above, and Fig. 4 is a block diagram of Embodiment 3 of the same. (2)
CPU1+41 is an address bus. Agent Patent Attorney Ishi 1) Choshichi

Claims (1)

[Claims] fl) CPU and its peripheral circuitry are CMO8-IC
In a microcomputer system configured with C
It is equipped with a means for monitoring the address bus of the PU and determining the priority of the program being executed by the 1 CPU, and a means for generating a clock that generates high-speed and low-speed signals. While running the program, press C at low speed.
A microcomputer system characterized by operating a PU.