JPH0816389A - Arithmetic processor - Google Patents

Abstract

PURPOSE:To effectively reduce power consumption only at the time of executing specified instructions. CONSTITUTION:This device is provided with a storage part 3 equipped with an instruction storage area 3a for storing instructions and data storage area 3b for storing data, central arithmetic processing part (CPU) 1 for reading an instruction by outputting an address to this storage part 3 and for arithmetically processing the data based on this instruction, and access control part 2 for controlling the timing of reading from the storage part 3 to this central arithmetic processing part 1. Further, a delay circuit 4 is provided to delay the reading operation of the specified instruction of the central arithmetic processing part 1 just for prescribed time by outputting a read start timing signal when the address outputted from the central arithmetic processing part 1 is an address within the range of recording the specified instruction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device, and more particularly to an arithmetic processing device for reducing the power consumption of a memory element.

[0002]

2. Description of the Related Art Conventionally, as an arithmetic processing unit of this type,
For example, there is one as shown in FIG. In FIG.
The central processing unit (CPU) 51 synchronizes with a system clock (not shown), and the storage unit 53 and the weight control unit 5
7 and outputs an address start signal such as an address strobe for notifying that access has started to the access control unit 52 and the weight control unit 57, and after the period instructed by the weight control unit 57, the storage unit 5
The data output from 3 is read from the data bus.

The access control unit 52 receives an access start signal from the CPU 51, generates various control signals necessary for accessing the storage unit 53, and supplies the control signals to the storage unit 53.
Storage unit 53 receives the address sent from CPU 51 and the control signal sent from access control unit 52, and outputs the instruction code stored at the designated address to CPU 51 via the data bus. Weight control unit 5
In response to the address received from the CPU 51, 7 delays the reading of data from the data bus of the CPU 51 when the access is to a low-speed storage element that takes time to access.

Next, the operation of the arithmetic processing unit shown in FIG. 3 will be described. The CPU 51 incorporates an address register that is sequentially increased for each fetch cycle for reading an instruction code. In the fetch cycle, first, the contents of the address register are output to the address bus to generate an access start signal. Access control unit 52
Generates a control signal necessary for accessing the storage unit 53 based on this access start signal.

The storage unit 53 outputs the instruction code stored at the designated address to the CPU 51 through the data bus according to the address sent from the CPU 51 and the control signal sent from the access control unit 52. When the storage unit 53 includes storage elements having different access speeds, the weight control unit 57 determines the type of the storage element based on the address output from the CPU 51, and the CPU
Instruct 51 to read the data from the data bus.

As a technique for reducing the power consumption of such an arithmetic processing unit, for example, in Japanese Patent Laid-Open No. 4-251348, the clock supply to the CPU 51 is temporarily delayed at the time of memory access to wait for memory access (standby). Time) is disclosed.

[0007]

However, in such a power consumption reducing method for temporarily delaying the system clock, the arithmetic processing device includes a timer circuit which requires that the system clock has a constant frequency. However, there is an inconvenience that the measurement time is changed when the measurement is performed.

Further, in the case of a circuit which performs a dynamic operation, there is a limit to the frequency change of the system clock, so that the system clock cannot be slowed unless it is within the range, so that a sufficient power consumption reduction effect can be obtained. It was difficult to expect.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the inconvenience of the conventional example, and particularly to effectively reduce only the power consumption during execution of a specific instruction.

[0010]

Therefore, according to the present invention as set forth in claim 1, a storage unit having a command storage region for storing a command and a data storage region for storing data, and an address are output to this storage unit. Therefore, it is provided with a central processing unit that reads out the instruction and arithmetically processes data based on the instruction, and an access control unit that controls the timing of data transfer from the storage unit to the central processing unit. Moreover, when the address output from the central processing unit is an address in the range in which the specific instruction is recorded, the read operation of the specific instruction of the central processing unit and the output of the specific instruction of the storage unit The configuration is such that a delay circuit that delays the operation for a fixed time is provided.

According to the present invention of claim 2, the delay circuit comprises:
A decoding unit that decodes the address output from the central processing unit to the storage unit, and a weight control that outputs a read wait signal when the address output by this decoding unit is within the range in which a specific instruction is recorded. And a section. Moreover, the access control unit has a read control signal generation delay function for delaying the generation of the read control signal to the storage unit when receiving the read weight signal. Further, the central processing unit has a reading delay function of delaying the reading operation based on the reading weight signal when the reading weight signal is received.

According to the present invention of claim 3, the specific instruction is a waiting routine instruction for waiting an instruction from the outside.

The present invention aims to achieve the above-mentioned object by these means.

Here, the instruction means an execution procedure for driving and controlling the device driven and controlled by the arithmetic processing unit according to the present invention according to various conditions, and the data means various conditions and the driving control. The data handled by the device.

[0015]

According to the first aspect of the present invention, the central processing unit first outputs the address in which the data to be processed is recorded to the address bus and the access start signal to the access control unit. After receiving the access start signal, the access control unit controls the timing of data transfer from the storage unit to the central processing unit by outputting a control code required when the storage unit outputs data. The storage unit outputs the instruction or data stored in the address to the data bus according to the address and the control code. In this way, the central processing unit reads out the command by outputting the address to the storage unit, and processes the data based on the command.

During this operation, the delay circuit first acquires the address output by the central processing unit. Then, it is determined whether or not the acquired address is within the address range in which only a specific instruction is recorded. Further, when the address is within the specific address range, the read start timing signal is output to delay the read operation of the specific instruction by the central processing unit for a predetermined time. Therefore, the read speed of the instruction stored in the specific address range is reduced, and the number of memory accesses per unit time is reduced. On the other hand, because reading of commands and data belonging to other address ranges is not delayed,
Read at normal speed.

According to the present invention as set forth in claim 2, during the operation of the arithmetic processing unit, the decoding unit decodes the address output from the central arithmetic processing unit to the storage unit. The weight control unit outputs a read weight signal to the access control unit and the central processing unit when the address output by the decoding unit is within the range in which only a specific instruction is recorded. When receiving the read weight signal, the access control unit delays the generation of the read control signal in the storage unit. On the other hand, when the read weight signal is received, the central processing unit delays the read operation by the time (the number of clocks) based on the read weight signal. Therefore, the storage unit outputs the instruction stored in the address to the data bus at the delayed timing, and the central processing unit reads the instruction at the delayed timing.

According to the present invention of claim 3, the delay circuit comprises:
When the address output by the central processing unit is within the address range in which the standby routine command for waiting for an external command is stored, the reading operation of the central processing unit is delayed. Therefore, when the device controlled by the arithmetic processing device according to the present invention is waiting for some external command,
The read operation is delayed. Therefore, the number of memory accesses is reduced in the standby state, and the power consumption required to access the storage unit is reduced by the reduced number of accesses.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a block diagram of an arithmetic processing unit according to an embodiment of the present invention, and FIG. 2 is a timing chart showing an example of a fetch cycle.

The arithmetic processing unit according to the present embodiment has a storage unit 3 having a command storage area 3a for storing a command and a data storage area 3b for storing data, and outputs an address to the storage unit 3 to output the command. And a central processing unit (CP that processes data based on this command).
U) 1 and an access control unit 2 for controlling the read timing of the central processing unit 1 from the storage unit 3.

Moreover, when the address output from the central processing unit 1 is within the range where the specific instruction is recorded, the read start timing signal is output to output the specific address of the central processing unit 1. The delay circuit 4 delays the instruction read operation for a predetermined time.

The arithmetic processing unit of this embodiment shown in FIG. 1 has eight data buses and 16 address buses. Therefore, the storage unit 3 has an address space from address 0 to address FFFF in hexadecimal.

Of this address space, addresses 0 to 7F
The area up to the FF address is the instruction storage area 3a and is a read only memory (RO) in which a control program is written.
M) is mounted, while a random access memory (RAM) is mounted as the data storage area 3b in the area from the address 8000 to the address FFFF.

The CPU 1 of this embodiment, as shown in FIG.
In the case of a no-wait, the fetch cycle for reading an instruction is performed during four system clock cycles (T1, T2, T3, T4), and the CPUAS signal is generated in the latter half of T1, and T3
The data on the data bus is read at the rising edge of. When a wait signal is input, a wait signal (WAIT signal) is input to insert wait cycles Tw between T2 and T3 by the required number of cycles. Note that FIG.
In the figure, the broken line indicates the timing of the data (DATA) reading operation of the CPU 1.

Further, the CPU 1 has a built-in address register which is sequentially increased for each fetch cycle, and outputs the contents of the address register to the address bus at the head of the machine cycle.

The CPU 1 outputs an address to the storage unit 3, outputs an address and a CPUAS signal to the delay circuit 4, and outputs W from the delay circuit 4.
When the AIT signal becomes "L" level, the data output from the storage unit 3 is read from the data bus at the next rise of the system clock.

The access control unit 2 operates from the delay circuit 4 to the AS
When the signal is received, various control signals necessary for accessing the storage unit 3 are generated and supplied to the storage unit 3.

The storage unit 3 is a main storage unit composed of a part of ROM and RAM, and when the address sent from the CPU 1 and the control signal sent from the access control unit 2 are received, the designated address The instruction code stored in is output to the CPU 1 via the data bus.

The delay circuit 4 has a decoding unit 4A for decoding the address output from the central processing unit 1 to the storage unit 3, and a range in which the address output by the decoding unit 4 stores a specific instruction. And a weight control unit 4B which outputs a read weight signal when the address is. When receiving the address and the CPUAS signal from the CPU 1, the decoding unit 4A decodes the address and outputs it to the weight control unit 4B. In the weight control unit 4B, the address is from 7000 to 7F.
If it is between FF addresses, that is, if it is within the address range in which only a specific instruction is stored, as shown in FIG. 2, the withdrawal of the WAIT signal is delayed by 16 clocks to cause the CPU 1 to A wait of 16 clock cycles is inserted and the CPUAS signal is set to 1
It is delayed by 6 clock cycles and output as an AS signal to the access control unit 2.

If the address is any other address, the WAIT signal is withdrawn at the end of T2 so that no wait is performed and the CPUAS signal is directly output to the access control unit 2 as the AS signal.

The external interface (I / F) 5 transmits data from the outside to the CPU 1 and issues an interrupt request to the interrupt controller 6.

The interrupt controller 6 issues an interrupt to the CPU 1 when receiving an interrupt request from the external I / F 5.

Next, the operation of the arithmetic processing unit shown in FIG. 1 will be described. In the program of this arithmetic processing unit, a normal processing routine, an interrupt processing routine, an interrupt vector, etc. are placed from address 0 to address 6FFF, and addresses 7000 to 7F.
By the address FF, a routine (repeated instruction) that is executed when the instruction execution amount per unit time may be small, such as a standby routine, is placed.

During normal processing, the CPU
Since No. 1 operates with no wait, high speed operation is possible. When entering the standby routine, 16 waits are inserted for one fetch cycle, so the execution speed is reduced and the number of memory accesses per unit time is reduced, so that power consumption is reduced. When an external interrupt occurs, the interrupt processing routine is executed as it is by reading the no-wait interrupt vector, so that interrupt processing can be performed at high speed.

As described above, according to the arithmetic processing unit of this embodiment, it is possible to reduce the power consumption of the storage element without changing the system clock. Therefore, it is possible to effectively reduce the power consumption when high-speed processing is not required, without affecting the timer circuit and the like.

Next, a printer device will be described as an example of an optimum device for using the above-described arithmetic processing device. The printer device is a device that is not used even when the power is turned on and has a long standby time. When printing out the print data received from the host device, high-speed processing is required. When waiting, high speed is often not required.

Therefore, the printer apparatus according to the present embodiment is a RAM used in the central processing unit 1 via the above-described processing unit and the data storage area 3b of the storage unit 3.
And a printing unit that prints out on a recording medium, and a paper feeding unit that conveys recording paper to the printing unit.

Moreover, the first area of the instruction storage area 3a is
An instruction for allocating a part of the RAM as a reception buffer for temporarily storing the received print data and an instruction for allocating a part of the RAM as a drawing memory for temporarily storing the dot data obtained by expanding the print data are provided. . Further, the second area of the command storage area is a drive command for reception for receiving print data from the host device and temporarily holding it, and a drive command for expansion for expanding the print data into dot data and drawing it in the image memory. And a printing drive command for controlling the drive of the printing unit to print out the dot data accumulated in the image memory. Moreover, the third area of the command storage area is provided with a standby drive command that waits for reception of print data from the host device.

The wait controller 4B has a standby low power consumption function for outputting a read wait signal when the address output from the decoder 4A is the third area of the instruction storage area 3a.

The operation of this printer device will be described. When the printer is powered on, the central processing unit 1
First reads the first area of the instruction storage area 3a and reads R
Allocate part of AM to the receive buffer and drawing memory. When the print data is received from the higher-level device, the arithmetic processing unit reads the second area of the command storage area 3a and operates as a receiving unit and a developing unit, controls the driving of the printing unit, and prints the received print data on a recording sheet. To print out.

When the print data is not received from the host device after the power is turned on, the third area of the command storage area 3a is read as a standby time to wait for the print data. At this time, the weight control unit 4B has the decoding unit 4A.
Since the address output from is within the third area, a read wait signal is output. In response to this, the access control unit 2 delays the generation of the reading control signal to be output to the storage unit 3 when the reading weight signal is received. On the other hand, when receiving the read weight signal, the central processing unit 1 delays the read operation by the time (clock number) based on the read weight signal. Therefore, the storage unit 3 outputs the instruction stored in the address at the delayed timing to the data bus, and the central processing unit 1 reads the instruction at the delayed timing. Therefore, the power consumption of the storage unit 3 can be reduced without changing the system clock speed.

As described above, the printer according to the present embodiment operates the arithmetic processing unit at high speed during normal operation, and operates at low speed by reducing the number of memory accesses while waiting for print data. Therefore, not only the power consumption due to the memory access but also various power consumption can be reduced due to the slower calculation. Moreover, such a reduction in speed can be implemented without modifying the timer circuit or the like, only by changing the arithmetic processing unit and changing the address on the ROM of the standby routine.

[0043]

Since the present invention is constructed and functions as described above, according to the present invention, the delay circuit first obtains the address output by the central processing unit, and then the address only outputs a specific instruction. In order to determine whether or not it is included in the stored address range, the instructions stored in the storage unit can be controlled separately by the stored address. Further, when the address is within the specific address range, the delay circuit outputs the read start timing signal to delay the read operation of the specific instruction by the central processing unit for a predetermined time. Therefore, the read execution speed of the instruction stored in the specific address range is reduced, and the number of memory accesses per unit time can be reduced. Therefore, the power consumption in the storage unit can be reduced without changing the system clock speed. As described above, it is possible to provide an unprecedented excellent arithmetic processing device that can effectively reduce only the power consumption of the arithmetic processing device when a specific instruction is executed without changing the timer circuit or the like. .

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart of the arithmetic processing device shown in FIG.

FIG. 3 is a block diagram of a conventional arithmetic processing unit.

[Explanation of symbols]

 1 central processing unit (CPU) 2 access control unit 3 storage unit 3a instruction storage area 3b data storage area 4 delay circuit 4A decoding unit 4B wait control unit 5 external I / F 6 interrupt control unit

Claims (3)

[Claims] 1. A storage unit having a command storage region for storing a command and a data storage region for storing data, and the address is output to the storage unit to read the command, and the data is stored based on the command. An arithmetic processing device comprising: a central arithmetic processing unit that performs arithmetic processing; and an access control unit that controls timing of data transfer from the storage unit to the central arithmetic processing unit. A delay circuit that delays a read operation of the specific instruction of the central processing unit and an output operation of the specific instruction of the storage unit for a predetermined time when the address is an address within a range in which only the specific instruction is recorded. An arithmetic processing device comprising: 2. The decoding circuit, wherein the delay circuit decodes an address output from the central processing unit to a storage unit, and an address output by the decoding unit is an address in a range in which a specific instruction is recorded. A read control signal generation delay that delays the generation of the read control signal to the storage unit when the access control unit receives the read weight signal. 2. The arithmetic processing unit according to claim 1, further comprising a function, wherein the central processing unit has a reading delay function of delaying a reading operation based on the reading weight signal when the central processing unit receives the reading weight signal. . 3. The arithmetic processing device according to claim 1, wherein the specific instruction is a standby routine instruction that waits for an instruction from the outside.