JPH0991193A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimally perform the memory control without depending on the operating speed of a CPU and to bring out maximum memory performance by using clocks dedicated to memory control whose cycle is different from the clocks for CPU control. SOLUTION: While the CPU 1 is operated based on CPU clocks 7, a memory control circuit 3 controls memory control signals 13, memory address signals 15 and data buffer control signals 14 based on MEM clocks 6. Further, by tentatively holding memory read data in a data butter 5, the memory control circuit 3 can start next memory read control without waiting for the operation end of the CPU 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device in an arithmetic processing device including a CPU and a memory.

[0002]

2. Description of the Related Art In a conventional processor including a CPU and a memory, the same clock is supplied to the CPU and the memory controller. The clock is generally a clock optimized for the CPU, and the memory control signal is generated based on the clock. Therefore, an increased wait (wait time) is inserted in the memory.

FIG. 3 is a block diagram showing an example of a conventional arithmetic processing device of this type. CPU1 is status signal 1
1 starts the external cycle. The memory control circuit
When the memory read / write cycle is determined by the status signal 11, the memory address signal 15 is generated from the address signal 8 and output to the memory 4 together with the memory control signal 13 to control the read / write.
Data is transferred via the data bus 9. The end of the cycle is transmitted from the memory control circuit 3 or the CPU control circuit 2 to the CPU 1 by the RDY signal 12.

FIG. 4 is a timing chart showing memory reading in the conventional example shown in FIG. 16 in the figure
The external cycle is started at the rising edge of the CPU clock 7 indicated by. Then, when the memory control signal 13 becomes active (18 in the figure) in response to the rising of the CPU clock 7 shown in 17 in the figure, memory data is output after a predetermined time from that (19 in the figure). Therefore, the memory control circuit 3 activates the RDY signal 12 (20 in the figure).
Then, the CPU 1 samples the data on the data bus 9 (21 in the figure).

Further, the memory control circuit 3 deactivates the memory control signal 13 (22 in the figure) and, at the same time, switches the memory address 15 to the next address (23 in the figure).
The memory control signal 13 is activated (24 in the figure) to start the next reading. The next data is C shown by 25 in the figure.
Sampled by the CPU 1 at the rising edge of the PU clock 7.

[0006]

As described above, in the conventional memory control device, since the CPU and the memory are controlled by one clock, the period from when the memory control signal 13 becomes active to the next becomes active. Since (between 18 and 24 in FIG. 4) is restricted by the CPU clock 7, it is impossible to finely set the timing of the memory control signal 13, so that an additional wait cycle must be inserted. Therefore, there is a problem that it is a cause of hindering the improvement of the memory performance.

[0007]

The device of the present invention comprises a CPU
In a memory control device in an arithmetic processing device comprising a memory for storing the contents of arithmetic processing performed by the CPU and an arithmetic result, and a memory control circuit for controlling the memory, a cycle different from the CPU clock supplied to the CPU Supplying a MEM clock optimized for the operating speed of the memory, and the CPU clock and MEM
Since the clock cycle is different, the CPU is provided with a data buffer that holds the output data from the memory until the CPU reads it.

[0008]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the arithmetic processing unit of FIG. 1, the CPU 1 is C
The arithmetic processing and access to the memory 4 are performed based on the PU clock 7. The data bus 10 of the memory 4 is connected to the CPU 1 via a data buffer 5 that temporarily holds data.
Is connected to the data bus 9.

The memory controller 3 is supplied with a memory clock (MEM6) that is faster than the CPU clock and optimized for the memory 4. Optimization here means
One of the standards of the memory 4 is the minimum cycle time (tc) indicating the operation speed of the memory 4, and the standard for the CAS signal, that is, the minimum CAS width (tw) and the minimum CAS precharge width (tp). It means that T that satisfies the condition of is the cycle of the memory clock. In the formula below, x and y are integer values, and xT is the CAS width,
yT represents the CAS precharge width. Satisfying such a condition means that the cycle of the MEM clock 6 is determined so that an integral multiple of the cycle of the MEM clock 6 becomes the minimum cycle time of the memory 4 while satisfying the CAS standard.

XT + yT = tc (condition 1) xT ≧ tw (condition 2) yT ≧ tp (condition 3) As an example, tc = 50 ns, tw = 20 ns, tp =
In the case of 10 ns, T = 25 ns and 16.7 ns are realistic places.

The memory control circuit 3 generates a memory control signal 13 (CAS, etc.) and a data buffer control signal 14 from the address signal 8 and the status signal 11 of the CPU 1 based on the MEM clock 6.

First, the CPU 1 activates the external cycle by the status signal 11. When the memory control circuit 3 detects the memory read / write cycle by the status signal 11, it generates the memory address signal 15 from the address signal 8 and outputs it to the memory 4 together with the memory control signal 13 (CAS, etc.) for read / write. Take control. The read data from the memory 4 passes through the memory data bus 10 and is held in the data buffer 5. The memory control circuit 3 controls the data buffer 5 at this time by the data buffer control signal 14. The data held in the data buffer 5 is transferred to the CPU 1 via the data bus 9. The end of the cycle is transmitted from the memory control circuit 3 or the CPU control circuit 2 to the CPU 1 by the RDY signal 12.

In FIG. 2, the memory 4 has a first page DRA.
9 is a timing chart showing a memory read cycle in the case of M; The CPU 1 activates the address signal 8 to start the external cycle in response to the rising edge of the CPU clock 7 shown by 26 in the figure (27 in the figure). On the other hand, the memory control circuit 3 samples the status signal 11 and the address signal 8 in response to the rising edge of the MEM clock 6 shown by 28 in the figure, and starts the memory cycle.

First, the memory control circuit 3 uses the address signal 8
Generates and outputs a memory address signal 15 (2 in the figure)
9). Next, the memory control signal 13 is activated in response to the rising edge of the MEM clock 6 shown by 30 in the drawing (31 in the drawing). After a certain time from that point, the read data is output to the data bus 10 of the memory 4 (3 in the figure).
2). The memory control circuit 3 deactivates the memory control signal 13 (34 in the figure) at the rising edge of the MEM clock 6 shown by 33 in the figure, and at the same time, the memory address signal 1
5 is switched to the next address (A2) (35 in the figure).
Further, the read data from the memory 4 is transferred to the data buffer 5
(36 in the figure) and at the same time, the read data is output to the data bus 9.

The memory control circuit 3 has the first falling edge 4 of the CPU clock 7 after the first data holding (36 in the figure).
When the RDY signal 12 is activated in response to 7 (38 in the figure), the CPU 1 samples data in response to the CPU clock rising edge 39. It should be noted that, earlier than this data sample 39 by the CPU 1,
The memory control circuit 3 activates the memory control signal 13 for the next read by the MEM clock rising 37 (40 in the figure). That is, by temporarily holding the read data in the data buffer 5, the CPU 1 at the rising edge 39 of the CPU clock 7
Memory control can be performed without waiting for the operation of.

The memory control circuit 3 re-holds the read data from the memory 4 in the data buffer 5 at the rising edge 41 of the MEM clock 6 (42 in the figure). The data held at this time is the second read data (D2), and CP
Sampled by the CPU 1 at the U clock rising edge 43.
During this time, the RDY signal 12 remains active. 3
The next read data is the next CPU clock rising 4
Since it is not in time for 4, memory control circuit 3 once
The signal 12 is made inactive at the CPU clock falling edge 45 (46 in the figure) so that data is not sampled at the CPU clock rising edge 44. Reactivate at the next falling edge 48 of the CPU clock 7 (49 in the figure)
As a result, the third and fourth data are sampled by the CPU 1 at the rising edges 50 and 51 of the CPU clock.

[0018]

As described above, the memory control device according to the present invention uses the clock (C
A clock (MEM clock 6) having a different cycle from the PU clock 7) is used exclusively for memory control, and the memory control signal 1
The timing 3 can be set finely, the memory can be operated at the optimum timing, and the memory performance in the arithmetic processing device can be improved.

Further, by temporarily holding the read data, the waiting time due to the operation of the CPU can be eliminated and the memory timing can be optimized more effectively.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is an example of a timing chart of memory reading in the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional example.

FIG. 4 is an example of a timing chart of memory reading in the conventional example shown in FIG.

[Explanation of symbols]

 1 CPU 2 CPU control circuit 3 Memory control circuit 4 Memory 5 Data buffer 6 MEM clock 7 CPU clock 8 Address signal 9 Data bus 10 Memory data bus 11 Status signal 12 RDY signal 13 Memory control signal 14 Data buffer control signal 15 Memory address signal

Claims (2)

[Claims] 1. A memory control device in an arithmetic processing device, comprising: a CPU; a memory for storing the contents of arithmetic processing performed by the CPU and an arithmetic result; and a memory control circuit for controlling the memory, which is supplied to the CPU. Since the MEM clock optimized for the operation speed of the memory and having a different cycle from the CPU clock is supplied and the cycles of the CPU clock and the MEM clock are different, the output data from the memory is read until the CPU reads the data. A memory control device comprising a data buffer for holding. 2. The optimization is performed by determining the cycle of the MEM clock so that an integer multiple of the cycle of the MEM clock is the minimum cycle time of the memory while satisfying the CAS standard of the memory. The memory control device according to claim 1, wherein: