KR20000002638A - Semiconductor integrated circuit with processor embedded - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit is provided to save the electric current consumption by converting the sub-routine which is frequently used in the software of a processor into a hard ware. CONSTITUTION: The semiconductor direct circuit comprises; a central processing device(100) connected to the 1st data bus and generates a slim start signal and becomes a slim mode; a logic device, connected to the 3rd data bus, performing the work in response to the start up signal and generating a work finished signal when the work is completed; a data storage device to save a data.

Description

Semiconductor Integrated Circuits with Processor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a semiconductor integrated circuit including a processor.

Recently, semiconductor chips continue to add new and diverse functions to increase product competitiveness, and also use high-density Application Specific Integrated Circuits (ASICs) to increase product price competitiveness. On the other hand, it is difficult to add new functions because it requires a lot of time and effort to design new functions with hardware every time new functions are added. To address these challenges, many ASICs currently in production tend to incorporate processors such as Digital Signal Processing (DSP) processors or Reduced Instruction Set Computers (RISCs). In other words, most functions are handled in software, and new functions can be added easily by adding programs. However, in general, when performing any task in software through the processor, it consumes more current than when performing the same task in a logic circuit implemented in hardware. This is because there are many blocks connected to the inside and outside of the processor by the data bus. In other words, when the processor is operating, the blocks connected to the processor and the data bus are also in an operating state, thereby increasing current consumption.

As a result, when the processor is embedded and processed in software, the current consumption increases. In particular, in the case of a semiconductor chip for a portable product considering mobility, when the processor is embedded, the current consumption is large and the time for continuous use is shortened. There is a problem of losing competitiveness.

An object of the present invention is to provide a semiconductor integrated circuit incorporating a processor capable of reducing current consumption by hardwareizing a subroutine frequently used in the software of the processor.

1 is a block diagram illustrating a semiconductor integrated circuit incorporating a processor according to the present invention.

In order to achieve the above object, a semiconductor integrated circuit including a processor according to the present invention is connected to a first data bus, generates a sleep start signal, and then enters a sleep mode, and performs central processing to exit the sleep mode in response to the wakeup signal. Means, logic means connected with a third data bus, operating in response to a task start signal to perform a task, and generating a task completion signal when the task is completed, coupled with a second data bus, to perform the task Data storage means for storing necessary data and storing data generated as a result of performing the operation, first switching means for switching the first data bus and the second data bus in response to the bus control signal, responsive to the inverted bus control signal Second switching means for switching the second data bus and the third data bus by means of a central processing means And a mode control means for generating a bus control signal and the work start signal in response to a sleep start signal and for generating the wakeup signal in response to a work completion signal generated from logic means.

Hereinafter, a semiconductor integrated circuit incorporating a processor according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor integrated circuit incorporating a processor according to an exemplary embodiment of the present invention, which includes a central processing unit 100, a first resource unit 110, a mode control unit 140, and a first switching unit ( 180, the processor 130 includes a second switching unit 190 and a second resource unit 120, a data storage unit 150, and a logic unit 160.

Unlike the conventional processor, the processor 130 illustrated in FIG. 1 divides and controls resources into two types of first and second resource units 110 and 120. In this case, the first resource unit 110 is a resource having functional blocks in which the function is always performed by the central processing unit 100, and the second resource unit 120 functions by the central processing unit 100 or the logic unit 160. These are resources with functional blocks that can be performed. In addition, the data bus for transmitting and receiving data between the respective units is divided into first, second and third data buses 105, 115, and 125 by the first and second switching units 180 and 190. In this case, the first switching unit 180 switches between the first data bus 105 and the second data bus 115 in response to the bus control signal Sb, and the second switching unit 115 switches the bus control signal. Switching between the second data bus 115 and the third data bus 125 in response to (Sb), the first switching unit 180 and the second switching unit 190 in response to the bus control signal (Sb) Complementary to each other.

Meanwhile, the central processing unit 100 generates a sleep start signal Ss corresponding to the function to be performed currently. That is, if a function to be performed currently is a function performed by the first resource unit 110, the central processing unit 100 generates a sleep start signal Ss having a "low" logic level. In addition, if a function to be performed currently is a function performed by the second resource unit 120, the central processing unit 100 generates a sleep start signal Ss having a "high" logic level, and then enters a sleep mode. The sleep control unit 140 corresponds to a sleep start signal Ss generated by the central processing unit 100, and includes a bus control signal Sb and a logic unit for switching the first and second switching units 180 and 190. Each of the job start signals Sjs for controlling 160 is generated. When the central processing unit 100 generates a sleep start signal Ss having a "low" logic level, the mode control unit 140 generates a bus control signal Sb and a job start signal Sjs having a "low" logic level. To generate the device shown in FIG. 1 in software mode. That is, the first switching unit 180 is "on" and the second switching unit 190 is "off" by the bus control signal Sb having the "low" logic level, so that the logic The third data bus 125 connected to the unit 160 is separated from the data bus. In addition, since the job start signal Sjs having the "low" logic level causes the logic unit 160 to be in an inactive state, the apparatus illustrated in FIG. 1 may be configured to include the central processing unit 100, the first and second resource units ( 110 and 120 and the data storage unit 150 to perform a function in software. At this time, the data storage unit 150 stores data necessary for performing the function, and stores new data generated as a result of the function execution.

On the other hand, when the central processing unit 100 generates the sleep start signal Ss having the "high" logic level and enters the sleep mode, the mode control unit 140 operates with the bus control signal Sb having the "high" logic level. The start signal Sjs is generated to put the device shown in FIG. 1 into the hardware mode. That is, the bus control signal Sb having the "high" logic level "turns off" the first switching unit 180 and "turns on" the second switching unit 190, and thus the central processing unit 100 and the first processing unit. The first data bus 105 connected to the resource unit 110 is separated from the data bus. In addition, since the job start signal Sjs having the "high" logic level puts the logic unit 160 into an operating state, the device shown in FIG. 1 eventually provides the logic unit 160, the second resource unit 120, and the data. The storage unit 150 processes the function in hardware. When the hardware function is performed by the logic unit 160, the logic unit 160 generates a task completion signal Sjd to the mode controller 140. When the logic unit 160 generates a job completion signal Sjd, the mode controller 140 generates a wakeup signal Sw to the central processing unit 100. The CPU 100 exits the sleep mode by the wake-up signal Sw generated by the mode controller 140 and replaces the sleep start signal Ss, which was at the "high" logic level, with the sleep start signal (the "low" logic level). Ss). By the sleep start signal Ss converted to the "low" logic level, the logic unit 100 is inactivated again, the first switching unit 110 is "on" and the second switching unit 190 is " Off ". The central processing unit 100 out of the sleep mode continues to perform the next function by the above-described operation. That is, it is determined whether to perform the next function to be performed in the software mode by the central processing unit 100 or the hardware mode by the logic unit 160, and the function is determined by the mode corresponding to the determination result. Will be performed.

Meanwhile, when designing a semiconductor integrated circuit incorporating a processor as described above, infrequently used resources may be separated into the first resource unit 110 and infrequently used resources into a second resource. That is, functions performed by infrequently used resources can be quickly implemented using the central processing unit 100, and are performed by frequently used resources (including arithmetic logic devices and multipliers). The function is to implement the function in hardware through the logic unit 160. As a result, since the functions performed by the frequently used second resource unit 120 are processed in hardware, the current consumption by the central processing unit 100 may be reduced. As mentioned in the prior art, many blocks are connected to a conventional processor. Thus, when a function is implemented by a processor, a large amount of current is consumed by many blocks connected to the processor's data bus. However, if the function is implemented by the hardware, the first resource unit 110 and the other blocks (not shown) connected to the central processing unit 100 do not operate, thereby reducing current consumption.

As described above, a function that is not frequently used in a semiconductor integrated circuit incorporating a processor according to the present invention can be quickly processed in software by the central processing unit by putting the semiconductor integrated circuit in software mode, and is often used. Since the central processing unit is in the sleep mode and the semiconductor integrated circuit is in the hardware mode, the logic is processed by the hardware to reduce the current consumed in the central processing unit and the blocks connected to the central processing unit.

Claims (3)

A central processing means connected to a first data bus, generating a sleep start signal, entering a sleep mode, and exiting the sleep mode in response to a wake up signal; Logic means connected to the third data bus, in a state of operation in response to a task start signal to perform a task, and generating a task completion signal when the task is completed; Data storage means connected to the second data bus, storing data necessary for performing a task, and storing data generated as a result of the task execution; First switching means for switching the first data bus and the second data bus in response to a bus control signal; Second switching means for switching a second data bus and the third data bus in response to the inverted bus control signal; And A mode control means for generating the bus control signal and the operation start signal in response to a sleep start signal generated from the central processing means, and generating the wakeup signal in response to the operation completion signal generated from the logic means; A semiconductor integrated circuit incorporating a processor, comprising: a processor. 2. The semiconductor integrated circuit according to claim 1, further comprising first functional blocks connected to the first data bus and having a function of performing a function by the central processing means. 2. The semiconductor integrated circuit of claim 1, further comprising second functional blocks connected to the second data bus and having a function performed by the central processing means or the logic means;