JPS60148128A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPS60148128A JPS60148128A JP432984A JP432984A JPS60148128A JP S60148128 A JPS60148128 A JP S60148128A JP 432984 A JP432984 A JP 432984A JP 432984 A JP432984 A JP 432984A JP S60148128 A JPS60148128 A JP S60148128A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- single crystal
- semiconductor
- semiconductor substrate
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000013078 crystal Substances 0.000 claims abstract description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 229910021426 porous silicon Inorganic materials 0.000 abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- 229910052760 oxygen Inorganic materials 0.000 abstract description 7
- 239000001301 oxygen Substances 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract 2
- 239000002699 waste material Substances 0.000 abstract 2
- 230000002349 favourable effect Effects 0.000 abstract 1
- 230000007547 defect Effects 0.000 description 13
- 238000011109 contamination Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 229910001385 heavy metal Inorganic materials 0.000 description 4
- 238000001556 precipitation Methods 0.000 description 3
- 239000000428 dust Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 不発明は半導体基板に関するものである。[Detailed description of the invention] The invention relates to semiconductor substrates.
不発明の目的とするところは、半導体装置の製造プロセ
ス中での重金属などによる汚染及びそれに伴って発生す
る微小欠陥の核をゲッターする能力をもつ半導体基板を
提供することにある。An object of the present invention is to provide a semiconductor substrate that has the ability to getter the nuclei of minute defects that are contaminated by heavy metals and the like during the manufacturing process of semiconductor devices and that occur as a result of the contamination.
従来のゲッター能力をもつ半導体基板は長面に機械的損
傷を与えたもので該損傷部に埋込まれたシリコン屑が飛
散し牛導体装置芙造の大赦である塵の原因となる問題が
あった。また、ゲッター能力をもつ他の半導体基板とし
て、半導体基板の裏面が多結晶半導体からなるものが知
られている・これは、半導体裏面に多結晶半導体を形成
する際６００℃前後の温夏で数時間の熱処理を委する為
。Conventional semiconductor substrates with getter capabilities have been mechanically damaged on their long sides, and there is a problem in that silicon debris embedded in the damaged areas can fly off and cause dust, which is a major problem in the manufacture of conductor devices. Ta. In addition, as another semiconductor substrate with getter ability, one in which the back side of the semiconductor substrate is made of polycrystalline semiconductor is known. To entrust time heat treatment.
単結晶半導体中の酸素が析出しテバイスプロセスを経る
と単結晶半導体基板中に高密度の内部欠陥が発生しその
欠陥が基板表面にまで達してしまう。When oxygen in a single crystal semiconductor is precipitated and subjected to a device process, a high density of internal defects is generated in the single crystal semiconductor substrate, and these defects reach the surface of the substrate.
従って、この様な基板表面に形成された半導体装置は電
気的特性が劣化し１歩ｗシの低下さらには信頼性の低下
をも招く問題があった。Therefore, a semiconductor device formed on the surface of such a substrate has a problem in that its electrical characteristics deteriorate, leading to a decrease in performance and even a decrease in reliability.
第１図は従来のＣＺ法で育成された単結晶シリコン基板
の例である。単結晶シリコン基板１の裏面には８ｉ０ｚ
粉等で形成された機械的損傷部２がある（第１図（ａｌ
）、時間を経るに従って機械的損傷部２より７リコン
屑が飛散する。このシリコン屑は塵の原因となシ、半導
体装置の歩留シ低下をもたらす一因となる。又この方法
はプロセスの熱処理を経るにつれ歪場がアニールされ効
果が持続しない。また、他の従来の方法は前述したよう
に単結晶シリコン基板３の裏面が多結晶シリコン４から
なっている（第２図（Ｎ）、これは単結晶シリコン基板
３に多結晶シリコン４を形成すると単結晶シリコン基板
３に内在する酸素が析出し微小欠陥５となる（第２図（
Ｂ））。その後のデバイスプロセス（主に熱処理）で微
小欠陥５は内部欠陥として大きく成長し表面にまで到達
する。その結果半導体装置の電気的特性が劣化し、歩留
り、信頼性の低下を招く問題があった。FIG. 1 is an example of a single crystal silicon substrate grown by the conventional CZ method. 8i0z on the back side of the single crystal silicon substrate 1
There is a mechanically damaged part 2 formed by powder etc. (see Fig. 1 (al.
), 7 Recon debris scatters from the mechanically damaged portion 2 over time. This silicon dust does not cause dust, but also contributes to a decrease in the yield of semiconductor devices. Further, in this method, the strain field is annealed as the process heats, and the effect does not last. In addition, in another conventional method, as described above, the back surface of the single crystal silicon substrate 3 is made of polycrystalline silicon 4 (FIG. 2 (N)). Then, the oxygen inherent in the single crystal silicon substrate 3 precipitates and becomes micro defects 5 (see Fig. 2).
B)). In the subsequent device process (mainly heat treatment), the micro defects 5 grow as internal defects and reach the surface. As a result, the electrical characteristics of the semiconductor device deteriorate, resulting in a problem of lower yield and reliability.
不発明は上記欠点を除いた半導体基板を提供することを
とし、単結晶半導体基板の裏面を多孔質半導体とする
ことを特徴としている。かかる不発明によればシリコン
屑の発生がなく、酸素の析出が少なく、重金属などの汚
染及び微小欠陥の核をゲッターする能力をもち、該単結
晶半導体基板上に設けられた半導体装置の特性の劣化を
防ぎ歩留シ、信頼性を同上させることができる。The present invention aims to provide a semiconductor substrate that eliminates the above-mentioned drawbacks, and is characterized in that the back surface of the single crystal semiconductor substrate is made of a porous semiconductor. According to this invention, there is no generation of silicon debris, less precipitation of oxygen, the ability to getter the nuclei of contamination such as heavy metals and micro defects, and the characteristics of the semiconductor device provided on the single crystal semiconductor substrate are improved. It is possible to prevent deterioration and improve yield and reliability.
以下、実施例に基づき不発明の詳細な説明する。Hereinafter, the invention will be described in detail based on examples.
第３図は、不発明を単結晶シリコン基板に適用した場合
の断面図である。即ち、単結晶シリコン基板６の裏面が
多孔質シリコン７からなるシリコン茶飯である（第３図
）。不発明の基板は長面が多孔質シリコンで返る為シリ
コン屑は飛散しない。FIG. 3 is a cross-sectional view when the invention is applied to a single crystal silicon substrate. That is, the back surface of the single-crystal silicon substrate 6 is made of porous silicon 7 (FIG. 3). Since the long side of the non-inventive substrate is made of porous silicon, silicon debris does not scatter.
また、多孔質シリコン形成には熱処理全必要としない為
単結晶シリコン基板中の酸素の析出も少ない。さらに、
多孔質シリコンの孔径が極めて小さい為、デバイスプロ
セス（主に酸化熱処理）によシ単結晶シリコン基板に応
力を与えることができる。その結果、多孔質シリコンに
接する単結晶シリコンに結晶欠陥が誘起され、該結晶欠
陥がゲッターシンクとして働き重金属などの汚染及び表
面微小欠陥の核等をゲッターする。従って、本発明のシ
リコン基板上に設けられた半導体装置の特性は劣化せず
歩留シ、信頼性も同上する。尚、単結晶シリコン基板の
裏の多孔質シリコン厚さは幾らでもかまわないが、１〜
１０μｍ程度にするのが良い、このような半導体基板は
例えは単結晶半導体基板’ｉ７ツ酸溶液での陽極化成等
により多孔質半導体を形成する方法等がある。Furthermore, since no heat treatment is required to form porous silicon, there is little oxygen precipitation in the single crystal silicon substrate. moreover,
Since the pore diameter of porous silicon is extremely small, stress can be applied to the single crystal silicon substrate during device processes (mainly oxidation heat treatment). As a result, crystal defects are induced in the single crystal silicon in contact with the porous silicon, and the crystal defects act as getter sinks to getter contamination such as heavy metals and nuclei of surface micro defects. Therefore, the characteristics of the semiconductor device provided on the silicon substrate of the present invention do not deteriorate, and the yield and reliability also remain the same. Note that the thickness of the porous silicon on the back side of the single crystal silicon substrate may be any number,
The thickness of such a semiconductor substrate, which is preferably about 10 .mu.m, can be obtained by forming a porous semiconductor by, for example, anodizing a single crystal semiconductor substrate with an acid solution.
以上詳細に説明したように不発明の半導体基板はシリコ
ン屑の発生がなり、酸素の析出が少なく、重金属などの
汚染及び微小欠陥の核をゲッターする能力全もち、該半
導体基板上に設けられた半導体装置の電気的特性が同上
し、夛留り同上に寄与することができる。As explained in detail above, the uninvented semiconductor substrate generates less silicon debris, has less oxygen precipitation, has the ability to getter contamination such as heavy metals, and the nuclei of micro defects, and has the ability to getter the nuclei of micro defects and the formation of silicon chips. The electrical characteristics of the semiconductor device are the same as above, and can contribute to the same as above.
第１図および第２図はそれぞれ従来の単結晶シリコン基
板を示す断面図、第３図は不兄明全シリコン基板に適用
した実施例の断面図である。
尚、図において。
１、ｊ、６・・・単結晶シリコン、２ ・・機械的損傷
部、４・・ 多結晶シリコン、５・・・・・微小欠陥。
７ ・・多孔質シリコン。
乃１（２）
損２閉 （Ａ）FIGS. 1 and 2 are cross-sectional views showing conventional single crystal silicon substrates, respectively, and FIG. 3 is a cross-sectional view of an embodiment applied to an unconventional all-silicon substrate. In addition, in the figure. 1, j, 6... Single crystal silicon, 2... Mechanically damaged part, 4... Polycrystalline silicon, 5... Micro defect. 7...Porous silicon. No1 (2) Loss 2 closing (A)
Claims (1)
特徴とする半導体基板。A semiconductor substrate characterized in that a long surface of the single crystal semiconductor substrate is made of a porous semiconductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP432984A JPS60148128A (en) | 1984-01-13 | 1984-01-13 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP432984A JPS60148128A (en) | 1984-01-13 | 1984-01-13 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60148128A true JPS60148128A (en) | 1985-08-05 |
Family
ID=11581403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP432984A Pending JPS60148128A (en) | 1984-01-13 | 1984-01-13 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60148128A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2794897A1 (en) * | 1999-06-11 | 2000-12-15 | Mitsubishi Electric Corp | Semiconductor chip comprises silicon layer, oxide film and gas-retaining porous silicon layer in sequence |
| JP2006287186A (en) * | 2005-03-11 | 2006-10-19 | Elpida Memory Inc | Semiconductor chip comprising porous single crystal layer and its manufacturing method |
| JP2007150129A (en) * | 2005-11-30 | 2007-06-14 | Elpida Memory Inc | Semiconductor chip having island-shaped scattering structure and manufacturing method therefor |
-
1984
- 1984-01-13 JP JP432984A patent/JPS60148128A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2794897A1 (en) * | 1999-06-11 | 2000-12-15 | Mitsubishi Electric Corp | Semiconductor chip comprises silicon layer, oxide film and gas-retaining porous silicon layer in sequence |
| US6774435B1 (en) | 1999-06-11 | 2004-08-10 | Renesas Technology Corp. | Semiconductor wafer and semiconductor device comprising gettering layer |
| JP2006287186A (en) * | 2005-03-11 | 2006-10-19 | Elpida Memory Inc | Semiconductor chip comprising porous single crystal layer and its manufacturing method |
| US7632696B2 (en) | 2005-03-11 | 2009-12-15 | Elpida Memory, Inc. | Semiconductor chip with a porous single crystal layer and manufacturing method of the same |
| JP2007150129A (en) * | 2005-11-30 | 2007-06-14 | Elpida Memory Inc | Semiconductor chip having island-shaped scattering structure and manufacturing method therefor |
| US7911058B2 (en) | 2005-11-30 | 2011-03-22 | Elpida Memory Inc. | Semiconductor chip having island dispersion structure and method for manufacturing the same |
| JP4677331B2 (en) * | 2005-11-30 | 2011-04-27 | エルピーダメモリ株式会社 | Semiconductor chip having island-shaped dispersion structure and manufacturing method thereof |
| US8088673B2 (en) | 2005-11-30 | 2012-01-03 | Elpida Memory Inc. | Semiconductor chip having island dispersion structure and method for manufacturing the same |
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