JPS60145639A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60145639A
JPS60145639A JP222184A JP222184A JPS60145639A JP S60145639 A JPS60145639 A JP S60145639A JP 222184 A JP222184 A JP 222184A JP 222184 A JP222184 A JP 222184A JP S60145639 A JPS60145639 A JP S60145639A
Authority
JP
Japan
Prior art keywords
film
elements
substrate
forming
photoresist film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP222184A
Other languages
Japanese (ja)
Inventor
Kosaku Yamamoto
山本 功作
Yoshihiro Miyamoto
義博 宮本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP222184A priority Critical patent/JPS60145639A/en
Publication of JPS60145639A publication Critical patent/JPS60145639A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Abstract

PURPOSE:To form a separating part between elements having a flat surface by slightly shortly developing as compared with the usual developing time, etching it, then again developing to remove the resist film of underetched part, burying with insulator by a lift-off method, and forming a burying groove. CONSTITUTION:When a photoresist film 5 is developed on a substrate 2 to open, it is developed slightly shorter than the optimum developing time to open the pattern 6 of the separating part between elements, the width is narrowed from the designed value. When chemical etching is perfored to etch the substrate 2, overhangs 8 are formed at a photoresist film 5 by the formation of underetching part 7. Then, the photoresist film for forming the overhangs 8 is dissolved by the redevelopment. Then, an insulating layer 10 is formed on the film 5 by a lifting method in the same manner as the conventional one, the film 5 is removed with a solvent, thereby forming the layer 10 having no groove.

Description

【発明の詳細な説明】 (a)発明の技術分野 本発明は平担な表面をもつ半導体基板の素子間分離方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method for isolating elements of a semiconductor substrate having a flat surface.

(b) 技術の背景 ICやLSIによって代表される半導体装置は半導体チ
ップと言イっれる微少な面積をもつ半導体基板上にダイ
オードやトランジスタなどの能動素子を数多く形成し、
これを配線バター/により回路接続して高密度な電子回
路を形成したものであり、この場合各素子間の絶縁は、
pn接合によって生ずる種層を効果的に用いて行われて
いる。
(b) Technical Background Semiconductor devices, represented by ICs and LSIs, have many active elements such as diodes and transistors formed on a semiconductor substrate with a small area called a semiconductor chip.
A high-density electronic circuit is formed by connecting these circuits with wiring butter.In this case, the insulation between each element is
This is done effectively using a seed layer created by a pn junction.

一方二酸化硅素(Stop)や窒化硅素(SiiN4)
などの絶縁物を用いて素子間分陰を行うデバイスもある
On the other hand, silicon dioxide (Stop) and silicon nitride (SiiN4)
There are also devices that use insulators such as these to provide shielding between elements.

例えば電荷注入デバイスを用いる固体撮像素子はこれで
あって選択電極と5フシみ出し電極とは互1こ近接して
設けられて単位の画素を形成し′Cおり、か\る画素は
半導体基板の上にt3緑層を介して数多く形成されてい
る。第1図囚はか\る画素の配列を示す平面図また同図
(B)はx −x’ 線における断面図を示している。
For example, in a solid-state image sensor using a charge injection device, the selection electrode and the five-edge protruding electrode are provided close to each other to form a unit pixel, and the other pixel is located on the semiconductor substrate. A large number of t3 green layers are formed on top of the t3 green layer. FIG. 1 is a plan view showing the pixel arrangement, and FIG. 1B is a sectional view taken along the line x-x'.

すなわち選択i1t iと読み出し1d極とが隣接して
構成されている画素1は半導体基板2の上に設けられた
絶縁層3の上に形成されてMIS構造をなしており、各
画素1の素子間分離部4の上に設は弘 られ主体交互する配線を通じ各選択′1ニ極はシフトレ
ジスタにまた各読み出し電極は信号増幅回路へと配線さ
れている。こ\で素子間分離部4は半導体基板に写真蝕
刻技術(ホトリソグラフィ)を用いてエツチングし、こ
れに絶縁物を埋め込んで形成されている。
That is, the pixel 1 in which the selection i1t i and the readout 1d pole are configured adjacent to each other is formed on an insulating layer 3 provided on a semiconductor substrate 2 to form an MIS structure, and the elements of each pixel 1 Each selection '1 electrode is connected to a shift register, and each readout electrode is connected to a signal amplification circuit through wiring which is provided above the separation section 4 and alternates between main bodies. The element isolation section 4 is formed by etching a semiconductor substrate using photolithography and embedding an insulator therein.

本発明はこのような素子間分離の形成法に関するもので
ある。
The present invention relates to a method of forming such isolation between elements.

(e) 従来技術と問題点 半導体基板上への素子間分離部の形成はホトレジストを
被(転)後に紫外線の選択露光を行い被照射部が縮重合
して不溶性となる(ネガ型レジスト)か或は分解して現
像液に可溶となる(ポジ波レジスト)のを利用してレジ
スト膜に素子間分離部のパターンを窓開けしこれにエツ
チング処理を施すことにより形成されている。
(e) Conventional technology and problems To form an isolation part between elements on a semiconductor substrate, after applying (transferring) a photoresist, selective exposure to ultraviolet rays is performed so that the irradiated part undergoes condensation polymerization and becomes insoluble (negative resist). Alternatively, it is formed by using a resist film that decomposes and becomes soluble in a developer (positive wave resist) to open a pattern of an element separation part in a resist film and then etching it.

第2図は化学エツチング法を用いて素子間分離部を形成
する工程を示すもので、上記の写真蝕刻技術でホトレジ
スト膜5に素子間分離部のパターン6を窓開けした後(
同図A)半導体基板(以下略して基板)2を化学エツチ
ング液に浸漬して窓開は部を化学エツチングするがエツ
チング液の廻り込み現象のためホトレジスト膜5の開口
部の周辺に沿ってアンダーエツチング部7を生じそのた
めレジス)IMの庇8を生ずる(同図B)。
FIG. 2 shows the process of forming the element isolation part using the chemical etching method. After opening the pattern 6 of the element isolation part in the photoresist film 5 using the above photolithography technique,
Figure A) A semiconductor substrate (substrate hereinafter) 2 is immersed in a chemical etching solution to chemically etch the window opening. An etched portion 7 is formed, thereby forming an eave 8 of the resist IM (FIG. B).

次に絶縁物を高周波スパッタなどの方法でエツチングに
より形成されたlY+;9か埋められるまで析出させて
絶縁層10を形成するが、この場合アンダーエツチング
部7は庇8の影となって絶縁層10の形成は行われない
(同図C)。
Next, an insulating material is deposited using a method such as high-frequency sputtering until the lY+; 10 is not formed (C in the same figure).

そのためホトレジスト膜5を?11媒を用いて溶解除去
した後はアンダーエツチング部7が窪んだ素子間分離部
が生じる(同図1))。
Therefore, what about the photoresist film 5? After dissolving and removing using medium No. 11, an inter-element separation area in which the under-etched area 7 is depressed is generated (FIG. 1)).

そのために素子量分1r’i部をもつ基板2の上に絶縁
層3を形成し更に導電層11を形成したす;合に素子間
分離部のアンダーエツチング部7の上に溝12が生じて
しまう(同図E)。この溝12の存在はこの部分を通っ
てパターン形成されている配線パターンのt:d?線障
害の原因をrti成し、’Iff 軸性の面から問題で
あった。
For this purpose, an insulating layer 3 is formed on a substrate 2 having a 1r'i portion corresponding to the amount of elements, and a conductive layer 11 is further formed; in this case, a groove 12 is formed on the under-etched portion 7 of the element isolation portion. (E in the same figure). The presence of this groove 12 is due to the t:d? of the wiring pattern formed through this portion. The cause of the line disturbance was the rti, which was a problem from the viewpoint of the 'Iff axis.

(d) 発明の目的 本発明の目的は半導体基板の素子間分離部に生ずる溝を
無くして平坦な平面をもつ素子間分離部を形成する方法
を提供することを目的とする。
(d) Object of the Invention An object of the present invention is to provide a method for forming an element isolation part with a flat surface by eliminating grooves that occur in the element isolation part of a semiconductor substrate.

(e) 発明の構成 本発明の目的は半導体基板上に形成したレジスト膜に紫
外線を露光・現像して素子間分離パターンを窓開けする
際、標準とされる現像時間よりも少なめに現像して前記
基板をエツチングした後、再び現像処理を行ってアンダ
ーエツチング部上のレジスト膜を除き、リフトオフ法を
用いて絶縁物による穴埋めを行い埋め込み溝を形成する
半導体基板のg子間分離方法により達成することができ
る0 (f) 発明の実施例 本発明は基板を写真蝕刻技術を用いて化学エツチングす
る場合に生ずるホトレジスト膜5の庇8を無くすること
1こよって素子間分離部に沿って生ずる溝を熱くするも
のである。
(e) Structure of the Invention The object of the present invention is to develop a resist film formed on a semiconductor substrate by exposing it to ultraviolet rays and developing it to open a window for isolation patterns between elements, by developing the resist film in a shorter time than the standard development time. After etching the substrate, it is developed again to remove the resist film on the under-etched area, and a lift-off method is used to fill the hole with an insulator to form a buried trench. (f) Embodiments of the Invention The present invention is to eliminate the eaves 8 of the photoresist film 5 that occur when chemically etching a substrate using photolithographic technology. It is something that makes things hot.

第3図は本発明に係る工程図であって、基板2の上のホ
トレジスト膜5をホトエツチングして開口する際最適な
エツチング時間よりも少なめに現像して素子間分離部の
パターン6を開口する際その幅を設計値よりも狭く作る
FIG. 3 is a process diagram according to the present invention, in which the photoresist film 5 on the substrate 2 is opened by photoetching, and the pattern 6 of the isolation part between elements is opened by developing the film for a shorter time than the optimum etching time. In this case, make the width narrower than the design value.

例えばポジ型レジスト0FPR−800を用いる場合厚
さ1〔μm〕のレジストj撲を現像するには約30印ン
〕の浸漬が必要であるがこれを20〔秒〕に留めること
により開口部を段積1冶より狭めに作ることができる(
第3図A)。
For example, when using positive resist 0FPR-800, it takes approximately 30 seconds of immersion to develop a 1 μm thick resist, but by keeping this for 20 seconds, the openings can be closed. It can be made narrower than a single stage (
Figure 3A).

次に化学エツチング処理をi4してl+3iA”42の
エツチングを行うがこの際アンダーエツチング部7の形
l戊によりホトレジスト11g45にj圧8力i生ずる
(同図B)。
Next, a chemical etching process i4 is performed to etch l+3iA'' 42, and at this time, a pressure j8 force i is generated on the photoresist 11g45 due to the shape l of the underetched portion 7 (FIG. 3B).

次に本発明に係る再籾、像を行うことにより庇8を形成
しているホトレジスト膜を溶解させる。
Next, the photoresist film forming the eaves 8 is dissolved by re-hulling and imaging according to the present invention.

例えば0FPR−800を用いた;舗i1i I+ll
においては10〔秒〕間浸漬することにより除去するこ
とができる(同図C)。
For example, using 0FPR-800;
can be removed by dipping for 10 seconds (C in the same figure).

その理由は庇8の部分のホトレジストは部分的に感光し
た部分であってこれが短い現1)コ処理により溶は残っ
たものであることによる。次に従来と同様にリフトオフ
法によりポトレジス) rs<p 5の上に絶縁層10
を形成しく同図D)、次にホトレジスト膜5を溶剤を用
いて取り除くことにより溝のない絶縁層10が形成でき
(同図E)、そのためこの上に形成された絶縁層3と導
電層11は共に平坦である。
The reason for this is that the photoresist on the eaves 8 is a partially exposed portion, which is short and remains undissolved due to the 1) process. Next, as in the conventional method, an insulating layer 10 is formed on the potresist (rs<p) 5 using a lift-off method.
The insulating layer 10 without grooves can be formed by removing the photoresist film 5 using a solvent (see E in the same figure). are both flat.

(g) 発明の効果 本発明は従来の絶縁物を埋め込んだ素子間分離法におい
てはアンダーエッチ現象によってホトレジストに庇部を
生ずるため埋め込んだ絶縁層に沿って溝ができると言う
欠点があったがホトレジストの庇部を除去する本発明の
実施により平坦な表面をもつ素子間分離が可能となり、
これにより信頼度の向上が達成される。
(g) Effects of the Invention The present invention has the drawback that in the conventional device isolation method in which an insulating material is buried, a groove is formed along the buried insulating layer because an eaves are formed in the photoresist due to an under-etch phenomenon. By implementing the present invention, which removes the eaves of the photoresist, it is possible to separate elements with a flat surface.
This achieves improved reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

電1図は素子間分離の説明図で囚は平面図、a3)はX
 X’腺における断面図、第2図(4)〜(ト)は従来
性われていた素子間分離の工程の説明1凶、また第3図
(4)〜いは本発明に係る工程の説明図である。 図において、2は基板、3と10は絶縁層、4は素子間
分離部、5はホトレジスト膜、7はアンダーエツチング
部、8は庇、12は溝。 雫↓−一−−1
Figure 1 is an explanatory diagram of the separation between elements, the figure is a plan view, and a3) is an
A cross-sectional view of the X′ gland, and FIGS. 2(4) to (g) are explanations of the conventional process of separating elements, and FIGS. 3(4) to 3(g) are explanations of the steps according to the present invention. It is a diagram. In the figure, 2 is a substrate, 3 and 10 are insulating layers, 4 is an isolation portion, 5 is a photoresist film, 7 is an under-etched portion, 8 is an eaves, and 12 is a groove. Drop ↓-1-1

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に形成したレジスト膜に紫外線を露光・現
像して素子間分離パターンを窓開けする際、標準とされ
る現像時間よりも少なめに現像して前記基板をエツチン
グした後、再び現像処理を行ってアンダーエツチング部
上のレジスト膜を除き、リフトオフ法を用いて絶縁物に
よる穴埋めを行い埋め込み溝を形成することを!j+徴
とする半導体装置の製造方法。
When a resist film formed on a semiconductor substrate is exposed to ultraviolet rays and developed to open a window for isolation patterns between elements, the resist film is developed for a shorter time than the standard development time to etch the substrate, and then the development process is performed again. Then, remove the resist film on the under-etched area, fill the hole with an insulator using the lift-off method, and form a buried groove! A method for manufacturing a semiconductor device having a j+ characteristic.
JP222184A 1984-01-10 1984-01-10 Manufacture of semiconductor device Pending JPS60145639A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP222184A JPS60145639A (en) 1984-01-10 1984-01-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP222184A JPS60145639A (en) 1984-01-10 1984-01-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60145639A true JPS60145639A (en) 1985-08-01

Family

ID=11523297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP222184A Pending JPS60145639A (en) 1984-01-10 1984-01-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60145639A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9278603B2 (en) 2012-09-11 2016-03-08 Nhk Spring Co., Ltd. Semimanufactured product of movement regulation member, stabilizer bar having movement regulation member, and method for installing semimanufactured product of movement regulation member to a stabilizer bar

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9278603B2 (en) 2012-09-11 2016-03-08 Nhk Spring Co., Ltd. Semimanufactured product of movement regulation member, stabilizer bar having movement regulation member, and method for installing semimanufactured product of movement regulation member to a stabilizer bar

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