JPS6014559A - Psk demodulator - Google Patents

Abstract

PURPOSE:To eliminate various in conveniences caused by a delay line without no need for the synchronism by detecting digitally a signal so that ''0'' or ''1'' is outputted depending that the detected phase difference is 0 or 0+ or -180 deg.. CONSTITUTION:In the 2-phase phasl modulation, one phase difference is theta, then the other phase difference is theta+180 deg. (or theta-180 deg.). In the demodulation of the DPSK, when the phase difference before one symbol is theta and the phase difference after one symbol is theta, the demodulation is conducted such as the data is ''0'' and when the data is theta+180 deg. (or theta-180 deg.), then the data is ''1''. A longitudinal axis represents the direction of a vector representing the 2nd reference signal passing through a path 26. That is, the input signal is decomposed into directions of vectors 28, 29 representing two orthogonal reference signals and inputted to the digital system DPSK demodulator 24. The phase difference information decomposed into two and outputted from a sampling circuit is A/D-converted and the DPSK demodulation is conducted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a carrier wave whose phase is modulated by data extracted from a digital signal (so-called PSK (Phase
Shift Keying, Phase Shift Keying] East leg of No. B.

Regarding the PSK demodulator for restoring data ('1-7).

In the following, DPSK (Differential Ph
ase ShiftKeying, differential phase shift variable)
The present invention will be explained as an example of PSK.

DI) SK A delay detection method is a method often used for the field I4 of a K-modulated signal. In this method, DPSK demodulation is performed by combining with No. 46 delayed by a time corresponding to l symbols, but the phases of the carrier components of both must match with a fairly high degree of accuracy. For this purpose, a high-precision delay line or a means equivalent to a delay line is required, and it has drawbacks such as difficulty in adjusting the delay time and poor yield of the delay line.
Ru. Another problem is that stability sometimes deteriorates due to temperature characteristics of the delay line, changes over time, etc.

Figure 1 is a block diagram showing the configuration of the delayed detection method D P and SK demodulator. A filter, 5 is a determination circuit, and 6 is an output.

Fig. 2 is a signal waveform diagram for explaining the operation of the device shown in Fig. 1. The waveform signal is input to the DPSK signal input terminal in Fig. 1. That is, the two-phase DPSK signal (Fig. 2 (C))
inverts the phase of the carrier wave ta+ if the data is 1, and 01
Equations are obtained by continuing the previous phase. Second
(dJ is the output waveform of the l-symbol delay line 2 in Figure 1. TE+ in Figure 2 is the output waveform of the delay line 3, (f
) is the low-pass filter 40 output waveform. '(m is the data adjusted by the signal judged by the judgment circuit 5 in Fig. 1. The original data is restored by the time corresponding to the symbol (M). However, if the delay exceeds the delay and the delay time is not set correctly (Fig. 3 tcI ,+(I
As shown in 1-7, the data has been restored. ICI, tdJ, (eJ, () in Fig. 3 respectively correspond to the waveforms with the same symbols in Fig. The carrier wave phase of the input signal and the one-symbol-delayed signal that is manually input are significantly different (・, it will be mistakenly transmitted. Therefore, at a high carrier frequency, the delay time is q!j K敲冨If it is set to 7.C, it will be blown (・.

As a way to solve this carrier phase problem, D
A method has also been considered in which the carrier wave component is removed before PSK demodulation, and then DPSK1 is performed at the base band. The column is shown in FIG.

In the figure, 7.8.14 is a mixer, 9 is a 906 phase shifter, 10 is a voltage controlled oscillator, 11.12 is a low pass filter, 13
is a Rougoo filter, and 15 is a DPSK tone tuner.

The circuit shown is for the Co5tas (also known as Co5tas).
) loop, this loop demodulates the two-phase phase modulator, and from its output (base band) l))'5KOiI
Perform the back round using p unit 15. In this case, it is necessary to synchronize the phases of the carrier wave and the reference signal (output of the voltage-controlled oscillator 10) by assembling a closed circuit, and the adjustment is complicated.

The object of the invention is therefore to
'SK demodulator is provided.

In order to achieve the above object, the PSK demodulator according to the present invention includes a first reference signal having the same frequency as the carrier frequency;
a first low-pass signal having a fringe reference signal having a phase difference of 90° with respect to the first reference signal, and obtained by multiplying the input signal and the first reference signal in a multiplier; A second low-pass component obtained by multiplying the input signal and the second reference A multiplier is extracted as carrier phase information, and the first and second low-pass component A means for analog-to-digital conversion, a storage device that stores the time corresponding to the digital No. 46 Vt symbol obtained in this way, and a comparison between the digital signal and the digital signal stored l symbol before in the storage device. death,
The gist of the present invention is to have a means for determining whether the phase difference is θ or θ±180°. In an advantageous embodiment of the invention, P, SK are DPSK and, by analog-to-digital conversion, the digital signal obtained corresponds to one symbol j untimes earlier than that obtained in a similar procedure. , compared with the digital signal stored in the storage device, DPSK demodulated, and stored in the storage device,
This will prepare you for the next comparison.

Hereinafter, the present invention will be described in more detail with reference to the drawings, but these are merely illustrative and do not go beyond the scope of the present invention. Of course, improvements can be made.

FIG. 5 is a block diagram showing the configuration of a DPSK demodulator according to the present invention, in which 16.17 is a mixer, 18 is a reference oscillator, 19 is a 90' phase shifter, 2fl, 21 is an integrator and dumper, 22 .23 is a sampling circuit, and Sae is a digital DPSK demodulator.

In Fig. 5, if the phase difference lθ between the reference generator and the input signal is output from the sampling circuit η and the input signal, then the outputs are l/2 cosθ and l/2sinθ, respectively.
It is. That is, each time the phase based on the output of the standard excavator is measured. Hereinafter, this will be referred to as a phase difference. The phase difference θ is jan-1(sinθ/
cos θ).

Now, the present invention will be explained in detail by taking as an example the case where DPSK (ii) of binary phase keying is demodulated.

In two-phase phase modulation, if one phase difference is θ, the other phase difference is θ+180° (or θ−180°). DPSKo) Demodulation is performed as follows: If the phase difference before l symbols is θ, then if the phase difference after l symbols is θ,
For example, the data may be 0, θ+180° (or θ−
180'), then II IP is performed. The phase difference θ between the input signal and the reference oscillator is measured by two orthogonal reference signals obtained from one reference optical device.

The principle is shown in Figure 6.

The horizontal axis of FIG. 6 represents the direction of the 10th reference signal 'Jk: front vector passing through the path 25 in FIG. represents the direction of n is the human input signal vector, and thus 4 and 4 respectively represent the components of the input signal in the direction of the vectors representing the first and second reference signals. That is, the human input signal is decomposed into vectors representing two mutually orthogonal reference signals and input into the digital DPSKI adjustment system. output from the sampling circuit,
These two pieces of phase difference information are each subjected to Δ/D conversion, and the A/D converted signal is stored in memory for a time corresponding to l symbols, and is output at υPSK demodulation is performed by digitally comparing the A/D-modified signal with the A/D-modified signal.

FIG. 7 is a block diagram corresponding to FIG. 5 showing more specifically the configuration of the digital DPSKI adjuster 24, in which the phase difference information of the two input signals obtained by the sampling circuit η and The conversion converters 31 and 31 are manually powered and converted to /Dyk respectively. The ^/D-converted signal is compared with the memory 32 and that information storing l symbols previous information in digital comparators and 34, respectively. Further, the outputs of the A/D converters 31 and 31 are compared with each other by the digital comparators 34 and 34, and are stored in the memories 32 and 34 and compared with the information after one symbol. The digital comparator and its output are judged by a judgment circuit 36, and the judgment circuit 36 outputs a DPSK demodulated signal.

Although the present invention has been described above for the vDPsKv sequence, it is clear that the present invention can be applied to all PSK modulated signals.

As explained above, in contrast to the conventional delayed detection method, in which synchronization must be accurately achieved at °C, according to the present invention, the detected phase difference is 0 or θ±tso'. Since the signal is detected digitally, there is no need for synchronization, and various inconveniences caused by delay lines can be eliminated. If you can do this, the benefits will be realized.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a conventional delayed detection type D P S K repeater. Figures showing the waveforms in Figure 3 (C), tdL (e) and (fJ are the Irz diagrams where the delay time of the delay line is not set correctly. tcL tdll (e) and (
The figure corresponding to f), Figure 4, uses Kostas Loopun.
A block diagram showing the structure of a conventional DPSK converter, No. 5
FIG. 6 is a block diagram showing the configuration of the DPSKIX device according to the present invention, FIG. 6 is a diagram for explaining the human input signal according to the present invention, and FIG. 7 is a DPSKIX device according to the present invention.
FIG. 6 is a block diagram showing the demodulator configuration 2 more specifically than in FIG. 5; ■...DPSK (i! No. input terminal, 2...L symbol delay line, 3...Mixer, 4.11.12...Low pass filter, 5...Judgment circuit, 6...・Output, 7.
8+ 14. l6117°... mixer, 9,19.
...906 phase shifter, lO...voltage controlled oscillator, ]3.
...Loop filter, 15...DPSK demodulator, 1
8...Reference gain/loss, addition, 21...Integrator and dumper, thorn, mu...sampling circuit, 24...Digital power type DPSK demodulator, 5...I o) Reference signal Path, 26... Path of second reference signal, 2'l...
・Vector representing input signal 2, 4...first reference 1g
4...Vector representing the second reference signal, 30.31.../D converter, 32.35
...The time memory corresponding to the l symbol, Kan, 34.
...Digital comparator, 36...judgment circuit. Figure 1, Figure 2, Figure 3 (9) □ Figure 4, Figure 5, Figure 6 Procedural amendment (1 vision 1) Indication of the incident 1988 Q Joint application No. 122172 2 Name of the invention PSK reproduction 1 IAL device 3 Relationship with the case of the person making the amendment Address and name of the person making the amendment (148) Clarion Co., Ltd. 4 agents 〒1
05 Address: Shiba 3-chome Building 5, 3-2-14 Shiba, Minato-ku, Tokyo
Detailed explanation of the invention in the specification to be amended

Claims (1)

[Claims] tU Demodulation of a so-called PSK signal in which the phase of a carrier wave is modulated with data consisting of a digital signal. A PSK demodulator for restoring data has a first reference signal having the same frequency as the carrier frequency and a second reference signal having a phase difference of 90' with respect to the first reference signal, and inputs signal, the first reference signal and the multiplier t.
A first low-pass component obtained by multiplying the input signal by the second reference signal and a second low-pass component obtained by multiplying the input signal by the second reference signal are extracted as carrier phase information, and means for converting the first and second low-pass components from analog to digital; a storage device for storing the time corresponding to the digital signal 'kl symbol thus obtained; A PSK demodulator characterized in that it has a means for comparing the digital signal stored l symbols before and determining whether the phase difference is 0 or θ±180'. (2) PSK is DPSK, and the digital signal obtained by analog-to-digital conversion is better than that.
obtained by a similar procedure before the time corresponding to the symbol,
DPSK is compared with the digital signal stored in the storage device.
The PS according to claim 1, wherein the PS is demodulated and stored in a storage device in preparation for the next comparison.
K demodulator.