JPS60143687A - Method of forming solder - Google Patents
Method of forming solderInfo
- Publication number
- JPS60143687A JPS60143687A JP25128283A JP25128283A JPS60143687A JP S60143687 A JPS60143687 A JP S60143687A JP 25128283 A JP25128283 A JP 25128283A JP 25128283 A JP25128283 A JP 25128283A JP S60143687 A JPS60143687 A JP S60143687A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- conductor
- conductor portion
- paste
- printing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、配線基板上の導体部分に半田を形成する方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of forming solder on conductor portions on a wiring board.
従来例の構成とその問題点
一般に配線基板１上に形成された導体部分２の導体抵抗
を下げる為に、導体抵抗を下げようとす２、−
る導体部分に半田４を形成する方法が用いられている。Conventional Structures and Problems Generally, in order to lower the conductor resistance of the conductor portion 2 formed on the wiring board 1, a method is used in which solder 4 is formed on the conductor portion 2, which is intended to lower the conductor resistance. It is being
この場合、対象とする導体部分全体に半田を形成するの
が一般的である。In this case, it is common to form solder over the entire target conductor portion.
ところが、ペースト半田を印刷もしくは塗布し、加熱に
より溶融させて対象導体全体に半田を形成する方法では
、印刷もしくは塗布されるペースト半田の量のばらつき
や導体部分の形状によって半田が溶融した時の表面張力
により半田の形成が不均一となり、第１図に示すように
半田形成ができない部分５が発生したり、半田が片寄っ
て突起６が発生してしまうことがしばしばあり問題であ
った０
発明の目的
本発明はこのような従来の欠点を除去するものであり、
簡単な構成で導体部分への半田形成を均一に信頼性高く
形成することのできる方法を提供することを目的とする
。However, with the method of printing or applying paste solder and melting it by heating to form solder over the entire target conductor, the surface when the solder is melted may vary due to variations in the amount of paste solder printed or applied and the shape of the conductor part. The tension often causes uneven solder formation, resulting in areas 5 where solder cannot be formed as shown in FIG. 1, and the solder is uneven, resulting in protrusions 6, which is a problem. Purpose The present invention obviates such conventional drawbacks,
It is an object of the present invention to provide a method that can uniformly and reliably form solder on a conductor portion with a simple configuration.
発明の構成
本発明の半田形成方法は、配線基板上に形成された半田
形成しようとする導体部分に少なくとも３ ＼−
１ケ所以上の半田レジスト材を印刷もしくは塗布により
形成し導体部分を半田レジスト材により複数個の導体に
分割し、この分割された導体部分それぞれにペースト半
田を印刷もしくは塗布する。Structure of the Invention The solder forming method of the present invention includes forming at least three or more solder resist materials on a conductor portion to be soldered on a wiring board by printing or applying the solder resist material to the conductor portion. The conductor is divided into a plurality of conductors, and solder paste is printed or applied to each of the divided conductor parts.
そして、印刷もしくは塗布されたペースト半田を加熱し
溶融させ、分割された導体部分それぞれに半田を形成す
るものである。Then, the printed or applied solder paste is heated and melted to form solder on each of the divided conductor parts.
実施例の説明 以下、本発明の一実施例を第２図を参照して説明する。Description of examples An embodiment of the present invention will be described below with reference to FIG.
第２図ａ、ｂに示すように、配線基板７上に形成された
導体部分８に半田レジスト材１０ ａ 、１０ｂ。As shown in FIGS. 2a and 2b, solder resist materials 10a and 10b are applied to the conductor portion 8 formed on the wiring board 7.
１０Ｃを印刷もしくは塗布により形成し導体部分８を複
数に分割する・この時形成される半田レジスト材１０ａ
、１０ｂ、１０ｃ の太さは適度な太さとし、太くな
り過ぎないようにする。またこの半田レジスト材１０ａ
、１０ｂ、１０ｃは他の半田レジスト材９を形成する
時に同時に形成することができる。10C is formed by printing or coating and the conductor portion 8 is divided into a plurality of parts.Solder resist material 10a formed at this time
, 10b, and 10c should be of appropriate thickness and should not be too thick. Also, this solder resist material 10a
, 10b, and 10c can be formed simultaneously when other solder resist materials 9 are formed.
このように半田レジスト材１０ａ 、１０ｂ、１０ｃに
よって分割された導体部分８にそれぞれペースト半田１
１ａ、１１ｂ、１１ｃ、１１ｄを印刷もしくは塗布し、
加熱することによりペースト半田１１ ａ 、１１ｂ。Paste solder 1 is applied to each of the conductor parts 8 divided by the solder resist materials 10a, 10b, and 10c in this way.
Print or apply 1a, 11b, 11c, 11d,
Paste solder 11a, 11b by heating.
１１ｃ、１１ｄを溶融させ導体部分８それぞれに半田形
成する。11c and 11d are melted and soldered to the conductor portions 8, respectively.
発明の効果
以上のように本発明は、配線基板上に形成された半田形
成しようとする導体部分に半田レジスト材を印刷もしく
は塗布することにより形成して導体部分を複数個に分割
し、それぞれ分割された導体部分において半田を印刷も
しくは塗布し、加熱することにより半田を形成するもの
で、それぞれの導体部分の導体形状が均一化され、ペー
スト半田の量のばらつきに影響されることなく安定な均
一の半田形成ができるものである。また、分割により半
田形成しようとする導体長さが短くなるので表面張力の
影響により半田が片寄ったり、突起が発生したりするこ
とがないという利点を有する。Effects of the Invention As described above, the present invention is formed by printing or applying a solder resist material to a conductor portion to be soldered formed on a wiring board, dividing the conductor portion into a plurality of parts, and dividing each conductor part into a plurality of parts. Solder is formed by printing or applying solder on the solder conductor parts and heating it.The conductor shape of each conductor part is made uniform, and stable uniformity is achieved without being affected by variations in the amount of solder paste. It is possible to form solder. Furthermore, since the length of the conductor to be soldered is shortened by dividing, there is an advantage that the solder is not biased or protrusions are not generated due to the influence of surface tension.
第１図ａ、ｂは従来例の半田形成を示す平面図５ ＜−
および断面図、第２図ａ、ｂは本発明の一実施例による
半田形成方法により形成された基板の平面図および断面
図である。
７・・・・・・配線基板、８・・・・・・導体、１０ａ
、１０ｂ。
１０Ｃ半田レジスト材、１１ａ、１１ｂ、１１ｃ。
１１ｄ・・・・・・ペースト半田。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図1A and 1B are plan views and cross-sectional views showing conventional solder formation, and FIGS. 2A and 2B are plan views and cross-section views of a substrate formed by a solder formation method according to an embodiment of the present invention. It is a diagram. 7... Wiring board, 8... Conductor, 10a
, 10b. 10C solder resist materials, 11a, 11b, 11c. 11d...Paste solder. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure
Claims (1)
上の半田レジスト材を印刷もしくは塗布によシ形成して
前記導体部分を複数個の半田を形成しようとする導体部
分に分割し、分割された各導体部分それぞれにペースト
半田を印刷もしくは塗布し、加熱することによシ前記ペ
ースト半田を溶融させ、前記分割された導体部分それぞ
れに半田を形成するようにしたことを特徴とする半田形
成方法。A solder resist material is formed at least one place on a conductor portion formed on a wiring board by printing or coating, and the conductor portion is divided into a plurality of conductor portions on which solder is to be formed. A solder forming method comprising printing or applying paste solder on each conductor portion, melting the paste solder by heating, and forming solder on each of the divided conductor portions.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25128283A JPS60143687A (en) | 1983-12-29 | 1983-12-29 | Method of forming solder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25128283A JPS60143687A (en) | 1983-12-29 | 1983-12-29 | Method of forming solder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60143687A true JPS60143687A (en) | 1985-07-29 |
Family
ID=17220479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25128283A Pending JPS60143687A (en) | 1983-12-29 | 1983-12-29 | Method of forming solder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60143687A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01238193A (en) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | Soldering of chip element to printed wiring board |
| US7300083B2 (en) | 2005-07-01 | 2007-11-27 | Masahito Hamazaki | Tongs |
-
1983
- 1983-12-29 JP JP25128283A patent/JPS60143687A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01238193A (en) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | Soldering of chip element to printed wiring board |
| US7300083B2 (en) | 2005-07-01 | 2007-11-27 | Masahito Hamazaki | Tongs |
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