JPS60143647A - Integrated circuit chip structure for reducing inductance ofcircuit and provicing voltage gradient controlled - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to large scale integrated circuit chips and, more particularly, to reducing inductive crosstalk that can cause signal errors on a chip, The present invention relates to a wiring configuration or arrangement for such a chip to provide a more uniform voltage distribution.

As continued developments occur in the field of microelectronics and integrated circuit technology, large-scale integration (L
The operating speed, size, and circuit density of SI) and very large scale integration (VLS) logic chips are constantly increasing. One phenomenon that has, to date, received little or no consideration in the design of these chips because it has not posed a significant problem is the effect of the magnetic fields generated by the current path loops on the chip. Smaller chips, e.g. 1, .
In chips with 000 gates or less, the magnetic field is extremely weak and does not have any noticeable effect on the signal current. However, as circuit densities and speeds on chips continue to increase, the effects of this magnetic field become increasingly important.

In conventionally wired chips, 8-current is typically injected onto the chip through bonding pads located at the corners or sides of the chip, and also through bonding pads located at diagonally opposite corners or sides of the chip. Another bonding pad located on the opposite side of the gate is connected to a ground reference potential to sink current from the gate. Thus, a current path is established from one corner or side of the chip to the opposite corner or side of the chip, and the current path is looped back to the pad into which the current was injected, It covers a considerable part of the area. For example, referring to FIG. 1, an integrated circuit chip 10 may have a number of logic gates 12, each connected in parallel with each other between a power bus 14 and a ground bus 16. has been done. As shown in FIG. 1, the logic gates 12 are divided into two rows, and the power and ground buses are also divided into two parallel conductive lines, each of which has two rows. It is connected to the. However, a chip may have only one row of logic gates, or it may have many rows, each row provided with a separate conductive line. The particular number of rows of logic gates connected in parallel is determined by the circuitry provided on the chip and the design layout principles used.

The chip of FIG. 1 shows a conventional wiring arrangement for supplying and sinking current to and from individual logic gates. More specifically, a power bus 14 is connected to a bonding pad 18 located at one corner of the chip. This pad is further connected to one of the pins within the chip package, which is supplied with current from a suitable source. Ground bus 16 is also connected to a bonding pad 20 located on a diagonally opposite corner of the chip from pad 18. Pad 2o is connected to a suitable ground reference potential via a connection pin of the chip package.

In a somewhat different wiring configuration, the current supply pad 18
can be located close to the center of the top edge of the chip, and the current sink pad can be positioned close to the center of the bottom edge of the chip, rather than on diagonally opposite corners. Is possible.

To explain the operation, the current flows through the bonding pad 18.
to ground bus 16 and to bonding pad 20 through various conductive logic gates 1-1. A current return path extends from the bonding pad 20 to a pad 18 that is separated by at least the diagonal dimension of the chip package. This current flow path is schematically shown in dotted lines in FIG. 1 for the case in which the one to the logic gates 1 of the upper row is in the conducting state. Similar flow paths are established when each gate is in a co-conducting state. In practice, this return path is formed by conductive traces on a printed circuit board (not shown) on which the chip is mounted. These lines extend from the connection pins associated with the bonding pads 18 and 20 to edge connectors on the circuit board that are connected to the power supply.

As can be seen, the area enclosed by the current loop is
Even in its smallest case, it occupies a significant portion of the area of an integrated circuit chip. During a clock cycle, changes in the switching states of logic gates on the chip can be large enough to cause significant changes in the amount of current flowing from pad 18 to pad 20, and due to this changing magnetic field. Currents induced in conductors on other chips may be sufficient to cause logic errors. More specifically, during a clock cycle, multiple gates can change state sequentially.

Switching operations that occur later in a series of gates during the same clock cycle can inductively trigger state changes at earlier times, thereby generating logic errors.

The likelihood of such errors occurring increases as the density of chip integration increases. For example, on a VLSI chip with 10G gates, the number of gates switching in one direction during a given clock cycle exceeds the number of gates switching in the opposite direction by at most 20,000. Sometimes. Assuming the total current supplied to the chip is 25 amps, each individual logic gate receives 25 microamps,
A net change in state of 20,000 gates will result in the current flowing through the chip being increased or decreased by 172 Amps. These changes, in more detail,
The electromotive force generated by such a change can be significant considering that the voltage levels typically used in IC chips are relatively low. For example, the difference between a logic high and logic low state may be as low as 0.1 volt. If the magnetic field inductively generated by the current change is large enough, it can influence the voltage on the signal lines within the chip, and 1
One logic state is incorrectly detected as another, resulting in a logic error.

Since the total magnetic flux generated by a current loop is the product of inductance and current, if it is possible to reduce the inductance of the chip, the possibility of logic errors caused by inductively generated magnetic fields is also reduced. Ru.

13- The inductance L generated by the current loop can be defined as:

L=μ, A/2πR where μ0 is the effective magnetic permeability of the area on the chip where the magnetic field exists, A is the area surrounded by the current loop,
R is the average radius of the loop.

Thus, the size of the inductance is directly related to the area of the current loop. More specifically, it is directly proportional to the average radius of the loop (because A=πR2). If it is possible to reduce the area within the current loop, the possibility of inductive interference between circuits can also be reduced. This is because magnetic field strength is directly proportional to inductance for a given current level.

SUMMARY OF THE INVENTION The present invention has been conceived in view of the foregoing and has a general object to reduce the possibility of crosstalk caused by inductive interference in circuitry on a chip. A more specific object of the present invention is to provide a novel wiring configuration or arrangement capable of reducing the area on the chip surrounded by current loops compared to the prior art. is to reduce the inductance of the circuit. Yet another object of the invention is to provide a uniform voltage distribution to the individual gates on the chip so that each gate receives the same amount of current.

According to one feature of the invention, the area surrounded by the current path on the chip replaces the conventional location of the bonding pads where the current sources and current sinks are connected to the logic gates, respectively. reduced by These pads, according to the invention, are not placed, for example, on opposite sides of the chip, but physically adjacent to each other. The area of the current loop can be further reduced by locating the power and ground buses adjacent to each other for the logic gates. Ideally, these two buses could be superimposed one on top of the other on different metal layers of the chip, in which case the spacing between these buses would be equal to the separation separating the two metal layers. It's just the layer thickness.

According to another feature of the invention, the voltage gradients at the gates on the chip are carried in each part of the conductor while ensuring that the overall length of the current path is the same for the current flowing through each gate. By varying the cross-sectional areas of the power and ground buses depending on the magnitude of the current, the current is regulated to be the same for each gate.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As previously mentioned, one feature of the present invention is that it produces a net change in the current flow on the integrated circuit chip, mitigating potentially error-causing noise that is inductively generated during switching cycles. It is to let According to the present invention, the area of the current loop on the chip is reduced, and in one embodiment, the current sink pad 2o
This is achieved by moving the location of the current supply pad 18 on the chip closer to the location of the current supply pad 18. An example of implementing this principle is shown in FIG. As understood from Figure 2,
The wiring configuration of the chip is generally similar to that shown in FIG. 1, but the physical location of the bonding pads 20 is different. In this case, pad 20 is located physically adjacent pad 18. That is, as a result of changing the position in this way, the current source and current extraction paths are disposed close to each other, and the area between the two paths is reduced. By varying from the conventional, the area on the chip surrounded by the current loop is substantially reduced, as shown by the dotted line.

As used in connection with the present invention, the expression "in physical proximity" does not necessarily mean that bonding pads 18 and 20 are two pads that are next to each other on a chip. do not have.

Rather, it can be interpreted in a somewhat broader sense,
It is related to the location of these two pads relative to the logic gate. Thus, while in the most preferred embodiment of this aspect of the invention the current source and current sink pads are consecutive pads on the same side of the chip, in practice the power and ground pins are at least one contiguous pad on the same side of the chip. The design may require that the two pins be separated by one pin. In such a case, according to the present invention, even if these bonding pads are not adjacent to each other, they are physically located as close to each other as possible and according to the layout of the chip with respect to the arrangement of the logic gates. located on the same side.

A modification of this first feature of the invention is shown in FIG. In this modification, the power supply bonding pad 18 is located approximately in the middle of one end of the chip. A ground bus 16 is provided with its ends connected to two bonding pads 20 and 21, respectively. These pads are arranged on both sides of the power supply pad 18, respectively. The advantage of this arrangement is that it is possible to balance the current paths on the chip. That is, the magnetic field generated by the current flow in one of the current paths indicated by the dotted line reduces the effect of the magnetic field generated by the current flow in the other current path, because:
This is because current flows in opposite directions in these two loops.

On the other hand, the same effect can be achieved by connecting the ground bus 16 to a single pad and connecting the power bus to two pads on either side of the ground pad.

In the embodiment of FIGS. 2 and 3, power bus 14 and ground bus 16 are each located on opposite sides of the logic gate. By separating by the width of the gate in this way,
The spacing between the power supply bus and the sink bus is narrowed, significantly reducing the area encompassed by the current loop. Although the embodiments of FIGS. 2 and 3 significantly reduce the current loop area compared to the conventional structure shown in FIG. 1, additional modifications can be made to further reduce the inductance of the circuit. It is possible. An embodiment regarding this point is shown in FIG. In this embodiment, both current buses are located on the same side of the logic gate;
These current buses therefore extend adjacent to each other. It can be seen that in this embodiment the area covered by the individual current loops is further reduced. Therefore, the inductance of the circuit is reduced as well, thereby reducing the possibility of logic errors occurring.

In a preferred embodiment of the above aspect of the invention, the area enclosed by the current loop is minimal. However, when all other design conditions are taken into account, it may not be possible to minimize the current loop area without adversely affecting other parameters. Therefore, the practical implementation of the invention is to reduce the area of the current loop as much as possible without making significant compromises with other design considerations.

A more detailed example of an integrated circuit chip embodying some of the principles of the invention is shown in FIG. The circuit configured in the chip shown in FIG. 5 is, for example, a MO
S memory circuit, for example ROM. MOS memory circuits are used here to explain the invention because they are relatively simple and easy to understand. However, those familiar with integrated circuit technology will appreciate that the invention is not to be limited thereto, and can be applied not only to memories, but also to virtually all types of circuits and other types of integration, such as bipolar, 2L, etc. It is applicable to technology. In fact, a particularly preferred application of the invention is in the field of high speed bipolar logic gate chips. because,
This is because these types of gates are more sensitive to voltage transients than those of other technologies.

Referring to FIG. 6, the memory circuit is connected to bit line 22.
and 24 and word lines 26, 28, and 30.

Each bit line is connected to a power supply via a load FET 32. Each bit line also has a data output or read terminal 34.
connected to.

The memory elements whose locations and connections determine the information stored within the chip are comprised of FETs QI through Q4, whose gates are connected to respective word lines 26 through 30.
and their drain terminals are connected to bit lines 22 and 24, and their source terminals are commonly connected to a ground reference potential.

In operation, binary signals applied on word lines 26-30 have input addresses and output data is read at bit line terminals 34''. More specifically, if a binary 1 is represented by a high voltage level, e.g. 5 volts, and a binary 0 is represented by a low voltage level, e.g. Each word line that appears is a memory F whose gate is connected to that line.
Make ET conductive. This action causes the bit lines connected to the drain terminals of these FETs to ground, thereby representing a binary 0 at their respective output terminals. Conversely, when a word line is in the binary O state, the memory FETs connected to that line are off, and when all memory FETs connected to the bit line are off,
That line will be in a high state. In short, all the memory FETs connected to the bit line are integrated into the NOR gate 1.
The word line is an input terminal with 22
- Yes and the bit line is an output terminal.

Therefore, in general, when most address bits are binary O's, the current through the chip is relatively low since most memory FETs are off. On the other hand, if most address bits are binary ones, the current flow will be higher. If, in any given clock cycle, the O:1 bit ratio in the address word changes significantly, it will result in a significantly greater number of memory FETs being switched in one direction than those being switched in the opposite direction. , a substantial change occurs in the net current flow through the chip. If the inductance of the circuit is large enough, the electromotive force generated by the current change can affect the signals appearing on word lines 26-3o and may cause errors in the output data.

Of course, this general consideration applies to memory F relative to the word line.
It varies depending on the distribution of ET, which in turn depends on the specific information stored in the ROM.

Referring to FIG. 5, the drain and source elements of the various FETs are formed as diffusion tracks 36 in substrate 38. For example, these diffusion tracks can be of N-type material and the substrate can be of P-type material.

These diffusion tracks are parallel to each other and the load F
Extending substantially along the length of the chip except for cuts in every other track used to form the ET. A layer 39 of a suitable insulator, such as silicon dioxide, is deposited over the substrate and the diffusion tracks and then suitably etched using known techniques to reduce the thickness in the region of overlap of two adjacent diffusion tracks, with the Give the FET gate to . A layer of silicon dioxide is then deposited on the parallel rows of conductor tracks 40, which constitute the word lines of the circuit. The portions of the silicon dioxide layer whose thickness has been reduced and which are covered by these conductive lines are
Determining where the memory FET is located in the circuit and determining the information stored therein.

Each word line is connected to a suitable bonding pad 42 located adjacent one end of the chip.

Every other diffusion track 26, ie each uncut 1-rack, forms a bit line for the circuit. These tracks are suitably connected to bonding pads 44 disposed on the bottom edge of the chip, so that stored logic data can be read therefrom.

In addition to the conductive line 4o forming the word line, two additional lines 46 and 48 are provided on the chip, which provide a power bus and a ground bus, respectively. In the past, ground buses connected to other diffusion tracks that did not form bit lines of the circuit were sometimes located at the bottom of the chip, as shown in FIG. However,
According to the invention, it is arranged adjacent to the power supply bus 46. This power bus is connected to short cut portions of every other diffusion track that constitute the drain terminals of the load FETs, and to the gates of these FETs. A cross section of the chip taken along the length of power bus 46 is shown in FIG.

Although the embodiments of FIGS. 4 and 5 are effective in substantially reducing the area of current loops established on the chip, the best method is to overlap the power and ground buses on top of each other on the chip. There should be no space between the two on the plane. This variant can be easily implemented when using two-layer or multi-layer metallization during chip fabrication. An example of such a variation is shown in FIG. 8, in which a second layer 47 of silicon dioxide or other suitable insulating material is placed over the power supply bus 46 as shown.
A conductive line forming a ground bus 48 is deposited on this insulating layer. Although the embodiment of FIG. 8 shows that the ground bus and power bus are provided in adjacent metal layers separated only by the thickness of the intermediate insulating layer 47, it will be appreciated by those skilled in the art that the embodiment of FIG. As is clear,
These two layers need not be adjacent metal layers;
Ground and power buses can be provided in metal layers located almost anywhere within the thickness of the chip.

The basic principle of the invention regarding the above points is to reduce the area of the current loop on the chip in order to reduce the inductance of the circuit compared to the prior art, and to reduce the possibility of inductively generated digital errors. to reduce;
is applicable to any type of integrated circuit technology, limited only by the specific design criteria for that technology and the specific circuitry provided within the chip. For example, certain technologies may require a small space between the power and ground buses, and other designs may require the buses to be spaced apart to accommodate signal lines. Sometimes it is necessary to do so.

However, within such limitations, it is still practical to use the concepts disclosed herein.

According to another feature of the invention, the voltage gradients in the power and ground buses are controlled so that the same amount of current flows through each logic gate or stage.

Since the resistance to current flow is directly proportional to the length of the conductor through which the current must flow, voltage gradients are established along each of the power and ground buses. If this voltage gradient is uncontrolled or something that comes out of the chip's design, the current flowing through the various logic gates connected along the length of the power and ground buses. Sizes may vary. If this happens, current differences between the gates can cause logic errors or other failures. For example, in integrated injection logic (I2L), the current in a common emitter switching transistor or common base current injection transistor may be exponentially directly proportional to the voltage difference between the power bus and the ground bus. Therefore, for each logic gate connected to it, these two
It is desirable for the same voltage difference to exist between the two buses, and it is desirable for all gates to operate with the same amount of current.1,N.

To further extend this objective, two basic principles are used in the design of the power and ground buses. First, at the connection point to the gate, the direction of current flow is the same on both buses. With this approach, the combined length of the power and ground buses through which current must flow is the same for all gates. To explain the ninth section, the current flow direction in the power supply bus 14 is from left to right in the drawing. Similarly, gate 12
Current flows in the same direction in the portions of the ground bus 16 that are connected to the ground bus 16.

Therefore, the leftmost and rightmost game h shown in the drawing
Focusing on G1 and G6, the current path in the power bus 16 for the current supplied to the rightmost gate G6 is 5 units longer than for the leftmost gate G1, in this case the unit conductor length. is equal to the distance between the connections of two adjacent gates to the power supply bus. However, on the ground bus, the rightmost gate G
The current path for the current from 6 is the leftmost gate G1
It is shorter by the same 5 unit length than that for . The same relationship holds for all other gate pairs 28-. Therefore, the total current path from the power to ground pad is the same for all gates connected to the power and ground buses.

After the final connection, the ground bus 16 is looped back in the direction of current flow to position the power and ground bonding pads physically adjacent to each other in accordance with the aforementioned features of the invention. There is. The return portion of this ground conductor is shown in FIG. 9 as being located within the gate, but as explained in connection with FIG.
It is possible to superimpose the return part in a separate layer on the connection part of the ground bus.

The second design principle used to control voltage gradients concerns the cross-sectional area of the bus. More specifically, the cross-sectional area of each unit length is directly proportional to the amount of current carried by that unit length. Referring again to FIG. 9, there is a step in the width of each of the power bus and ground bus, and each conductor is widest where the current is greatest, and narrowest where the current is the smallest. It is the smallest. According to this configuration, the current density in each conductor is constant over the entire length of the conductor. Therefore, the voltage drop along each unit length of the conductor is the same and the voltage gradient across the gates is uniform.

Typically, the height of each conductor is the same throughout its length due to the metallization process used to deposit the metal layer on the substrate. Therefore, the cross-sectional area of the conductor can be controlled by adjusting its width.

In other words, the width of each unit length of conductor is directly proportional to the current carried in that portion of the conductor.

As shown in FIG. 9, variation in the width of each conductor is provided by placing discrete steps along the length of the conductor. On the other hand, it is also possible to use a uniform taper along the length of the conductor, but in the case of discrete steps computer-aided design of integrated circuit chips, so-called CAD, is more easily adapted. Therefore, it is more suitable. Furthermore, the change in the magnitude of the current in the conductor is not continuous but occurs at discrete points, ie, at the points where the gate is connected. Therefore, it is most logical to position the conductor width variations to match the load increments along the bus.

Since current flows in the same direction in the power and ground buses at the connection point to the gate, the width changes of these two buses are complementary to each other. It is therefore possible to fit these two conductors together, thereby saving space on the surface of the chip. More specifically, the total width of the area occupied by the two buses along a portion of their length and connected to the gate is the width of one of the buses at its widest point;
It is the sum of the spacing distance between two conductors and the width of the other conductor at its narrowest point. In contrast, two buses of constant width would occupy an area equal to the total width of each plus the spacing between them.

The control of the voltage gradient between gates has been described above with regard to the power bus and the ground bus. However, the principles described above are applicable to any conductor that supplies current to or receives current from a gate. for example,
In the case shown in FIG. 9, the current flows between each gate 12 and
A second set of conductors 50 and 52 are routed between buses 14 and 16. The total length of the current path along these conductors should also be the same for each gate.

To this end, the conductor 50 to the power supply bus 14 is connected to this bus along the end closest to the gate. This is because its ends are equidistant from each game 1. On the other hand, conductor 52 to ground bus 16 is connected to the end of the bus furthest from the gate. This is because this end is also located equidistant from each gate. Therefore, each pair of conductors 50 and 52 has the same length for all gates.

It is not necessary to connect conductors 50 and 52 to the ends of the bus, nor is it necessary that all conductors connected between one of the buses and the various gates have the same length. . Rather, the prevailing criterion is that the total current path from the power supply to the ground reference is the same for each gate.

Although specific embodiments of the present invention have been described in detail above, the present invention should not be limited only to these specific examples, and various modifications may be made without departing from the technical scope of the present invention. Of course, it is possible.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing a conventional wiring arrangement for an integrated circuit chip, FIG. 2 is a schematic block diagram showing a first embodiment of the wiring configuration for an integrated circuit chip according to the present invention, and FIG. is a schematic block diagram showing a modification of the wiring configuration shown in FIG. 2, FIG. 4 is a schematic block diagram showing a second embodiment of the wiring configuration based on the present invention, and FIG. 5 is a schematic block diagram showing a modification of the wiring configuration shown in FIG. 6 is an equivalent schematic electrical circuit diagram of the circuit shown in FIG. 5; FIG. 7 is a top view of a portion of an integrated circuit IC chip embodying some of the principles; FIG. 5 is a sectional view of the IC chip shown in FIG. 5, FIG. 8 is a sectional view of another embodiment of the chip structure shown in FIG. FIG. 2 is a schematic diagram of a wiring configuration showing consideration. (Explanation of symbols) 12: Logic gate 14: Power supply bus 16: Ground bus 18.20.21: Bonding pad Patent applicant
Fairiaild Camera and Instrument Corporation 35- Procedural Amendment January 11, 1985 Manabu Shiga, Commissioner of the Patent Office 1, Indication of Case 1988 Patent Application No. 1882
No. 56 No. 3, Relationship with the case of the person making the amendment Patent applicant 4, Agent 6, Number of inventions to be increased by the amendment None 7, Subject of the amendment Drawing (no change in content) 8, Contents of the amendment Attached sheet street

Claims (1)

[Claims] (1) A plurality of logic gates are provided, and the gates are connected in parallel between a power supply bus that supplies current to the gates and a ground bus that sinks current from the gates. In an integrated circuit chip, a wiring arrangement is located on the chip to reduce the possibility of inductive crosstalk occurring between circuits on the chip, allowing a power supply to be connected to the power supply bus. a first pounding pad connected to the power bus to provide a power supply bus; and a first pounding pad located physically adjacent to the first pad on the chip relative to the gate and connected to the ground bus. A wiring configuration characterized by having a second ponding pad. 2. Claim 1, characterized in that the Type 1 source bus and the ground bus are located physically adjacent to each other on the chip relative to the logic gates. Wiring configuration. 3. The wiring configuration according to claim 2, wherein the bus is located on a single layer of the chip. 4. The wiring structure according to claim 2, wherein one of the buses is provided on different layers of the chip so as to overlap above the other bus. 5. Claim 1, wherein one of the buses is connected to two pads, and a pad connected to the other bus is connected to the one bus. A wiring configuration characterized by being arranged between two pads. 6. Claim 1, characterized in that the cross-sectional area of the power bus and the ground bus is varied along their length depending on the magnitude of the current carried in the bus. Wiring configuration. 7. The wiring configuration according to claim 6, wherein the bus 2 has a stepped width. 8. The wiring arrangement according to claim 6, wherein the current flowing through each of the power bus and the ground bus flows in the same direction at least within a bus portion having a variable cross-sectional area. 9. An integrated circuit chip comprising a plurality of logic gates and having the gates I- connected in parallel with each other between a power supply bus that supplies current to the gates and a ground bus that sinks current from the gates. a method for reducing the likelihood of inductive crosstalk between circuits, the method comprising: locating the ground bus at a location physically adjacent to the location where the ground bus is connected to a ground reference potential relative to the logic gate; The method further comprises the step of reducing an area on a chip surrounded by a path of current flowing from the power bus to the ground bus via the gate by injecting current into the power bus provided. Method. 10. A method according to claim 9, comprising the step of arranging the power bus and the ground bus physically adjacent to each other relative to the ring gate. . 11. The method of claim 9, comprising maintaining a current density in each of the power bus and the ground bus substantially constant along the length of each bus. 12. Claim 11, characterized in that the cross-sectional area of each bus is varied along its length depending on the magnitude of the current carried, thereby maintaining the current density constant. How to do it. 13. The method of claim 9, comprising the step of maintaining the overall length of the path of current flowing through the gate the same for each gate. 14. Claim 13, characterized in that current flows in the same direction in each of the power bus and the ground bus at least along a length of each bus connected to the gate 1-. how to. =4-15, comprising a plurality of logic gates, and connecting the gates 1 to 1 in parallel with each other between a power supply bus that supplies current to the gates and a ground bus that sinks current from the gates. A wiring configuration in an integrated circuit chip in which the power bus and the ground bus are not physically located in the same side stop as the gates to which they are connected to reduce the area of current loops on the chip. The wiring configuration is characterized by: 16. The wiring configuration according to claim 15, wherein the power supply bus and the ground bus are located adjacent to each other in a single layer of the chip. 17. The wiring configuration according to claim 15, wherein the power supply bus and the ground bus are superimposed one above the other on different layers of the chip. 18. The wiring according to claim 15, characterized in that the cross-sectional area of the power bus and the ground bus varies along their length depending on the magnitude of the current carried in the bus. composition. 19. The wiring configuration according to claim 18, wherein the bus has a stepped width. 2. The wiring configuration according to claim 18, wherein currents flowing through each of the power bus and the ground bus flow in the same direction at least in a portion of the bus where the cross-sectional area changes. 21. In an integrated circuit chip having a plurality of logic gates connected in parallel between a power supply and a ground reference potential by a power supply bus and a ground bus, respectively, the same voltage gradient is applied across each gate connected to said bus. The method includes the steps of: maintaining the same overall length of the current path from the power supply to the ground reference potential for each gate; and varying the cross-sectional area of the bus depending on the magnitude of the current being conducted. A method characterized by having. 2. Claim 21, characterized in that current flows in the same direction in each of the power supply bus and the ground bus at least along the length of each bus connected to the gate. How to do it. 23, a plurality of logic gates electrically parallel to each other;
A power bus connects each gate to a power supply and has a cross-sectional area that varies along its length depending on the magnitude of the current being conducted, and a power supply bus connects each gate to a ground reference potential for conduction. and a ground bus having a cross-sectional area that varies along its length depending on the magnitude of the current carried. 2. The integrated circuit according to claim 23, wherein each of the buses has a stepped width. 2. The integrated circuit of claim 23, wherein the current flowing through each of the power bus and the ground bus flows in the same direction, at least in the bus portions having varying cross-sectional areas.