JPS6014327A - Multiplying circuit for digital signal - Google Patents

Abstract

PURPOSE:To prevent the accumulation of errors of many multiplying circuits by detecting the maximum value of the control signal which controls the gain of a digital signal and adding the minimum until 1 to the output signal of a multiplier for output. CONSTITUTION:A digital signal is supplied from a terminal 1, and a gain control signal is supplied from a terminal 2. When both signals are set at the maximum value FF (hexadecimal), a detector 4 detects the maximum value FF of the control signal and supplies a high level to a switch 7. The switch 7 selects and delivers 1. For an adder 5, the multiplication result (FFXFF=FE01) of a multiplier 3 needs 16 bits and 01 is defined as an error as long as the result of multiplication is defined s 8 bits. However 1 is added to the FF of the multiplication result and therefore the FF is delivered. As a result, no addition is carried out with accumulation of errors for a multiplying circuit having its control input set at maximum 1 despite a multi-stage connection of such multiplying circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal multiplication circuit for controlling the gain of a digital television video signal.

Traditionally, multipliers have been used to control the gain of digitized video signals. The disadvantage is that the number of bits, etc.) increases. Furthermore, since this type of gain control circuit is generally connected in multiple stages within one device, multipliers with a larger number of bits are required in later stages. In order to prevent the number of bits from increasing, a rounding circuit or the like is required for each multiplier, which inevitably makes the circuit complicated.

SUMMARY OF THE INVENTION An object of the present invention is to solve two conventional drawbacks and provide a digital signal multiplication circuit that is simple and has practically sufficient multiplication accuracy.

The multiplication circuit of the present invention includes a multiplier that inputs a digital signal and a control signal for controlling the gain of the digital signal and multiplies the two input signals, and a detection circuit that detects the maximum value of the control signal. and the least significant bit of the output signal of the multiplier by the output signal of the detection circuit.
and an adder for adding up the multiplier, and when the control signal is at the maximum value, the output signal of the multiplier has a minimum unit "°
It is characterized by adding l°° and outputting it.

Next, the present invention will be explained in detail with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention. That is, a digitized television video signal is input from input terminal 1, and a control signal for gain control of the bifurcated video signal is input from input terminal 2. Multiplier 3 is
Although this is a multiplier that multiplies two input signals, the number of bits of the output signal is the same as the number of bits of the input signal. When the detection circuit 4 detects the maximum value of the control signal input from the input terminal 2, it outputs a high level to control the switching device. The switch 7 inputs the minimum unit signals "1" and 0 " outputted by the data generator 9 and the data generator 8,
When a high level is supplied from the detection circuit 4, “
When the output of the detection circuit 4 is at a low level, it selects and outputs "0".The adder 5 selects and outputs "0" from the output of the switch 7 to the least significant bit of the multiplication result 6 output from the multiplier 3. The signal “o” or t” is added and outputted to the output terminal 10.

As an example, the digital video input signal and the control signal are both 8 bits, and their values are respectively expressed in hexadecimal.
Considering the case of FF and FF, the multiplication result is FFX
FF=FEO1 (displayed in hexadecimal). That is, 16
Bits are required. If the multiplication result is 8 bits, then
If rounding or the like is not performed, the result will be FE and will contain an error of 01. If this is used as is, the above-mentioned errors will accumulate if the multiplication circuits are connected in multiple stages. It would be possible to perform rounding or truncating for each multiplication, but this would require a large number of circuits and become complicated. In this embodiment, at this time, the detector 4 detects that the control signal is at the maximum value (FF).
is detected, and supplies a high level to the switch 7, and the switch 7 selects and outputs "l", so the adder 5 outputs the multiplication result 6 (currently FE) of the multiplier 3. Add “1” and output. That is, it outputs FF. Therefore, even if such circuits are connected in multiple stages, there will be no error addition for the multiplication circuit whose control input has a maximum value of 1. In a multiplication circuit where the control signal does not have a maximum value of 1, but is between 0 and less than 1, an error will occur, but this error will occur in the minimum unit of 1°.
° or less.

Generally, when a multiplier circuit is used as a mixer for two television video signals, the two multiplier circuits are connected in parallel, and the control signals supplied to each are set to be mutually complementary between 0 and 1. There is. Then, since the control signal is changed from O to 1 and two video signals are switched during this time, only one signal is being switched, and the multiplier circuits connected in multiple stages are gain-controlled at the same time. There isn't. Therefore, no two-way errors are accumulated. Furthermore, the error during image switching is difficult to detect visually and does not pose a problem. The problem is to prevent errors from accumulating in a large number of multiplier circuits that are controlled by the maximum value 1 of the control signal among multiplier circuits connected in multiple stages. In this embodiment, when the control input is the maximum value 1, each multiplier circuit adds the value that causes a multiplication error and removes the error. Therefore, even when multiple multiplier circuits are connected in multiple stages, the correct result is obtained. This has the effect of providing.

As described above, in the present invention, when the maximum value of the control input is detected, the minimum unit ``1°'' is added to the output of the multiplier and output, so the circuit configuration is simple and there is no multiplication error. This has the effect of making gain control possible.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. In the figure, 1, 2: input terminal, 3: multiplier, 4: detection circuit, 5: adder, 6: multiplication result of multiplier 3, 7: switch, 8, 9: data generator, 10: output terminal. Applicant: NEC Corporation Agent: Patent Attorney: Toshimune Sumita

Claims (1)

[Claims] a multiplier that receives a digital signal and a control signal for controlling the gain of the digital signal and multiplies the two input signals; a detection circuit that detects the maximum value of the control signal;
an adder that adds a minimum unit of "1" to the least significant bit of the output signal of the multiplier according to the output signal of the detection circuit; A digital signal multiplication circuit characterized by adding and outputting the unit "1".