KR950004459B1 - Apparatus and method for detecting image transition region - Google Patents

Abstract

The circuit correctly detects the shift area of the video signal in the video equipment eg. television or VTR. The circuit comprises means (17) for detecting the shift area component by comparing the input video signal with the neighboring pixel, means (18) for detecting the shift area width by counting the detected shift area component, a ROM (20) for providing the output control data, and an output controller (21). The method includes the steps of identifying the shift area component and the shift area width, and providing the control signal responsive to the shift area width.

Description

Method and apparatus for detecting transition region of video signal

(A), (b) and (c) of FIG. 1 are block diagrams of a conventional transition area detection apparatus.

2 is a block diagram of a transition region detection apparatus of the present invention.

3 is a detailed circuit diagram of the transition region detection apparatus of the present invention.

4A to 4F are waveform diagrams of operation signals of the present invention.

5 is a data structure diagram of a ROM table in the apparatus of the present invention.

* Explanation of symbols for the main parts of the drawings

17: transition region component detecting means 18: transition region width detecting means

19: transition region discrimination means 20: ROM

21: output control unit

The present invention relates to a method and apparatus for detecting a transition region of a video signal in a video signal processing device (TV, VCR, etc.), and determining whether or not a transition region component is determined from a difference value between an input pixel and a neighboring pixel. Is recognized as the final transition region by comparing with the transition region width selected by the user, so that the influence of noise is excluded and the transition region according to the image bandwidth can be accurately detected.

Conventionally, an apparatus for detecting transition regions (rising edges and falling edges) in a video signal detects a transition region from a difference signal between an input video signal and a video signal delayed by one sample, as shown in FIG. B) It is divided into a case of detecting a transition region through an operation using an adder as shown in FIG. 2 and a case of detecting a transition region from a video signal delayed by two samples as shown in (c).

In the case of (A), the input video signal VIDEO IN is delayed in one sample memory 1, and the delayed video signal and the input video signal are subtracted by the subtractor 2 to obtain the difference signal, and the difference signal is absolute value. When the absolute value of the difference signal is greater than the reference level TH, the detection signal is converted to the output terminal OUT when the absolute value of the difference signal is larger than the reference level TH. Will print.

In the case of (b), the signal delayed by one sample memory (5) and the signal amplified by the half amplifier (6), the two samples delayed by one sample memory (5) and (7) and the half amplifier (8) The amplified signal is subjected to arithmetic processing of X 。- (X1 + X-1) / 2 in the adder 9, and the result is converted into an absolute value in the absolute value calculator 10 by the reference level TH and the comparator 11 If the absolute value is larger than the reference level TH, the difference is determined as the transition region component.

In the case of (C), the subtractor 14 subtracts the signal and the input video signal delayed by two samples into one sample memory 12 and 13 to obtain the difference signal, and the difference signal is obtained by the absolute value calculator 15. When the absolute value of the difference signal is larger than the reference level (TH) by comparing with the reference level (TH) and the comparator 16 is determined as a transition region component.

Therefore, the conventional transition region detection device detects the transition region by comparing the absolute value of the signal delayed by one or two sample periods and the difference with a fixed reference level, so that malfunctions that easily detect noise as the transition region are easily generated. There is a problem in that it is impossible to reliably detect the transition region because it cannot cope with the change of the width of the transition region according to the bandwidth.

Since the bandwidth of the video signal and the width of the transition area are inversely related, the width of the transition area varies for each video signal when processing video signals with different bandwidths such as NTSC, PAL, VCR, and S-VHS. As a result, the video signal with a large bandwidth becomes narrower in the transition region, and the video signal that is constantly increasing or decreasing is recognized as a transition region. On the contrary, the video signal with a narrow bandwidth becomes wider in the transition region. It will not be recognized as a transition area.

Since it is difficult to rule out such a malfunction, it is difficult to reliably trust the overall signal processing relationship by performing image enhancement processing according to the detected transition region.

The present invention determines whether a transition region component is determined from a result of comparing an input image signal (pixel) with a difference value between neighboring pixels, and detects the width of the transition region from the determination result. By detecting the transition region from whether it is included or not, it detects the transition region accurately without the influence of noise and detects the transition region according to the change of the video bandwidth by setting the detection width arbitrarily variable according to the bandwidth of the video signal. It is an object of the present invention to provide a method and a device for detecting a transition region of an image signal, which are reliable in operation. Hereinafter, the configuration and effect of the present invention and its apparatus will be described with reference to the accompanying drawings. .

First, the transition region detection method of the present invention comprises a process of determining a transition region component for determining whether a transition region component is compared by comparing an input image signal component with a neighboring pixel, and if the transition region component is a transition region component, A transition region width determining process of counting and comparing a count value with a transition region reference width set by a user, and determining whether the transition region corresponds to a transition region reference width, and if the transition result corresponds to the transition region reference width, If the result is determined to be maintained, and does not correspond to the transition region reference width, the detection output control process converts the result determined by the transition region component into a non-transition region signal and outputs the result.

On the other hand, in the transition region detection apparatus of the present invention, the transition region detection method of the present invention is performed, referring to Figure 2, the transition region for detecting the presence or absence of the transition region component from the comparison result of the input video signal and the neighboring pixel The component detecting means 17, the transition region width detecting means 18 for counting the detected transition region components to detect the width of the transition region, and the reference width NTHl (NTH2) in which the user sets the detected transition region width. Transition region discrimination means 19 for discriminating whether the bandwidth of the detected transition region component corresponds to the transition region reference width, and the output control data of the transition region detection signal by receiving the transition region discrimination result as an address. ROM 20 for supplying, and an output control unit 21 for selectively outputting the detected transition region component in accordance with the ROM output control data.

Reference numeral CLOCK is a system clock, 22 and 23 are delay matching units for compensating for a delay time required for signal processing, and 24 is an n sample memory for compensating for a time required for detecting a transition region of an input video signal.

The transition region detection operation according to this is as follows.

The input image signal is delayed by one sample and two samples by the transition region component detecting means 17 to calculate a difference signal with neighboring pixels, and compares the absolute values with each other to determine whether there is a transition region component in the currently input image signal. Detect.

The detection result is inputted to the transition region width detecting means 18, and the delay matching section 22 is inputted to the output control section 21 after a predetermined time delay processing.

The transition region width detecting means 18 counts the input transition region component detection signal.

The count result is input to the transition region discrimination means 19 as the detection width of the input transition region component, and the transition region discrimination means 19 sets the reference width NTHl (NTH2), which is determined by the user. Compared to NTH <NTH2.

If the comparison result is NTH ≤ detection width ≤ NTH2, it is determined that the detected transition region component is a signal corresponding to the transition region. Otherwise, if NTH1> detection width or detection width> NTH2, it is determined that it is not a transition region. This determination result is supplied to the address ADDR of the ROM 20.

The ROM 20 is configured with output control data for outputting the output of the transition region component detecting means l7 as a detection signal or converting it to a non-transition region signal in response to the transition region discrimination result.

Therefore, in response to the address ADDR designation, output control data is output from the output terminal D0 earth Dn of the ROM 20. According to the output control data, the output control unit 21 outputs a transition region component detection signal (delay matching unit ( 22) outputs to the output terminal OUT (if it is determined as a transition region) or converts the transition region component detection signal into a non-transition region signal component and outputs it to the output terminal OUT.

For example, the reference width NTHl (NTH2) is set to 3 to 7 clocks (NTH1 = 3CLOCK, NTH2 = 7CLOCK), and the ROM 20 has a 32-bit data (D0 to D31) memory structure. As an example, the above-described transition region detection operation of the present invention will be described.

First, referring to FIG. 3, an exemplary circuit configuration in this case is shown. The transition region component detecting means 17 includes one sample memory 1701 and 1702 for delaying one sample and two samples of an input video signal. Adders 1703, 1704 and 1705 for calculating the difference signal between neighboring one-sample and two-sample delay signals, and absolute value calculators 1706, 1707, and 1708 for calculating the absolute value of each addition result. And an comparator 1709 (1710) for comparing the absolute value calculation results with each other, and an AND gate (1711) for outputting the comparison result as a transition region component detection signal, wherein the transition region width detecting means (8) is a transition region component. An AND gate 1801 that supplies a clock CLOCK to the counter 1802 at the time of detection, a counter 1802 that counts the AND gate output as the transition region detection width, and an output 1-bit memory 1803 that stores the count result ( 1804 (1805) 1806 (1807), and the transition region component detection signal is inverted to memory clock And an inverter 1809 and an end gate 1810 for supplying a counter carry output as a counter initialization signal, and the transition region determining means 19 uses the transition region width detection signal as a reference width. (NTHl) (NTH2), comparators (190l) (1902), the transition gate width and output result of the comparison result as the transition region width determination result, and the transition region by the transition region determination result AND gates 1905, 1906, 1907, 1908, and 1909, which logically combine the area width detection signals to be output to the ROM address, and delay the predetermined area width detection signal by a predetermined time to generate the AND gates 1905 to 1909. And a delay matching unit 1910 inputted to the delay matching unit 1910, and the output control unit 21 performs an AND of the transition region component detection signal in turn from the output least significant bit data of the ROM 20 to output the transition region detection signal. Gates 2101 to 2132 and 1 ratio It is comprised of a memory (2133 Land 2164).

Accordingly, the transition region detection operation is as follows.

The input video signal is memorized in one sample memory 1701 and 1702 by a clock clock as shown in FIG. 4A, and is delayed by one sample and two samples, respectively, and in the adder 1703, The difference signal between the one-sampled delayed video signal is added by the adder 1704 and the difference signal between the one-sampled delayed video signal and the two-sampled delayed video signal by the adder 1704. Each difference signal is outputted by the absolute value calculators 1706, 1707 and 1708.

The absolute values of the output difference signals are compared by the comparators 1709 and 1710. In the case of the transition region, the absolute value of the two sample difference is greater than the absolute value of the one sample difference.

That is, in the transition region, the comparison result of the comparators 1709 and 1710 becomes high so that the output of the AND gate 1711 becomes high, otherwise it becomes low.

4B shows the detection result of such a transition region component.

This signal (output of the end gate 1711) is inverted to the inverter 1808 as shown in FIG. 4C and supplied to the memory clock of the 1-bit memories 1803 to 1807.

In addition, the output of the AND gate 1711 is input to the AND gate 1801 and logically multiplied by the system clock CLOCK and supplied to the clock of the counter 1802.

Accordingly, the counter 1802 performs a count during a period in which the transition region component detection signal (output of the gate 1711; see (b) of FIG. 4) is high, and the count results Q0 to Q4 are 1-bit memories 1803 to 1800. 1807 is stored at the rising edge of the inverter 1808 output (see (c) in FIG. 4).

That is, it is stored at the falling edge of the transition region component detection signal (see (b) in FIG. 4).

On the other hand, when the transition region detection signal is low or the carry C is output from the counter 1802 and the signal inverted by the inverter 1809 is input to the AND gate 1810, the output is cleared by the low signal. The counter 1802 is cleared because the signal is inputted as / CLEAR.

The memory output data is inputted to the comparators 1901 and 1902 and compared with the reference width (NTH1 = 3) (NTH2 = 7 clocks) so that the count value is greater than or equal to 3 clocks and less than or equal to 7 clocks. In the same manner, a high signal (output of and gate 1901) is output.

That is, the transition region is determined only when the transition region detection width corresponds to the reference width set by the user.

This high signal is inverted by the inverter 1904 and input to one side of the AND gates 1905 to 1909 as shown in FIG.

The outputs of the AND gates 1905 to 1909 become low (ADDR = 00000) during the period when this signal is low, and the transition region detection width (count value; memory 1803), which is the output of the delay matching unit 1910, during the high period. 1807) is supplied to the address 20 of the ROM 20.

In accordance with the address ADDR supplied in this manner, the ROM 20 outputs a series of output control data as shown in FIG. 5 from its output terminals D0 to D31.

That is, the least significant bit (D0) data of the output of the ROM 20 is logically multiplied by the transition region component detection signal passing through the delay matching section 22 and the AND gate 2101, and is input to the one-bit memory 2133. The output of the 1-bit memory 2133 is input to the 1-bit memory 2134 by logically multiplying with the next least significant bit (Dl) data, and this signal combination process is performed up to the most significant bit (D31). The transition region detection signal is output as shown in FIG.

That is, since the reference width set by the user is limited from 3 clocks (00011) to 7 clocks (001111) as shown in (a) of FIG. 4, the transition region component detection signal of the T1 and T4 sections where this section is detected is a transition region. It is output as a detection signal, and the remaining T2, T3, and T5 sections are less than 3 clocks or more than 7 clocks, so they are converted into non-transition region signals (ALL ZERO data output).

As described above, according to the present invention, when the transition region component is detected, the transition region component is recognized by comparing the difference values between the input pixel and the neighboring pixel values before and after, thereby reducing the influence of noise and the reference. It is possible to obtain a constant transition region component detection result regardless of the level change and the brightness change of the image.

In addition, the detection range for the transition region width can be arbitrarily determined by easily responding to the change of the bandwidth of the image, so that it can easily cope with input signals of various bandwidths (NTSC, PAL, VCR, S-VHS, etc.) It is effective to prevent the occurrence of errors and to improve image quality.

Claims (6)

A transition region component discrimination process for determining whether a transition region component is compared with an absolute value of an input image signal component with a neighboring pixel; The transition region width determining process of counting the transition region component and comparing the count value with the transition region reference width set by the user to determine whether the transition region component corresponds to the transition region reference width. Detection output control that maintains the result determined by the transition region component when the transition region is the reference width, and converts the result determined by the transition region component into the non-transition region signal when the transition region component does not correspond to the transition region reference width. Transition region detection method of a video signal consisting of a process. Transition region component detecting means 17 for detecting the presence or absence of a transition region component from a comparison result of an input video signal with a neighboring pixel, and transition region width detecting means for detecting the width of the transition region by counting the detected transition region components ( 18) a transition region discrimination means 19 for comparing whether the bandwidth of the detected transition region component corresponds to the transition region reference width by comparing the detected transition region width with the reference width NTHl (NTH2) set by the user. And a ROM (20) for receiving the transition region determination section as an address and supplying output control data of the transition region detection signal, and an output control unit (21) for selectively outputting the detected transition region components according to the ROM output control data. An apparatus for detecting a transition region of an image signal. 3. The transition region component detecting means (17) according to claim 2, characterized in that the transition region component detecting means (17) is adapted to provide a difference signal between one sample memory (1701) and 1702 for one sample and two sample delays of an input video signal and a neighboring one sample two sample delay signal. The adders 1703 (l704) 1705 to be calculated, the absolute value calculators 1706 (1707) 1708 for calculating the absolute value of each addition result, and the absolute value calculation results are compared with each other and the comparator 1709 ( 1710 and an AND gate 1711 for outputting a comparison result as a transition region component detection signal. 3. The transition region width detecting means (18) according to claim 2, wherein the transition region width detecting means (18) supplies an AND gate (1801) for supplying a clock (CLOCK) to the counter (1802) when detecting the transition region component, and counting the AND gate output as the transition region detection width. An output 1-bit memory 1803 (1804), 1805, 1806, and 1807 that store the count result. And an inverter (1808) for inverting the transition region component detection signal and supplying it to a memory clock, and an inverter (1809) and an end gate (1810) for supplying a counter carry output as a counter initialization signal. 3. The transition region discriminating means (19) according to claim 2, wherein the transition region discriminating means (19) compares the transition region width detection signal with a reference width (NTHl) (NTH2), and compares the result of the transition region with the transition region width discrimination result. An AND gate 1905, 1906, 1907, 1908 that logically combines the transition region width detection signal based on the transition region width determination result with the AND gate 1903 and the inverter 1904 to output the result. And a delay matching unit (1910) for delaying the transition region width detection signal by a predetermined time and inputting it to the AND gates (1905 to 1909). The AND gate (2101 site 2132) according to claim 2, wherein the output control means (21) performs an AND multiplication of the transition region component detection signal from the output least significant bit data of the ROM 20 in order to output the transition region detection signal. An apparatus for detecting a transition region of a video signal composed of bit memories (2133 to 2164).