JPS60142563A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a lower breakdown voltage and improved surge-withstanding capability by a method wherein a p-n junction with a low breakdown voltage is parallelly connected to a p-n junction with a high breakdown voltage positioned between an epitaxially grown layer and isolating region. CONSTITUTION:A buried region 10 of high n type density is positioned, partially in contact with an isolating region 3, along the interface between a base layer 2, which is an epitaxially grown region of low n type densty positioned below a base take-out region 5 of high n type density, and a substrate 1 of high p type density. With the region 10 being of high density, the p-n junction between the region 10 and the isolating region 3 has a lower breakdown voltage, which results in the lowering of the breakdown voltage across the base layer 2 and isolating region 3 and in an augmented surge withstanding capability.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bipolar semiconductor device having a lower breakdown voltage to increase surge resistance.

In bipolar integrated circuits (hereinafter referred to as ICs),
The breakdown voltage between the epitaxial growth 1M and the isolation region is high (breakdown voltage that is easy to break down is 100 to 150V)
Many of them are expensive. ), so if a surge is applied to this part, it will be easily destroyed. However, in terms of design, the resistance of the epitaxial growth layer is selected to achieve this breakdown voltage, so improvement is difficult.

For example, a lateral/vertical pnp transistor with a common collector uses an epitaxial growth layer in the base region of the lateral transistor, and the collector is at the same potential as the isolation region, so a surge voltage can damage the base.・Between the collectors (i.e., the interface between the evitagital layer and the isolation region)
The pn junction portion of the device often burns out.

Now, let's consider the surge resistance of the diode (pn junction) in the IC. Figure 1 Tal shows the test circuit. A capacitor C (200PI?) is charged to the voltage ■ by a power source of voltage ■, and then the switch SW is switched to the dotted line side, and the voltage of this capacitor C is V. When is applied to the test diode D, an equal j-curve circuit shown in FIG. 1 (bl) is formed, and a current I flows.

VR is the breakdown voltage of the diode, and r is the internal resistance. The power W applied to the diode D is (since W=I-VR), w= ((1/r) (V-VR) (1-e-fraud)) VR...ill, but in a simple way Therefore, by approximating the current waveform as a delta function, W-(1/r) (V VR) VR・A-(21
Try it as follows.

Assuming that the power W is the energy that destroys a diode of a certain shape due to a surge, let's fix this power W and examine the relationship between the voltage ■ and VR.

From formula (2), ('/VR) VR= r-W/ A=-=B...
・(3) Assuming that B has the apparent power above, V=V, +B/
V, ...(4). Therefore, if we represent this equation (4) graphically, we can obtain the second
As shown in the figure. Then, both sides of equation (4) are vR
Differentiating with dV/clvR-1-B/VR" ・+53. Therefore, when V, = flex...(6), the voltage ■ becomes the minimum value. Then, by converting this equation (6), By substituting into equation (4), the voltage ■ at this minimum value can be found.This voltage ■ is ■-2A...(7), and V=2VR...(8). be.

That is, if the capacitance of the capacitor C, the internal resistance r, and the power W applied to the diode D are constant, that is, if the apparent power B is constant, the voltage V (surge withstand voltage) is equal to the breakdown voltage ■R. When it is twice, it is the minimum,
The breakdown voltage at this time is R=A. This breakdown voltage ■,
Even if R is smaller or larger than 4, the surge withstand voltage increases.

This means that as the breakdown voltage Va'l)' increases, the current flowing through the diode decreases, while its breakdown voltage V.

This can be interpreted as the fact that as the voltage becomes smaller, the voltage applied to the diode becomes smaller, so the power consumed by the diode becomes smaller (Figure 3).

As is clear from the above, if the shape is constant, reducing the breakdown voltage vR of the pn junction to the extent possible increases the surge resistance.

The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device with a reduced breakdown voltage in accordance with the above theory and thereby improved surge resistance.

Examples of the present invention will be described below. FIG. 4 shows the structure of a common collector type lateral transistor showing one embodiment thereof. l is a p-type low-concentration substrate, 2 is a base region made of an n-type low-concentration epitaxial growth layer formed on the upper surface of the substrate 1, 3 is a p-type high-concentration isolation region; Since it is an area, it works as a collector area.

They are a 4B p-type high concentration emitter region and a 5B n-type high concentration base extraction region. Further, 6 is an insulating protective coating, 7 is an emitter electrode, 8 is a base electrode, and 9 is a ground electrode for setting the isolation region to a ground potential.

The above is the structure of a normal collector-grounded lateral transistor, and as mentioned above, in this structure, the breakdown voltage of the pn junction between the base region 2 and the isolation region 3 is high, so it is resistant to surges. The problem was that it was weak.

In this embodiment, in addition to the above structure, an n-type high concentration buried region IO is formed at the interface between the base region 2 and the substrate 1 below the base extraction region 5, and the buried region 10 is arranged so that a part thereof is in contact with the isolation region 3, thereby forming a pn junction.

Therefore, according to this structure, since the buried region 1O is highly doped, the breakdown voltage of the pn junction there between it and the isolation region 3, which is also highly doped, becomes low.

The buried region 10 is formed by diffusion or ion implantation of n-type impurities at a high concentration from the upper surface of the substrate 1. Epitaxial growth layer 2 is then formed by epitaxial growth. Other regions are formed by impurity expansion +l& or ion implantation in the same manner as in the prior art.

FIG. 5 shows another embodiment, in which a similarly high-concentration p-type buried region 3a is in contact with the lower part of the isolation region 3.
, and make it part of Aitsuregion area 3,
A buried region 10 is formed so as to be in contact with this buried region 3a.

In this example as well, a high concentration pn junction is formed as in the above embodiment, and the breakdown voltage at that portion is low.

As described above, the pn junction with a low breakdown voltage is connected in parallel to the pn junction with a high breakdown voltage between the epitaxial growth layer 2 and the isolation region 3, so that the pn junction with a low breakdown voltage is connected between the epitaxial growth layer 2 and the isolation region 3. It becomes possible to lower the breakdown voltage with respect to the ration region 3, thereby increasing the surge resistance of that portion.

As described above, according to the present invention, the surge resistance is increased and the IC is equipped with a pnp lateral transistor with a common collector.
suitable for

[Brief explanation of the drawing]

Figure 1 +al is a diode surge withstand test circuit diagram,
(b) is an equivalent circuit diagram when voltage is applied, Figure 2 is a characteristic diagram showing the relationship between breakdown voltage and surge withstand voltage, Figure 3 is a characteristic diagram showing the relationship between breakdown voltage and power, and Figure 4 is a characteristic diagram showing the relationship between breakdown voltage and surge voltage. FIG. 5 is a sectional view of a semiconductor device according to another embodiment. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Base ff4 region (epitaxial growth layer), 3... Isolation region (collector region), 3a... Buried region, 4... Emitter region, 5... Base extraction area, 6... Insulating protective coating, 7... Emitter electrode, 8... Base electrode, 9
...Ground electrode, 10...Embedded region. Patent Applicant: New Japan Radio Co., Ltd. Agent: Patent Attorney: Toakiaki Nagao Figure 1 (a) (b) Figure 4 Figure 5

Claims (1)

[Claims] (1) A low concentration epitaxial growth layer of a second conductivity type opposite to the second conductivity type is formed on the top surface of the first conductivity type low concentration substrate, and the epitaxial growth layer is directed in one direction from the top surface of the epitaxial growth layer. In a semiconductor device, a highly doped extraction region of a second conductivity type is formed in the semiconductor device, and a highly doped isolation region of a first conductivity type is formed from the upper surface of the epitaxial growth layer to the substratum. forming a second conductivity type high concentration buried region in contact with the isolation region at a lower interface between the epitaxial growth layer and the substrate;
A semiconductor device characterized in that the buried region and the isolation region form a pn junction having a low breakdown voltage.