JPS60140881A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60140881A
JPS60140881A JP58246950A JP24695083A JPS60140881A JP S60140881 A JPS60140881 A JP S60140881A JP 58246950 A JP58246950 A JP 58246950A JP 24695083 A JP24695083 A JP 24695083A JP S60140881 A JPS60140881 A JP S60140881A
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
manufacturing
paste
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58246950A
Other languages
Japanese (ja)
Other versions
JPH0518268B2 (en
Inventor
Haruhiko Matsuyama
松山 治彦
Mitsuo Nakatani
中谷 光雄
Masaaki Okunaka
正昭 奥中
Ataru Yokono
中 横野
Tadashi Saito
忠 斉藤
Kunihiro Matsukuma
邦浩 松熊
Satoru Suzuki
悟 鈴木
Sumiyuki Midorikawa
緑川 澄之
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58246950A priority Critical patent/JPS60140881A/en
Publication of JPS60140881A publication Critical patent/JPS60140881A/en
Publication of JPH0518268B2 publication Critical patent/JPH0518268B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/547Monocrystalline silicon PV cells

Abstract

PURPOSE:To enable the formation of a metal film by plating at the same time with a uniform p<+> layer by a method wherein a paste substance mainly made of Al powder, a kind or more of metals of Sn, In, and Sb, and a metal forming a high melting point alloy with Al is printed on a substrate and calcined. CONSTITUTION:Al paste compounded with at least a kind of metal selected out of Sn, In, and Sb is printed on the substrate 1 of silicon or the like and calcined, when a uniform p<+> layer 3 is formed, and the metal film by plating can be formed on the Al layer formed at the same time. The addition of the metal forming a high melting point alloy with Al into this Al paste eliminates the cohesion liable to generate in the Al layer during calcination or the generation of cracks. Particularly Co, Cr, Mn, Mo, Ti, Zr, B, or W is effective as the metal forming a high melting point alloy with Al that is very effective to form a smooth Al layer and a uniform p<+> layer 3.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、半導体装置の製造方法に係り、特に太陽電池
のBSF’(Back 5urface F’1eld
)および電極の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
) and a method for manufacturing an electrode.

〔発明の背景〕[Background of the invention]

半導体素子の例と(〜で、太陽電池の代光的な構成例を
図に示す。n十/p/p+接合を形成した81基叛の受
光面、および裏面にそnぞれ受光面電極4、裏面電極5
′(r−形成した構造である。さらに一般には反射防止
膜等も設けら扛ている。
An example of a semiconductor element and an example of an alternative photovoltaic configuration of a solar cell are shown in the figure.A light-receiving surface electrode is provided on the light-receiving surface of the 81-substrate having an n+/p/p+ junction formed thereon, and a light-receiving surface electrode on the back surface. 4. Back electrode 5
'(r-formed structure. Furthermore, an anti-reflection film or the like is generally not provided.

この太陽電池の近4:ICおける重要課題は、製造コス
トの低減にあり、受光面電極4、裏面電極5の形成法も
、従来の真空蒸着法にかわって低コストなめっき法や印
刷法が検討さnるようになってきた。特に印刷法は、自
動化が容易で生産性が高いことから広く検討さnている
An important issue in this solar cell IC is to reduce manufacturing costs, and the method for forming the light-receiving surface electrode 4 and back surface electrode 5 is also low-cost plating or printing methods instead of the conventional vacuum deposition method. I'm starting to think about it. In particular, printing methods are being widely studied because they are easy to automate and have high productivity.

P”l@3形成にもこの印刷法が広く用いらnておシ、
Aβ粉禾と有・機結合剤、有機溶剤を混練したペースト
状の物質(以下AfiInペーストう)をスクリーン印
刷法などで塗布し、焼成する方法である。このためのへ
2ペーストは、太陽電池のP+層形成用として多くのも
のが市販さ牡ている。
This printing method is also widely used to form P"l@3.
In this method, a paste-like substance (hereinafter referred to as AfiIn paste) made by kneading Aβ powder, an organic binder, and an organic solvent is applied by screen printing or the like, and then baked. Many H2 pastes for this purpose are commercially available for forming the P+ layer of solar cells.

しかし市販のInペーストを月]いP+層3、および裏
面電極4の形成を行うと次の問題があった。
However, when the P+ layer 3 and the back electrode 4 were formed using a commercially available In paste, the following problem occurred.

即ち、大気中(酸化雰囲気中)で焼成すると鶴層が酸化
さ′n、絶縁物(Afi20x)となるため、後工程て
こ扛を除去し、再びAgペースト等を用いて裏面を極4
全形成しなけ扛ばならず、工程が複雑化し太陽電池のコ
ストアップを招く欠点があった。これを防止するには、
へ2ペーストの焼成を不活性雰囲気(N2.Ar+He
等)中で行うことが有効であるが、市販前2ペーストで
は、焼成後のへ1層に凝集やクラックが生じ、均一なP
+施が形成できず、こ扛が原因して太陽電池の効率低下
が起きる欠点もあった。
That is, when fired in the air (in an oxidizing atmosphere), the crane layer is oxidized and becomes an insulator (Afi20x), so the lever in the post-process is removed and the back side is made into a polar 4 using Ag paste or the like again.
This has the drawback that the process is complicated and the cost of the solar cell increases because it has to be completely formed. To prevent this,
The paste was fired in an inert atmosphere (N2.Ar+He
However, in the case of pre-market 2 pastes, agglomerations and cracks occur in the first layer after firing, resulting in a uniform P paste.
There was also the drawback that the solar cells could not be formed and the efficiency of the solar cell would decrease due to the formation of the pores.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した欠点をなくシ、安価で高効軍
な太陽電池などの半導体装置の製造方法を提供すること
にある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an inexpensive and highly effective method for manufacturing semiconductor devices such as solar cells.

〔発明の概要〕[Summary of the invention]

本発明の半導体装置製造方法は、P形シリコン基板の一
方の主面に同−導電形不純物層、および電&を形成する
において、A2粉禾とzsn+In+sbから選ばnる
少なくとも一種の金槁と、A13 ・ と高融点合金を形成する金属とを主成分とするペースト
状物質を塗布した、焼成することを特徴とする。
In the method for manufacturing a semiconductor device of the present invention, in forming an impurity layer of the same conductivity type and a dielectric layer on one main surface of a P-type silicon substrate, at least one type of metal selected from A2 powder and zsn+In+sb, It is characterized by applying a paste-like substance whose main components are A13 . and a metal forming a high melting point alloy, and then firing.

本発明が従来の方法と異なる点は、上記組成のペースト
状物質(以下ではへ2ペーストと略す)を同一導電不純
物層および電極を形成するために用いることである。こ
扛は、このAβペーストをシリコンなどの基板上に印刷
し、焼成すると、均一なP+層が形成できること、更に
は同時に形成さnるAR,ペースト焼成層(以下ではA
lt層と略す)に、従来の市販品では不可能であっため
つきによる金属皮膜が形成できることを見い出したこと
による。 ′ 即ち、このへ1層上に牛田濡れ性のよ(ハ金属(例えば
C’n rNj、 +Pl) +Sn等)めっきをする
ことによって、従来必要であったAfi層のエツチング
、Agペーストの印刷、焼成による半田付用の電極形成
工程が全く不要となる。
The present invention differs from conventional methods in that a paste-like material having the above composition (hereinafter abbreviated as He2 paste) is used to form the same conductive impurity layer and electrode. This technique is based on the fact that when this Aβ paste is printed on a substrate such as silicon and fired, a uniform P+ layer can be formed, and furthermore, an AR and paste fired layer (hereinafter referred to as A) can be formed at the same time.
This is due to the discovery that a metal film can be formed by plating on the lt layer), which was impossible with conventional commercially available products. That is, by plating one layer on this layer with Ushida wettability (metal (e.g., C'n rNj, +Pl) +Sn, etc.), etching of the Afi layer, printing of Ag paste, which was previously necessary, The process of forming electrodes for soldering by firing is completely unnecessary.

本発明に用いるAI!、ペーストの成分について。AI used in the present invention! , about the ingredients of the paste.

以下に更に詳述する。主成分であるAlt粉末は、平均
粒径で10μmJ′、L下であることが好ましい。
Further details are provided below. It is preferable that the Alt powder, which is the main component, has an average particle size of less than 10 μm J′,L.

10μmより大きいものを用いてスクリーン印刷した場
合、メヅシ:、σン目づまりが起き易く、連続印刷性に
問題がある。
When screen printing is performed using a material larger than 10 μm, clogging tends to occur and there is a problem in continuous printing.

捷た。AIt粉禾粉状形状鱗片状が最も好ましい。I cut it. The powder-like shape of AIt powder is most preferably scaly.

が1片状AiV、粉末を用いると、均一なAIt層が形
成できる。
When a single-piece AiV powder is used, a uniform AIt layer can be formed.

こσ)AIt粉禾は、酸化防止のためにステアリン酸、
゛またはステアリン酸アルミニウム、またはステアリン
1拶亜鉛でコーティングさ扛ていることが好ましい。
σ) AIt powder contains stearic acid and
Preferably, the material is coated with aluminum stearate or zinc stearate.

このペースト中にSn+IrzSbから選ばn友少なく
とも一種の金朗全添加すると、AIt層をそのまま電極
とする際に非常に有効である。こnらの金属を配合し7
tAgペースト全シリコンなどの基板上に印刷し、焼成
すると、均一なP+層が形成さ扛るとともに、同時に形
成さ庇るA2層」二に、従来不勇卵であっためつきによ
り金属皮膜が形成できる。
Adding at least one type of metal selected from Sn+IrzSb to this paste is very effective when using the AIt layer as it is as an electrode. Blending these metals 7
When the tAg paste is printed on a substrate such as all-silicon and fired, a uniform P+ layer is formed.At the same time, a covering A2 layer is formed.Secondly, a metal film is formed by plating, which was conventionally difficult to achieve. can.

こ扛により、裏面電極5の電気抵抗が低減できるととも
に、めっき金属皮膜として半田濡註性の良い金FA(例
えばCu +Ni +Pb +Sn等)を用いた場合に
は、半田付も角層となる。
By this process, the electrical resistance of the back electrode 5 can be reduced, and when gold FA with good solder wettability (for example, Cu + Ni + Pb + Sn, etc.) is used as the plating metal film, the soldering becomes a corner layer.

このSn+In+Sbから選ば71.た少なくとも1種
の金属の配合割合は、Ait粉禾100vojlt に
対して(10〜150vofi%)/ A 1、好まし
くは(25〜100voR%)/A!であることが必要
である。10Won%/k11.11..!11少ない
と、先に述べたSn+In+Sbの添加効果はほとんど
得らnない。また1 50voβ%/A、9より多くな
ると、形成さnたA1層の電気抵抗が高くなり、セルの
効率低下を招く。
Selected from Sn+In+Sb 71. The blending ratio of at least one metal is (10 to 150 vofi%)/A1, preferably (25 to 100 voR%)/A! with respect to 100 vojlt of Ait powder. It is necessary that 10Won%/k11.11. .. ! If the amount is less than 11, the above-mentioned effect of adding Sn+In+Sb will hardly be obtained. On the other hand, if it exceeds 150 voβ%/A,9, the electrical resistance of the formed A1 layer increases, leading to a decrease in cell efficiency.

また、このAlペースト中に、Alと高融点合金を形成
する金属を添加することは、焼成時のAu層に発生し易
い凝集やクラヴクの発生をなくし、平滑なAIt層、お
よび均一なP導層を形成するのに非常に有効である。
In addition, adding a metal that forms a high melting point alloy with Al to this Al paste eliminates agglomeration and cracking that easily occur in the Au layer during firing, and creates a smooth AIt layer and uniform P conductivity. Very effective for forming layers.

A1と高融点合金を形成する金属としては、特にGo+
Cr+Mn+MO+Ti+Zr+El+Wが有効である
In particular, Go+ is a metal that forms a high melting point alloy with A1.
Cr+Mn+MO+Ti+Zr+El+W is effective.

配合割合は、AIt粉禾100yonに対して(5〜5
ovon%)AItであることが必要である。配合割合
が5v02%/d、、l−9少ないと、先に述べたA2
と高融点合金を形成する金属の添加効果はほとんど得ら
扛ない。また30vofi%/AIJ、f)多くなると
なると、形成さ几たA2層の電気抵抗が高くなり1セル
の他車低下を招く。
The blending ratio is (5 to 5
ovon%) AIt. If the blending ratio is 5v02%/d, l-9 less, the A2 mentioned earlier
There is almost no effect of adding metals that form high melting point alloys. Furthermore, if the value increases by 30 vofi%/AIJ, f), the electrical resistance of the formed A2 layer increases, resulting in a decrease in one cell compared to other vehicles.

次に他の構成成分である有機結合剤と有機溶剤について
述べる。こfらは、従来の厚膜スクリーン印刷用ペース
トで用いらnているものと同様のものをJもいることが
できる。有機結合剤はセルロース系化合物や、ポリメタ
クリレート系化合物などが、有機溶剤としては多価アル
コール系のものが特に好適である。
Next, the other constituent components, the organic binder and organic solvent, will be described. These may be similar to those used in conventional thick film screen printing pastes. The organic binder is preferably a cellulose compound or a polymethacrylate compound, and the organic solvent is particularly preferably a polyhydric alcohol.

次にAlペーストの焼成粂件について述べる。Next, the process of firing the Al paste will be described.

焼成温度は660〜900℃、好ましくは700〜80
0℃が艮い。660℃より低い温度ではAuが溶融しな
いため、均一なP導層およびA2層が形成さnにぐい。
Firing temperature is 660-900℃, preferably 700-80℃
0℃ is strange. Since Au does not melt at temperatures lower than 660° C., a uniform P conductive layer and A2 layer are formed.

まfC900℃より高温では、受光面側に形成さnてい
るn十接合層の接合深さがかわり、セル効率が低下する
At temperatures higher than fC900° C., the junction depth of the n-junction layer formed on the light-receiving surface side changes, resulting in a decrease in cell efficiency.

焼成時間は2〜60分、好ましくは3〜30分が良い。The firing time is preferably 2 to 60 minutes, preferably 3 to 30 minutes.

2分より短いと、へ1層やP導層の形成が不完全となり
、高効率のセルが得ら牡ない。また、60分より長く焼
成すると、900℃よシ高温で焼成した場合と同@Q−
1坪由でセル効率低下が生じる。
If it is shorter than 2 minutes, the formation of the He1 layer and the P conductive layer will be incomplete, making it impossible to obtain a highly efficient cell. Also, if you bake for longer than 60 minutes, it will be the same as firing at a higher temperature than 900℃.
Cell efficiency decreases after 1 tsubo.

溶成雰囲気は酸素濃度500ppm以下、好甘しくは5
0ppm以下の不活性ガス雰囲気が良い。300PPn
n より高濃度になると、A2層の酸化が進み電気抵抗
が高くなるため、セルの動車低下が生じる。
The melting atmosphere has an oxygen concentration of 500 ppm or less, preferably 5
An inert gas atmosphere of 0 ppm or less is preferable. 300PPn
When the concentration is higher than n, the oxidation of the A2 layer progresses and the electrical resistance increases, resulting in a decrease in cell mobility.

不活性ガスにN2+ArTHeなどがあるが、工業的に
得やすく安価なN2が好ましい。
Inert gases include N2+ArTHe, but N2 is preferred because it is industrially easily obtainable and inexpensive.

以下、本発明を実施例によって説明する。Hereinafter, the present invention will be explained by examples.

実施例1゜ 太陽電池用の接合形成シリコン基板として、図に示すよ
うにP形シリコン基板1(比抵抗19m。
Example 1 A P-type silicon substrate 1 (specific resistance: 19 m) was used as a junction-forming silicon substrate for solar cells, as shown in the figure.

直径3インチ、丸形ウェハ)の表面に、イオン打込み法
で深さ0.2〜0.4μmQ、’) n+十層(表面シ
ート抵抗50jJ/口)を形成したものを用いた。
A round wafer with a diameter of 3 inches was formed with a layer of 0.2 to 0.4 μm Q,')n+10 layers (surface sheet resistance 50JJ/mouth) by ion implantation on the surface.

八Rペーストには1表向をステアリン酸コーティングし
た平均粒径2μm以下の鱗片状AJと、これに10cp
sのエルセルロース5重量部をα−テルピネオール95
重量部に溶解した粘稠液を加えながら充分に混練し、粘
度全豹15pa−s (ずυ速1f101]sθc−1
)としたもの、およびこのdペーストにSn+In+S
bのうちから選ば扛る少なくとも1種の金属粉(平均粒
径5μm以下)を各種組合せたもの、およびA2と高融
点合金全形成する金属として、A2粉床100vofi
に対してCOを15Volt%/Afl添刀口したもの
を用いた。
The 8R paste contains scaly AJ with an average particle size of 2 μm or less coated with stearic acid on one surface, and 10 cp.
95 parts by weight of α-terpineol and 5 parts by weight of L cellulose of S
Thoroughly knead while adding the viscous liquid dissolved in the weight part to obtain a total viscosity of 15 pa-s (zυ speed 1f101] sθc-1
), and this d paste contains Sn+In+S
Various combinations of at least one kind of metal powder (average particle size of 5 μm or less) selected from b.
15 Volt%/Afl of CO was used.

こりAlペーストを、先に述べたシリコン基板の裏面に
スクリーン印刷し、150℃10分間の乾燥処理をした
後、この基板を窒素ガス雰囲気(酸素濃度2.6ppm
)中で、750℃にて5分間焼成した。この後受光面電
極4を形成した。
The stiff Al paste was screen printed on the back side of the silicon substrate mentioned above, and after drying at 150°C for 10 minutes, the substrate was placed in a nitrogen gas atmosphere (oxygen concentration 2.6 ppm).
) for 5 minutes at 750°C. After this, a light-receiving surface electrode 4 was formed.

この様にして作製した太陽電池の電流−電圧特性から、
開放電圧(Voa)、曲線因子(F−1t’)’に調べ
た。
From the current-voltage characteristics of the solar cell produced in this way,
The open circuit voltage (Voa) and fill factor (F-1t')' were investigated.

また、裏面電極4の外観(Al層の凝集、クラヴクの有
無)評価、および電気ニッケルめっき(液組成:スルフ
ァミン酸ニッケル150g/β、塩化ニッケル10g/
n、ホウ酸4og/A) を用いめっき析出性評価を行
った。
In addition, we evaluated the appearance of the back electrode 4 (agglomeration of the Al layer, presence or absence of Kravuk), and electrolytic nickel plating (liquid composition: nickel sulfamate 150g/β, nickel chloride 10g/β).
Plating precipitation properties were evaluated using boric acid (4 og/A).

第1表のに3〜8.Nα9〜14に示した如く。3-8 in Table 1. As shown in Nα9-14.

本発明の方法によnば、高Vocr高F’P″なセル帯
性が得られ、更にはクラックや凝集のないめっき析出性
の良好なAQ層が得らnた。
According to the method of the present invention, high Vocr, high F'P'' cell band properties were obtained, and furthermore, an AQ layer with good plating precipitation without cracks or agglomerations was obtained.

第1衆のNa1のように、In + Sn +S bの
金属およびAJ2と高融点合金を形成する金属C0全添
加しないものでは、A1層に凝集、クラックが発生し、
めっき析出性も不良であった。また凝集、クラックの九
め均一なP土層が形成さ牡ず%VOOIFF’とも低く
なり、効率が低下した。
When the metal of In + Sn + S b and the metal C0 that forms a high melting point alloy with AJ2 are not added at all, such as Na1 in the first group, agglomeration and cracks occur in the A1 layer,
Plating precipitation properties were also poor. Furthermore, a P soil layer with uniform agglomeration and cracking was formed, and the %VOOIFF' was also low, resulting in a decrease in efficiency.

第1表のNa2のようにI n + S n + S 
bの金塊を添加しないものでは、めっき析出性が不良で
あり、こnに起因するFFの低下が見らn友。
Like Na2 in Table 1, I n + S n + S
In the case of b without adding gold ingots, the plating precipitation was poor, and a decrease in FF due to this was observed.

また、第1表のNl19のようにSn+In+SbO何
nの金属の場合でも、添加量が150vofi%/An
、Jニジ多くなると、Voc+F’Fが低下した。
Also, as in Nl19 in Table 1, no matter how many n metals Sn+In+SbO are used, the amount added is 150vofi%/An
, as Jniji increased, Voc+F'F decreased.

なお第1我のN14〜14のめっき析出性の良好なもの
に半田濡n性試験を行った結果、非常に良好な半田濡n
性を示した。
In addition, as a result of conducting a solder wettability test on the N14 to N14 plating with good plating precipitation properties, it was found that the solder wettability test was very good.
showed his sexuality.

実施例Z 太陽電池用の接合形成シリコン基板として、実施例1と
同様のものを用いた。
Example Z The same substrate as in Example 1 was used as a silicon substrate for forming a junction for a solar cell.

hll、ペーストには平均粒径2μm以下の鱗片状A旦
と、こ牡にポリイソブチルメタクリレート20重量部を
α−テルピネオール80重量部に溶解した粘稠液を加え
ながら充分に混練し、粘度が約15Pa・8(ずp速度
100seo ’)になるよう調整したものに、粒径1
0μm以下のSn粉床75voji%/4fiを加え、
更にhftと高融点合金を形成するメタルを刃口えたも
のを用いた。
The paste was thoroughly kneaded while adding scaly A-tan with an average particle size of 2 μm or less and a viscous liquid prepared by dissolving 20 parts by weight of polyisobutyl methacrylate in 80 parts by weight of α-terpineol, until the viscosity was approximately Particle size 1
Add a Sn powder bed of 0 μm or less 75voji%/4fi,
Furthermore, a blade with a metal forming a high melting point alloy with hft was used.

このA1ペーストを、実施例1と同様に印刷。This A1 paste was printed in the same manner as in Example 1.

乾燥、焼成し、この後受光面電極4を形成した。After drying and baking, a light-receiving surface electrode 4 was formed.

作製した太陽電池の特性、およびA1層の外観。Characteristics of the produced solar cell and appearance of the A1 layer.

めっき析出性?+7笑施例1と同様にして調べた。めっ
き液には電気鋼めっき液(液組成:ビロリン酸鋼90g
zl、ピロリン酸カリ350g/J1.アンモニア3m
わべ)を用いた。
Plating precipitation? +7 lol It was investigated in the same manner as in Example 1. The plating solution is electrical steel plating solution (liquid composition: birophosphate steel 90g
zl, potassium pyrophosphate 350g/J1. Ammonia 3m
Wabe) was used.

第2表のNα17〜20.漱22〜33に示した如く。Nα17-20 in Table 2. As shown in Sou 22-33.

本発明の方法によ扛ば、高VOO+高FFなセル特性が
得らn1更にはクラックや凝集のないめっき析出性の良
好なA1層が得ら扛る。
By using the method of the present invention, cell characteristics of high VOO+high FF can be obtained, and furthermore, an A1 layer with good plating precipitation properties without cracks or agglomerations can be obtained.

第2表のNa15,16のようにAfiと高融点合金を
形成する金属を加えないか、または添加量の少ないもの
では、A2層に凝集、クラックが発生し、更には、Vo
c+FF’も低下した。
If a metal that forms a high melting point alloy with Afi is not added or added in a small amount, such as Na15 and 16 in Table 2, agglomeration and cracks will occur in the A2 layer, and furthermore, Vo
c+FF' also decreased.

第2表のNa21のように添刃口量が30vofi%/
d以上のものでは、Cuめつき膜の析出性が低下し、そ
nにつtてVoo+FF’も低下した。なお第2表中の
めっき析出性良好なものでは、何nも実施例1と同様に
半田濡n性は良好であった。
As shown in Table 2, Na21, the cutting edge amount is 30vofi%/
In the case of d or more, the precipitation property of the Cu plating film decreased, and Voo+FF' also decreased accordingly. In addition, among the samples with good plating precipitation properties in Table 2, similar to Example 1, the solder wettability was good.

実施例& 太陽電池用の接合形成シリコン基板として、実施例1と
同様のものを用いた。へ2ペーストとしては表面をステ
アリン酸亜鉛コーティングした平均粒径2μm以下の鱗
片状A2に% 10cpsのエチルセルロース5重量部
をα−テルピネオール95重量部に溶解した粘稠液を加
えながら充分に混練し、粘f’を約15Pa−s(ずシ
速1i100sec’)としたものに、平均粒径10μ
m以下のsb粉木75VOR%/An1MO粉宋15v
o1%/A1711]えたものをA2ペーストとした。
Examples & The same silicon substrate as in Example 1 was used as a junction-forming silicon substrate for solar cells. The paste was prepared by thoroughly kneading a scaly A2 surface coated with zinc stearate and having an average particle diameter of 2 μm or less while adding a viscous solution prepared by dissolving 5 parts by weight of ethyl cellulose (%10 cps) in 95 parts by weight of α-terpineol. When the viscosity f' was approximately 15 Pa-s (speed 1i100 sec'), the average particle size was 10 μ.
m or less sb powder wood 75VOR%/An1MO powder song 15v
o1%/A1711] was used as A2 paste.

この0ペーストを実施例1と同様に印刷、乾燥した後s
N2雰囲気中でq!r種条件を組み合せて焼成した。
After printing and drying this 0 paste in the same manner as in Example 1,
q in the N2 atmosphere! Firing was performed using a combination of r types of conditions.

この後、受光面電極4を形成した。めっき膜析出性は、
実施例1と同様の電気N1めっき液を用いて評価した。
After this, the light-receiving surface electrode 4 was formed. The plating film deposition property is
Evaluation was performed using the same electrolytic N1 plating solution as in Example 1.

第3表のNa35 、Na37〜40. Na42〜4
5. N1145〜46に示した如く、本発明の方法に
よ扛ば、高V o a + 高F l’なセル特性が得
ら扛、更にはクラヅクや凝集のないめっき析出性の良好
なA2層が得ら扛ることがわかった。
Na35, Na37-40 in Table 3. Na42~4
5. As shown in Nos. 1145 to 46, by using the method of the present invention, cell characteristics of high V o a + high F l' can be obtained, and furthermore, an A2 layer with good plating precipitation without cracks or agglomerations can be obtained. I found out that I can get it.

また、第6表のNa34の様にAnの融点以下の焼成温
度では、A1層が成膜せず、Ni めっき膜析出性が悪
い。またこnに、r、りVoa+FPも低くなっている
In addition, as in Na34 in Table 6, at a firing temperature below the melting point of An, the A1 layer is not formed and the precipitation of the Ni plating film is poor. Furthermore, r and Voa+FP have also become lower.

また第3表のNa36の様に焼成時間が2分より短いも
のも、A1層の焼成が不充分となり、第35 6 表のN[L34と同様の結果となっている。
In addition, when the firing time was shorter than 2 minutes, such as Na36 in Table 3, the firing of the A1 layer was insufficient, resulting in the same results as N[L34 in Table 356.

第3表の磁41の焼成時間が長ずざるもの、第3表のN
a47のように焼成温度が高すぎるものではn壜2が厚
くなり、短絡電流が低下し、そnに起因してVoc +
 F’F’が低下する。
Magnet 41 in Table 3 whose firing time is not long, N in Table 3
If the firing temperature is too high like A47, the bottle 2 becomes thicker and the short circuit current decreases, resulting in Voc +
F'F' decreases.

第3表のNa44のように酸素!1度が高すぎるとAf
i層が酸化さAFFの低下を招くとともに、Niめっき
膜の析出性が低下する。
Oxygen like Na44 in Table 3! If 1 degree is too high, Af
The i-layer is oxidized, leading to a decrease in AFF and the precipitation of the Ni plating film.

なお、第3表中のめっき析出性良好なものでは何nも半
田濡n性は良好であった。
In addition, the solder wettability was good for all of the samples with good plating precipitation properties in Table 3.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明の方法で半導体装置特に太陽電
池を製造す扛は、P土層および裏面電極形成を行う際に
従来困難であった、A1層の酸化防止に不可欠な不活性
雰囲気中での焼成が可能となった。
As described above, the method of manufacturing semiconductor devices, especially solar cells, using the method of the present invention is performed in an inert atmosphere, which is essential for preventing oxidation of the A1 layer, which has been difficult in the past when forming the P soil layer and the back electrode. It is now possible to bake in

1だ、へ2層上へのめっき処理も可能とした。こtLV
?−より従来必要でおった1層の除去、半田付用の電極
形成工程が不要となり、工程数および製造コストの大幅
低減が可能となった。
It is also possible to perform plating on the first and second layers. This LV
? -The removal of one layer and the process of forming electrodes for soldering, which were required in the past, are no longer necessary, making it possible to significantly reduce the number of processes and manufacturing costs.

【図面の簡単な説明】[Brief explanation of drawings]

図は太陽電池の代表的な構成を示した断面図である。 1・・・シリコン基板 2・・・n土層6・・・P土層
 4・・・受光面電極 5・・・裏面電極 代理人弁理士 高 橋 明 夫
The figure is a cross-sectional view showing a typical configuration of a solar cell. 1...Silicon substrate 2...N soil layer 6...P soil layer 4...Light receiving surface electrode 5...Back surface electrode Patent attorney Akio Takahashi

Claims (1)

【特許請求の範囲】 1、P形シリコン基板の一方の主面に、同−導電形不純
物層、および電極を形成するにおいて、AL粉末と、S
n、In+Sbから選ばf′L、り少なくとも一種の金
属と、A1と高融点合金を形成する金属とを主成分とす
るペースト状物質を塗布した後、焼成することを特徴と
する半導体装置の製造方法。 2、Aμ粉末が鱗片状であジ、必要に応じてステアリン
酸、またはステアリン酸アルミニウム、またはステアリ
ン酸亜鉛で表面コーティングさnていることを特徴とす
る特許請求の範囲第1項記載の半導体装置の製造方法。 l Sn+In、Sbから選ば牡た少なくとも一種の金
属の配合割合が、A2粉禾に対して10〜150VoJ
1%/AfAであることを特徴とする特許請求の範囲第
1項記載の半導体装置の製造方法。 4、八!と高融点合金を形成する金属がG o + C
r1Mn+Mo*Ti+zr+B+Wから選ばn九少な
くとも一種の金属であることを特徴とする特許請求の範
囲第1項記載の半導体装置の製造方法。 5、An と高融点合金を形成する金属の配合割合がA
L粉禾に対して5〜30vofi%yAflであること
を特徴とする特許請求の範囲第1項、第4項記載の半導
体装置の製造方法。 と 焼成の温度が660〜900℃であることを特徴と
する特許請求の範囲第1項記載の半導体装置の製造方法
。 Z 焼成の時間が2〜60分であることを特徴とする特
許請求の範囲第1項、第6項記載の半導体装置の製造方
法。 a 焼成の雰囲気が酸素濃度ipppm以下の不活性ガ
ス雰囲気であることを特徴とする特許請求の範囲第1項
記載の半導体装置の製造方法。
[Claims] 1. In forming an impurity layer and an electrode of the same conductivity type on one main surface of a P-type silicon substrate, AL powder and S
Manufacturing a semiconductor device characterized by applying a paste-like substance mainly consisting of at least one metal selected from n, In+Sb, and a metal forming a high melting point alloy with A1, and then firing. Method. 2. The semiconductor device according to claim 1, wherein the Aμ powder is scaly and optionally surface coated with stearic acid, aluminum stearate, or zinc stearate. manufacturing method. l The blending ratio of at least one metal selected from Sn+In and Sb is 10 to 150 VoJ with respect to A2 powder.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the ratio is 1%/AfA. 4.8! The metal that forms a high melting point alloy is G o + C
2. The method of manufacturing a semiconductor device according to claim 1, wherein n9 is at least one metal selected from r1Mn+Mo*Ti+zr+B+W. 5. The mixing ratio of An and the metal forming the high melting point alloy is A
5. The method for manufacturing a semiconductor device according to claim 1, wherein yAfl is 5 to 30 vofi% with respect to L powder. The method of manufacturing a semiconductor device according to claim 1, wherein the firing temperature is 660 to 900°C. Z. The method for manufacturing a semiconductor device according to claims 1 and 6, wherein the firing time is 2 to 60 minutes. (a) The method for manufacturing a semiconductor device according to claim 1, wherein the firing atmosphere is an inert gas atmosphere with an oxygen concentration of ipppm or less.
JP58246950A 1983-12-28 1983-12-28 Manufacture of semiconductor device Granted JPS60140881A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58246950A JPS60140881A (en) 1983-12-28 1983-12-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58246950A JPS60140881A (en) 1983-12-28 1983-12-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS60140881A true JPS60140881A (en) 1985-07-25
JPH0518268B2 JPH0518268B2 (en) 1993-03-11

Family

ID=17156145

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58246950A Granted JPS60140881A (en) 1983-12-28 1983-12-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60140881A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235785A2 (en) * 1986-03-03 1987-09-09 Kanegafuchi Kagaku Kogyo Kabushiki Kaisha Semiconductor device
JP2010272890A (en) * 2010-08-21 2010-12-02 Kyocera Corp Solar cell
CN103377750A (en) * 2012-04-25 2013-10-30 比亚迪股份有限公司 Electrocondution slurry for solar cell back electric field and preparation method thereof and solar cell

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882375A (en) * 1972-02-08 1973-11-02
JPS5110839A (en) * 1974-07-17 1976-01-28 Fujikura Kasei Kk DODENSEITORYO
JPS5478491A (en) * 1977-12-02 1979-06-22 Murata Manufacturing Co Conductive paste
JPS54150994A (en) * 1978-05-18 1979-11-27 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
JPS57208182A (en) * 1981-06-17 1982-12-21 Semiconductor Energy Lab Co Ltd Manufacture of phtoelectric converter
JPS5885574A (en) * 1981-11-18 1983-05-21 Toshiba Corp Solar battery and manufacture thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4882375A (en) * 1972-02-08 1973-11-02
JPS5110839A (en) * 1974-07-17 1976-01-28 Fujikura Kasei Kk DODENSEITORYO
JPS5478491A (en) * 1977-12-02 1979-06-22 Murata Manufacturing Co Conductive paste
JPS54150994A (en) * 1978-05-18 1979-11-27 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacture
JPS57208182A (en) * 1981-06-17 1982-12-21 Semiconductor Energy Lab Co Ltd Manufacture of phtoelectric converter
JPS5885574A (en) * 1981-11-18 1983-05-21 Toshiba Corp Solar battery and manufacture thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235785A2 (en) * 1986-03-03 1987-09-09 Kanegafuchi Kagaku Kogyo Kabushiki Kaisha Semiconductor device
JP2010272890A (en) * 2010-08-21 2010-12-02 Kyocera Corp Solar cell
CN103377750A (en) * 2012-04-25 2013-10-30 比亚迪股份有限公司 Electrocondution slurry for solar cell back electric field and preparation method thereof and solar cell

Also Published As

Publication number Publication date
JPH0518268B2 (en) 1993-03-11

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