JPS60139351U - tuner circuit - Google Patents

tuner circuit

Info

Publication number
JPS60139351U
JPS60139351U JP2634884U JP2634884U JPS60139351U JP S60139351 U JPS60139351 U JP S60139351U JP 2634884 U JP2634884 U JP 2634884U JP 2634884 U JP2634884 U JP 2634884U JP S60139351 U JPS60139351 U JP S60139351U
Authority
JP
Japan
Prior art keywords
circuit
reception
tuner circuit
tuner
mixing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2634884U
Other languages
Japanese (ja)
Inventor
晃一 大谷
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP2634884U priority Critical patent/JPS60139351U/en
Publication of JPS60139351U publication Critical patent/JPS60139351U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

−第1図は従来の混合回路の一般例を示す接続、―、第
2図は二重平衡型差動増幅回路を適用した混合回路を示
す接婢図、第3図は従来のテレビジョン受像機のチュー
ナ回路を示すブロック図、第4図はその詳細構成を示す
接続図、第5図は本考案によるチュiす回路の一実施例
を示す接続図、第6−は受信バンドの説明に供する路線
図であ″、、0981 ”、fl−を−m、82−0.
f、:L−+、゛切換回路、83・・・平衡・不平衡入
力切換回路、84・・・混合回路。
-Figure 1 is a connection diagram showing a general example of a conventional mixing circuit, -Figure 2 is a connection diagram showing a mixing circuit using a double-balanced differential amplifier circuit, and Figure 3 is a connection diagram of a conventional television receiver. Figure 4 is a block diagram showing the tuner circuit of the machine, Figure 4 is a connection diagram showing its detailed configuration, Figure 5 is a connection diagram showing an embodiment of the tuning circuit according to the present invention, and Figure 6 is an explanation of the receiving band. The route map provided is ``,, 0981'', fl--m, 82-0.
f, :L-+, ゛Switching circuit, 83...Balanced/unbalanced input switching circuit, 84...Mixing circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 二重平衡型差動増幅回路を温容回路に用いたチューナ回
路において、受信帯域を2″−′)又はそれ以上の受信
バンドに分けそのうち高周波の受信バンドの受信信号を
上記混合回路に平衡入力させると共に、他の受信バンド
の受信信号を上記混合回路に不平衡人力さすることを特
徴とするチューナ回−路。
In a tuner circuit using a double-balanced differential amplifier circuit as a thermal circuit, the reception band is divided into 2''-' or more reception bands, and the reception signal of the high-frequency reception band is input balanced to the mixing circuit. 2. A tuner circuit characterized in that the tuner circuit is characterized in that it simultaneously inputs received signals of other reception bands to the mixing circuit in an unbalanced manner.
JP2634884U 1984-02-25 1984-02-25 tuner circuit Pending JPS60139351U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2634884U JPS60139351U (en) 1984-02-25 1984-02-25 tuner circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2634884U JPS60139351U (en) 1984-02-25 1984-02-25 tuner circuit

Publications (1)

Publication Number Publication Date
JPS60139351U true JPS60139351U (en) 1985-09-14

Family

ID=30522271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2634884U Pending JPS60139351U (en) 1984-02-25 1984-02-25 tuner circuit

Country Status (1)

Country Link
JP (1) JPS60139351U (en)

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