JPS60137147A - Clock switching system - Google Patents

Abstract

PURPOSE:To prevent digital communication equipment from malfunctioning during system switching by controlling a clock with multiframe pulses for system switching from an FF which is set and reset with multiframe pulses of an in-use and a stand-by system. CONSTITUTION:Clocks C and C' from in-use and stand-by clock sources 8 and 9 which have clock generators 10 and 12 and multiframe pulse generating circuits 11 and 13 are inputted to a clock signal selector 14. Multiframe pulses 1 and 2 from the circuits 11 and 13 are inputted to a multiframe selector 15. When a system switching indication input 16 is supplied externally, a multiframe pulse generating circuit 17 for system switching composed of the FF which is set with the pulse 1 to generate a multiframe pulse 18 for system switching and reset with the pulse 2. When the signal 16 is supplied at a point 29 of time, the pulse 18 is generated with the pulse 1 and pulses 2 having the same intervals 5 and 7 before and after switching are sent out; and the transmission of clocks C and C' is stopped through a gate 19 with the pulse 18 during the system switching period 27.

Description

TECHNICAL FIELD The present invention relates to a clock supply circuit for digital communication equipment, and more particularly to a clock switching method for switching between a working clock and a standby clock.

Conventional technology In order to synchronize the timing of each circuit in the device in a digital communication device, counters with initial setting inputs are used in various timing generation circuits, and the counters are initialized by multi-frame pulses supplied from the clock supply circuit. However, many circuits are now in use that generate the necessary timing by counting clock pulses supplied from a clock supply circuit. When a clock supply circuit that supplies clock pulses and multi-frame pulses to such a digital communication device has a duplicated clock generation source and multi-pulse generation circuit, and the phases of each clock generation source are mutually independent. When switching from the current multi-frame pulse l as shown in Fig. 1(A) to the backup multi-frame pulse 2 as shown in Fig. 1(B) at time 4, as shown in Fig. 1(C), The interval 6 between multi-frame pulses 1 and 2 at the time of switching becomes irregular, and the interval 5 between multi-frame pulses 1 before switching and multi-frame pulse 2 after switching
If the interval is shorter than the interval 7, there will be problems such as the processing cycle of the logic circuit in the communication device being interrupted midway, and there will be disadvantages in that it will cause various malfunctions such as writing errors.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a clock switching method that solves the above-mentioned conventional drawbacks and prevents irregularities in multi-frame pulse intervals before and after switching.

Composition of the Invention The clock switching method of the present invention includes a first clock source having a clock generator and a multi-frame pulse generation circuit, a similar second clock source, and a clock switching method according to the first clock switching method according to an input of an external system switching instruction. and a clock signal selector that outputs the clock pulses output from the second clock source, and a multi-frame pulse selector that outputs the multi-frame pulses output from the first and second clock sources. In the clock switching method for digital communication equipment, the clock pulse and the multi-frame pulse are supplied by the other clock source when one of the clock sources fails.
a multi-frame pulse generation circuit for system switching, which is set by the output pulse of the multi-frame pulse generation circuit of the second clock source and reset by the output pulse of the multi-frame pulse generation circuit of the second clock source; a clock signal sending gate that inhibits the output of the clock signal selector based on the output of the pulse generating circuit; and a multi-frame that combines the output of the multi-frame pulse selector and the output of the system switching multi-frame pulse generating circuit and sends the result. It is characterized by being equipped with a pulse sending game i.

Embodiments of the Invention The present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, the first clock source 8 is composed of a clock generator IO and a multiframe pulse generation circuit 11 that outputs one multiframe pulse for every fixed number of clock pulses output by the clock generator 10. The clock source 9 of No. 2 is similarly composed of a lock generator 12 and a multi-frame pulse generation circuit 13, and inputs the outputs of the clock generators 10 and 12 to a clock signal selector 14.
The output is input to the multi-frame pulse selector 15. When the multi-frame pulse generating circuit 17 for thread trimming 8 is supplied with the system switching instruction input 16 from the outside, it is set by the multi-frame pulse 1 output from the multi-frame pulse generating circuit 11, and the multi-frame pulse generating circuit 1 is set.
It is composed of a flip-flop that is reset by the multi-frame pulse 2 outputted by 3. The clock signal selector 14 and the multi-frame pulse selector 15 are selectors that switch and output input signals according to the output of the multi-frame pulse generation circuit for system switching 17, and the output of the clock signal selector 14 is a selector that switches and outputs input signals according to the output of the system switching multi-frame pulse generating circuit 17. The output of the multi-frame pulse selector 15 and the output of the multi-frame Hals generation circuit 17 for system disconnection are OR-combined by the multi-frame pulse sending gate 20 to produce the multi-frame pulse 22.
is output as The clock signal sending gate 19 is a gate that is closed by the output of the system cutting light multi-frame pulse generation circuit 17.

Next, the operation of this embodiment will be explained. FIG. 3 is a time chart showing the signals of each part in FIG. 2. FIG. The multi-frame pulse 2 outputted by the circuit 13 is shown in FIG.

Now, when system switching is to be performed at time 29 with the first clock source 8 as the active system and the second clock source 9 as the standby system, the system switching instruction input 16 is input to the multi-frame pulse generation circuit for system switching at time 1 29. Since the system switching multi-frame pulse generation circuit 17 is set by the multi-frame pulse 1 and reset by the multi-frame pulse 2, the system switching multi-frame pulse output from the system switching multi-frame pulse generation circuit 17 is The pulse 18 becomes as shown in FIG. 3(C).

Therefore, as shown in the figure, the multi-frame pulse 22 output from the multi-frame pulse sending gate 20 includes multi-frame pulse 1 before switching, multi-frame pulse 18 for system switching during switching, and multi-frame pulse 2 after switching. The interval between the multi-frame pulse 1 before switching and the multi-frame pulse 18 for system switching is the same as the interval 5 between multi-frame pulses 1, and the multi-frame pulse 18 for system switching and the multi-frame pulse after switching The interval between pulses 2 and 2 is the same as the interval 7 between multiframe pulses 2. Of course, multi-frame pulse A and multi-frame pulse 2 are output at approximately the same period, and a fixed number of clock pulses are output between them. Therefore, between the multiframe pulse l and the multiframe pulse 18 for system switching, the number of clock pulses output from the clock I8 sending gate 19, the multiframe pulse 18 for system cutting, multiframe 1, and pulse 2
The number of clock pulses sent in between is the same. While the system switching multi-frame pulse 18 is being sent,
Since the clock signal sending gate 19 is closed, no clock pulses are sent out. Therefore, the clock pulse and multi-frame pulse of this embodiment have the effect that clock switching can be performed without causing a malfunction in the logic circuit within the device during system switching.

Effects of the Invention As described above, in the present invention, a multi-frame pulse for system switching is generated by a flip-flop that is set by a multi-frame pulse of the active system and reset by a multi-frame pulse of the protection system, and Since the transmission of the clock pulse is stopped during the multi-frame pulse generation period for switching, there is an effect that the clock can be switched without causing any malfunction to the digital communication equipment at the time of system switching.

[Brief explanation of the drawing]

Figure 1 is a time chart showing multi-frame pulses during clock switching using the conventional clock switching method;
The figure is a block diagram showing one embodiment of the present invention, and FIG. 3 is a time chart showing signals of various parts of the above embodiment. In the figure, 1, 2: multi-frame pulse, 8: first
clock source, 9: second clock source, 10.12: clock generator, 11.13: multi-frame pulse generation circuit, 14: clock signal selector, 15: multi-frame pulse selector, 16: system switching instruction Input, 17: Multi-frame pulse generation circuit for system cutting, 18: Multi-frame pulse for system cutting, 19: Clock signal sending gate, 2
0: Multi-frame pulse sending gate. Applicant: NEC Co., Ltd. Agent Patent Attorney: Toshimune Shiguchi

Claims (1)

[Claims] a first clock source having a clock generator and a multi-frame pulse generation circuit; a second similar clock source;
a clock signal selector that switches and outputs clock pulses output from the first and second clock sources in response to a system switching instruction input from the outside; and a clock signal selector that switches and outputs multi-frame pulses that the first and second clock sources output. a multi-frame pulse selector for a digital communication device, wherein when one of the clock sources fails, the clock pulse and the multi-frame pulse are supplied by the other clock source; a system switching multiframe pulse generation circuit that is set by an output pulse of a multiframe pulse generation circuit of a first clock source and reset by an output pulse of a multiframe pulse generation circuit of a second clock source; a clock signal sending gate that inhibits the output of the clock signal selector based on the output of the pulse generating circuit; and a multi-frame that combines the output of the multi-frame pulse selector and the output of the system switching multi-frame pulse generating circuit and sends the result. A clock switching method characterized by comprising a pulse sending gate.