JPS60136423A - Frequency synchronizing loop circuit - Google Patents

Abstract

PURPOSE:To make a D/A converter unnecessary by presetting a counter with a digital value indicating a frequency difference and starting counting thereafter and averaging the output of this counter and applying it to a voltage control oscillator. CONSTITUTION:An input frequency signal DELTAS is transmitted with 8 bits. The output of a voltage controlled oscillator (VCO) 8 is outputted as 8-bit information by a counter 13 and becomes a reference signal. The difference between both signals is operated by a subtractor 1 to obtin 9-bit frequency difference information, and this information is integrated by a complete integrator 2 to obtain 10-bit frequency differece information. This information is loaded to a counter 10. The counter 10 outputs the high-level output to an output QC in case of overflow. Since information is loaded at intervals of a certain time, a duty ratio of the output of an FF12 is changed by the loaded value, and the DC level of the output of a low-pass filter 7 is changed in accordance with the loaded value, namely, frequency difference information. The VCO8 is controlled by this DC level to constitute a frequency synchronizing loop circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a frequency-locked loop circuit in which an input signal and a reference signal are digital data, and more particularly to a frequency-locked loop circuit that can be realized with an inexpensive and simple circuit.

(b) Prior Art and Problems FIG. 1 is a block diagram of a conventional frequency-locked loop circuit.

In the figure, 1 is a subtracter, 2 is a perfect integrator, 3 is an adder, and 4 is D
5 is a digital-to-analog converter (hereinafter referred to as a D/A converter),
6 is an amplifier, 7 is a low frequency filter (hereinafter referred to as LPF), 8
9 indicates a voltage controlled oscillator (hereinafter referred to as VCO), and 9 indicates a reference signal generation circuit.

The circuit shown in FIG. 1 synchronizes the frequency of vcos with the frequency of the input signal.

The frequency of this input signal is expressed as digital data, and the frequency of vcos is converted into digital data by the reference signal generation circuit 9.

In operation, the digital data of the input signal and the digital data from the reference signal generation circuit 9 are added to the subtracter 1, frequency difference digital information is obtained, and the digital data is accumulated by the perfect integrator 2, which operates as a loop filter. D/
It is converted into an analog signal by the A converter 5, amplified by the amplifier 6, and added as a control signal to the VCO 8 via the LPF 7.
The cos frequency is synchronized with the frequency of the input signal.

However, in the case of the circuit shown in Fig. 1, the subtracter 1 and the D/A converter 5 constitute a frequency comparator, and a highly accurate D/A
The disadvantage is that a converter is required, the circuit scale is large, the lifespan is long, and the cost is high.

(C) Object of the Invention In view of the above-mentioned drawbacks, an object of the present invention is to provide a frequency-locked loop circuit that can be realized with an inexpensive and simple circuit.

(d) Structure of the invention In order to achieve the above object, the present invention has the following objectives:
Completely integrate the output digital value of the subtracter that calculates the difference between the number of clocks of the input signal and the number of clocks of the reference signal, input this integrated digital value to a counter for the number of bits of the digital value, and By averaging the DC level of the output of the counter over time and applying it to the voltage controlled oscillator that outputs the reference signal, the subtracter and the counter have the function of a frequency comparator. It is characterized by

(e) Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

As an example, we will take as an example the case of an image transmission system in which information on a sampling frequency on the transmitting side is transmitted as a digital signal, and a receiving device reproduces a sampling clock based on this information.

This sampling clock regeneration circuit has an input signal and a reference signal as digital data, and constitutes a frequency-locked loop circuit.

FIG. 2 is a block diagram of the above-described frequency-locked loop circuit according to an embodiment of the present invention, and FIG. 3 shows the digital value of the frequency difference between the outputs of the perfect integrator 2 in FIG. 2 and the counter setting value at the time of loading. The relationship diagram, FIG. 4, is a characteristic diagram showing the output of the RS flip-flop (hereinafter referred to as R8-FF) of FIG. 2.

Items in Figure 2 with the same functions as those in Figure 1 are indicated by the same symbols, and 1
0 is a counter, 11 is a differential circuit, 12 is R8-FF, 6
' is a DC amplifier, 13 is a counter, 14 is 1/1002
The frequency divider 15 is a 1/3 frequency divider, 16 is a 1/1192 frequency divider, and the frequency of the input clock to the 1/1002 frequency divider 14 is 32.064 MHz, and the sampling clock frequency of the input signal and VCO8 Nori ptsu frequency is 9
MI (suppose it is z).

In the circuit of FIG. 2, the input sampling clock frequency information ΔS is a clock frequency divided by 32.064 MHz by 1/1002 frequency divider 14.1/3 frequency divider 15.171192 frequency divider 16. It is assumed that the lower 8 bits of the actually sampled number are transmitted during the synchronization period of approximately 112 m5, and for this input information ΔS, the frequency 9 of the VCO 8 is
The lower 8 bits of the clock number of approximately 112 m5 of the Ml1z clock are generated by an 8-bit counter 13 and inputted to the subtracter 1 as a reference signal to form a frequency locked loop circuit.

The subtracter 1 takes the difference between the two input 8-bit signals to create 9-bit frequency difference information, and the perfect integrator 2 performs complete integration to create 10-bit frequency difference information. This information signal is a straight binary 1, that is, as shown in Figure 3, the frequency difference 0 is 200 (Fl, positive full 5cale is 3FF (Ill, negative full 5cale is ooo
to) (the above is expressed in hexadecimal) using the subtracter 1. This 10-bit frequency difference information is used as a counter setting value when the counter 10 is loaded.

Counter 10 is a 10-bit counter, 32.064
14. Divide the clock of M1lz to 1/1002. 1/
It is assumed that a load is applied every approximately 112 m5 of the clock frequency divided by the 3 frequency divider 15.1/1192 frequency divider 16, and that 1192 pulses are emitted during the clock frequency of approximately 112 m5. In the case where the digital value of the frequency difference of the output of the older total integrator 2 is +10.0°-10, and to explain using FIG. <522, 512, 502. Since the counter 10 is a 10-bit counter, when the count value reaches 1024, the output Qc emits a pulse as shown in FIG.

The time for emitting this level pulse varies as shown in FIG. 4, depending on the setting value at the time of loading.

This level value needs to be continued up to the pulse number 1192 in FIG. 4 at the next loading.

For example, if the value at the time of loading is 1000, the count value may exceed 2047 and the output Qc of the counter 10 may become O in about 112 m5.

In order to prevent this, a pulse is generated in the differentiating circuit 11 at the rising edge of the level, and in addition to R8-FF12, R8-
The reset pulse of FF12 is generally applied for about 112 ms. In this way, if the output of R8-FF12 becomes +Level in any case as shown in FIG. 4, +Level continues until the number of pulses is 1192. R8-F'F with
12, that is, a signal whose DC component changes in accordance with the frequency difference between the input information ΔS and the reference signal, is amplified by a DC amplifier 6' and applied as a control signal to vCO 8 via LPF 7.

In this way, the frequency comparator consists of subtracter I and counter 1.
Since the counter 10 is an inexpensive and simple circuit, the frequency-locked loop circuit is an inexpensive and simple circuit.

The present invention can also be applied to a phase-locked loop circuit in which phase difference information is input as an input signal as a digital value, and the reference signal is a digital value representing the phase.

(f) Effects of the Invention As explained in detail above, according to the present invention, since the frequency comparison circuit can be constructed from a subtracter and a counter, there is an effect that the frequency locked loop circuit can be made inexpensive with a simple circuit construction.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional frequency-locked loop circuit.
FIG. 2 is a block diagram of a frequency locked loop circuit according to an embodiment of the present invention, FIG. 3 is a relationship diagram between the digital value of the frequency difference of the output of the perfect integrator in FIG. 2 and the counter setting value at the time of loading, and FIG. Figure 4 is a characteristic diagram showing the output of the R-S flip-flop in Figure 2. In the figure, 1 is a subtracter, 2 is a perfect integrator, 3 is an adder, and 4 is a D
type flip-flop, 5-digit digital-to-analog converter, 6 is an amplifier, 6' is a DC amplifier, 7 is a low-frequency P wave converter, 8
is a voltage controlled oscillator, 9 is a reference signal generation circuit, 10.13
11 is a differential circuit, 12 is an RS flip-flop, 14 is a 1/1002 frequency divider, 15 is a 1/3 frequency divider, and 16 is a 171192 frequency divider.

Claims (1)

[Claims] Completely integrate the output digital value of the subtracter that calculates the difference between the number of clocks of the input signal and the number of clocks of the reference signal within a certain period of time, and use this integrated digital value as a counter for the number of bits of the digital value. A frequency-locked loop circuit characterized in that the DC level of the input signal and the output of the counter within the certain period of time is averaged and applied to a voltage-controlled oscillator that outputs the reference signal.