JPS60136367A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To augment the integration density while preventing a leak phenomenon between memorizing capacity elements from happening by a method wherein the first conductive plate comprising a memorizing capacity element is electrically connected to one semiconductor region and then the second conductor plate is composed of a semiconductor substrate while an MISFET is arranged on the upper part of the memorizing capacity element. CONSTITUTION:An insulating film 6 stores e.g. hole charges to be any data utilizing the first electrode of a capacity element (the first conductive plate) and the second electrode of the capacity electrode (the second conductive plate). A connecting hole 7 electrically connects the first conductive plate to one semiconductor region MISFETQ. An N<+> type semiconductor region 8 provided near the surface of a semiconductor substrate 1 of the connecting hole 7 electrically connects the first conductive plate to the other semiconductor region of MISFETQ. A memorizing capacity element C is composed of the first conductive plate 9 provided with one end thereof electrically connecting to one semiconductor region of MISFET through the intermediary of the connecting hole 7 and the semiconductor region 8.

Description

[Detailed description of the invention]

TECHNICAL FIELD] The present invention relates to a semiconductor circuit device f! It is related to VC, especially dynamic random access memory.I) RAM (Dyna+nic Rando
The present invention relates to a technique that is effective when applied to the ``AccessMemory''. [Back 1t1] DRAM, which has a memory cell consisting of a storage capacitor and a switching transistor, is designed to increase the amount of 1Ti information (bits) it can store and to improve its operating time. There is a trend toward higher integration. In a city integrated building, -peripheral circuits that make up DltAM, such as an address selection circuit, a readout circuit,
In addition to downsizing semiconductor elements such as single-write circuits, it is also necessary to downsize storage capacitive elements for holding information. This storage capacitor element is required to have a certain predetermined aging value so as to reduce the frequency of the four types of write operations and improve the time for the first and second write operations. For example, if the capacity value is small, Alpha Publishing +! (1,
Malfunctions or soft errors occur due to the influence of unnecessary minority carriers generated by alpha rays. Therefore, DItAM has been proposed, in which a groove is formed in one surface of the semiconductor substrate on which the storage capacitor element is formed, and the inside of the groove is utilized as well as the main surface of the substrate (Japanese Patent Application No. 1987-
53883). This storage capacitive element is M l S (bletal
], nst+-1ator Sem1conducto
R ) type capacitive element, specifically, a pore (U grooves are also formed) provided inward from the uncut surface of the semiconductor substrate, and a pore provided along the pore. It is composed of an insulating film and a capacitor electrode provided so as to cover the insulating film soil. In addition, the switching transistor specifically includes a source region and a υ/drain region provided at a distance from each other on the semiconductor substrate, and a region on the semiconductor substrate between the source region and the υ/drain region. Insulated gate field effect transistor (hereinafter referred to as 841SFET) using an insulating film and a gate electrode provided.
It is composed of: However, as a result of the inventor's experiments and studies, such I
When attempting to further increase the integration density of JRAM, the following problems were identified. The first problem is that the part of the storage capacitor that stores charge that becomes information is inside the semiconductor substrate near the pores.
When the distance between adjacent storage elements is further reduced for the purpose of high integration, the respective depletion regions formed in the semiconductor substrate in the respective pores forming adjacent storage capacitance elements are coupled to each other. As a result of this coupling, a potential difference between the adjacent capacitance parts occurs, which causes a force to move charges from the capacitance part with a low potential to the capacitance part with a high potential, causing a leak phenomenon between the adjacent capacitance parts. It turns out. This tends to cause malfunctions in information read operations, reducing the reliability of the DRAM. This σ
, ) For the following reasons, we cannot expect high integration of DItAM.The second problem is that the three-dimensional capacitor part using pore technology is different from the formation of planar storage capacitor elements in other conventional methods. Compared to the method, it is possible to construct a large volume value so that a large amount of charge can be accumulated in the wide depletion region and inversion layer region within the semiconductor substrate, but at the same time, it is possible to create The shadow 'I#' due to unnecessary minority carriers caused by injection of carriers σ) from σ) also becomes thick tx. This is because the pores ζ extending from the main surface of the semiconductor substrate σ) become deeper. 1) This is because the influence of the 11th minority carrier increases significantly. Unnecessary minority carriers generated by α rays and carrier injection from the peripheral circuitry σ) are retained in the nitrogen depletion layer of the storage capacitor.Reduce the voltage to convert ``0'' information to ``1''
This is because the information is reversed. This may cause a malfunction (soft error) in the information read operation. ζ et al., a predetermined 1! to deal with unnecessary minority carriers caused by α rays. There are limitations to increasing the depth of the pore size ζ in order to reduce the amount of accumulated loads, and it has not been possible to 1) improve the degree of integration of the RAM. [Object of the Invention] An object of the present invention is to provide a RAM that can be highly integrated. Another object of the present invention is to prevent leakage between storage capacitor elements of adjacent memory cells of a DRAM. Another object of the present invention is to reduce the influence of unnecessary minority carriers caused by α rays or injection from the peripheral circuitry in a storage capacitor element of a DRAM memory cell. In general, another object of the present invention is to: 1) increase the operating time of RAM by 1liJ by reducing the leakage current between the memory capacitor elements of DRAM and increasing the information retention time;
It is about making it possible. 7rO1 The above and other objects of the present invention and novelty 1
The heavy machinery will be clearly understood from the following description of the present specification and the accompanying drawings. Summary of the Invention] Among the inventions disclosed in this application, a brief outline of typical inventions is as follows. In other words, a D in which a series circuit of a memory Mf& element and a switching transistor MISFET is used as a memory cell.
RANK (, ;), and a first Sakai plate constituting the storage capacitor is electrically connected to one semiconductor region of the M l S l!'' ET 7 to configure the storage capacitor. A semiconductor substrate is used as a second conductive plate, and a 91+ I 18 F
By orienting the storage capacitor, electric charges serving as information are accumulated in the storage capacitor, and a large two-layer or inversion layer region is not required, thereby preventing a leakage phenomenon between the storage capacitors. In addition, it is possible to reduce the shadow 4!l' of unnecessary nine-sided carriers caused by α rays and injection from the peripheral circuitry, and also to reduce the area fN required for the MISFETK, thereby achieving high integration. Hereinafter, the structure of the present invention will be explained in detail together with examples. [Example 2] This example concerns a DRAM memory cell. Its S structure and its manufacturing method will be explained. 1 DRAM for explaining Embodiment I of the present invention
FIG. 3 is an equivalent circuit diagram showing a main part of the memory cell array of FIG. Note that in Examples 2 to 5, DIIAMs employing one set of folded bit lines will be described. In FIG. 1, +SA, SAt, . B L II - B L It is sense amplifier SA
1 (hereinafter, the direction in which the bit lines extend is referred to as the row direction). BL□,
BL, , are bit lines extending in the row direction from one end of the sense amplifier SA. These bit lines BL are for transmitting charges serving as information. WL,,WL
, is a word line extending in the column direction, connected to a predetermined gate electrode constituting a switching MISFET of a dummy cell to be described later, and the corresponding MlSll'ET0)ON. This is for performing an OFF operation (hereinafter, the direction in which the word line extends is referred to as the column direction). W.L. WL is a word line extending in the column direction, and is connected to a predetermined gate electrode that constitutes a switching MISFET of a memory cell, which will be described later, and is connected to the M1S1'ET (7) ON
, OFF” operation. MHt M
tte Mt□, M22e, . . . are memory cells that hold charges serving as information. Memory cell M++e MHv Mt,t Mtt is Ml S FEi"Q+ whose one end is connected to a predetermined bit line BL and whose gate electrode is connected to a predetermined word line WL.
w Qtt* QtIe Q22...and the M
ISFETQ, s+-Qsz, Q□, Q, 2...
・One end is connected to the other end, and the other end is connected to the ground potential (OLVI) or the substrate bias potential (-2, 5 to -3,
tBV)) connected to the fixed potential v8B terminal. . 0111 01111 Ctt... Dot Dl, e Dnw Dew... are dummy cells, and the information of memory cell 81 is "1", 0
1 holds such a charge that it can be determined that
MISFE whose gate electrode is connected to a predetermined word 1ijWL, one end of which is connected to a predetermined pin 14HL.
TQlll 1+ QDI□l Qozt+ QD2□
...and the MISFETQDIII Qo+r
Qu2x+ '1' D22 and other Q: M K One end of which is connected, and the other end of which is connected to the fixed and usable v8B terminal. “D2
Clear MI to clear the 11 loads accumulated in 2.
SFET0Q. φ0 is a terminal connected to the gate electrode of MISF BTOQ for clearing. Next, the specific structure of Example 2 of the present invention will be explained. FIG. 2 (5) is L) for explaining the structure of this embodiment.
It is a plan view of a main part of a RAM memory cell, and FIG. 2 tBl is a sectional view taken along the line 1-II in FIG. 2 (5). In all the drawings of this embodiment, parts having the same functions are designated by the same reference numerals, and repeated explanations and explanations will be omitted. @2I\1tAle (In the IC, 1 is a p-type semiconductor substrate and is for configuring a DRAM. 2 is a circuit between memory cells and peripheral circuits (not shown) 1
For example, address selection circuit, readout circuit. This is a field insulating film provided on the outer part of the semiconductor substrate 1 so as to be located between the semiconductor elements constituting the write circuit etc., and is for electrically isolating them. The memory cell is recessed around the field insulating film 2 in a pair of patterns. stipulated. Reference numeral 4 denotes a pore (groove) provided in the vicinity of the surface of the semiconductor substrate 1 in the storage capacitor forming portion, and is used to configure the storage capacitor. This pore 4 is
L for memory! The amount of electric charge per unit node in the element is increased by 7j (6 is small /
X is an insulating film provided on the main surface of the semiconductor substrate 1 of the storage capacitor type 1JM portion and on the surface of the semiconductor substrate 1 within the pore 4, and is used to configure the storage capacitor C. This insulation [6] is formed by the first (1) electrode of the capacitive element (hereinafter referred to as the first conductive plate) and the second electrode of the capacitive element (hereinafter referred to as the second conductive plate), which will be described later. It is designed to accumulate the charge of holes. Reference numeral 5 denotes a p+ type semiconductor region serving as a second guiding plate provided near the surface of the semiconductor substrate 1 in the storage capacitor element formation portion and near the surface of the semiconductor substrate 1 in the pore 4;
This is for configuring a storage capacitive element. The p+ type semiconductor region 5 is used to sandwich the insulating film 6 to obtain as much hole charge or depletion layer charge as possible, which is associated with the information stored in the capacitive element, or to apply it to the first conductive plate, which will be described later. It is provided to provide a threshold voltage higher than the operating voltage near the surface of the semiconductor substrate 1. Note that in this embodiment, the semiconductor region 5 is actively provided, but
The semiconductor substrate 1 is used as a second conductive iH plate, and the thickness and quality of the insulating film 6, the threshold voltage near the surface of the semiconductor substrate 1, the operating voltage applied to the first conductive plate, etc. are controlled. However, if the semiconductor region 5 is provided, charges of 1N and 1j may be accumulated in the circuit board F. The semiconductor region 5 is about 1J the same as the substrate 1, that is, the substrate bias Ichikawa VBE [--V]. 7 is a connection hole, which will be described later.
This is for electrically connecting one semiconductor region of the ETQ. 8 is provided near the surface of the semiconductor substrate 1 in the connection hole 7 portion. type semiconductor region, which will be described later.
This is for electrically connecting the guide plate and one semiconductor region of MlSl''E゛1゛Q.9
is provided independently for each memory cell on the upper part of the insulating film 6 of the storage capacitor element formation part, and one end part valves the connection hole 7 and the semiconductor region 8 and is heated at 1°C after 1°C.
It is a first conductive plate provided electrically connected to one semiconductor region of T, and is for configuring a storage capacitor O.Memory cell σ) Storage capacitor O
is mainly the first conductive plate 9. It is structured by a semiconductor region 5, which is a second conductive plate, and an insulating film 6. 10 is an insulating film provided to cover the first guiding σ plate 9; This is for electrically isolating the bamboo plate 9 from a word line, which will be described later, and also between adjacent first evening plates 9. 11 is M1Sl
It is provided on the top surface of the semiconductor substrate 1 in the I″ET formation area.
fI! It is one of the three edge films and serves as a gate insulating film. Reference numeral 12 denotes a gate electrode provided in a predetermined portion of the insulating film 111. 3 is electrically connected to the gate electrode 12 of the memory cell adjacent in the column direction, and is integrated with the gate electrode 12 and extends in the column direction. This is a word line (WL) provided as shown in FIG. n+
It is a type semiconductor region, and together with the north region and the drain axis region, it is the only one that constitutes MlSFET. The switching transistor, ie, MLSk'ETQ, has 11 poles and 12. It is composed of a semiconductor region 14 and an insulating film 1. −
The semiconductor region 14 is electrically connected to the semiconductor region 8, and as described above, is electrically connected to the first Sakai City plate 9. 15 is an insulating film provided so as to cover the entire surface, and is connected to the gate electrode 12 and the word line (WL
) 13 and the bit line described later. 16 is the other semiconductor region] 4 upper part e
) This is a connection hole formed by selectively removing the insulating film 15.11, and is for electrically connecting the semiconductor region 14 and a bit line to be described later. 17 is the connection hole]
A bit line (BL) is electrically connected to the semiconductor region 14 through 6 and is provided extending in the row direction, and is for transmitting a voltage serving as information. Next, b) of the DRAM according to the present invention having a configuration of a child chain.
I will explain the principle. FIG. 3 (5) and (Bl) are graphs for explaining the present invention in detail. In FIG. The vertical axis represents the unit area maintained near the surface of the p-type semiconductor region below by the voltage applied to the capacitor electrode. The figure shows the charge concentration Qsc [number/cffll].The vertical axis is on a logarithmic scale.The figure shows an example of a p-type silicon semiconductor substrate, so the burden induced near the surface is The interelectrode voltage vP>vFB is a negative charge, ■, <vFB is a positive charge. Here, vFB is a flat band voltage. Negative charges consist of electrons or acceptor impurities, and positive charges consist of holes. 3rd The figure shows the case where the holes in the space in the depletion region are used as the charges accumulated along the line axis. In order to facilitate understanding of the present invention, the principle of a conventional DRAM will first be described in FIG. 3 (5). Curve (al, (bl and tel are conventional l) RA
The relationship between the voltage vP at M and the charge concentration use near the surface is shown. In the figure, h is an accumulation region where an accumulation layer can be formed, k is a depletion region, and rll is an inversion region where an inversion layer is formed. The figure shows the curve (b) and (C1 is the area σ near the surface of the semiconductor substrate in the storage capacitor element). The curve (al indicates the number of holes p in the accumulated KN region) n or the number p of positive bills.
# I Oox/ q (VP-V, B) l・---
-・(denoted by tl. Kerf IcI indicates the electron and acceptor impurity pn in the inversion region m, n ”q 06'z / Q (vp
'th) "..." (21 is the main value. Here, C6X is the thickness of the insulating film as a capacitor element.Curve (
bl indicates the number of acceptor impurities that appear in a state where no inversion layer is formed (deep depletion dust) because it is in the inversion region, and is approximately expressed as 08 Cc , (If we take the surface load degree Q8c at the main parts of bl and fcl, when the pressure is 1 u and 2 dVt11, the surface load force, load a degree Q,
,,-1X 10” [pcs/c

[1st, 'fil pressure VP
−(surface negative when +) Q1o=2.2XJu1
1 (cells/C erased). In the conventional DRAM memory cell storage capacitor, the burden of the 17# information was electrons in the 1 inversion region! 11. In other words, at a constant voltage 1, for example, 5 ]
Apply a voltage of about
shall be. In that case, by supplying a heavy load from the outside and forming an inversion layer, the charge of 1QIL (curve (shape B of C1)) is 1QIL, and when no heavy load is supplied from the outside, a deep depletion-like dust (curve tb
+ state) charge layer QIH is formed according to the information. For example, the amount of charge QtL corresponds to the signal 00'' (ie, L'), and the amount of charge Q4 corresponds to the signal ``1'' (ftx, ie, ``H''), and there are two σ charges. Difference in quantity △Qx ”'Qt
LQ1H" 5.3 X 10'2 (i hard/cml)
was used to read out the signal. In contrast, the storage capacitor element of the DRAJI memory cell of the present invention uses the charge serving as information as a spatial burden at least in the depletion region. That is, the DLLAM of the present invention is characterized in that no inversion layer is used. The curve (mountain and tel are 1 of the present invention) shows the relationship between the capacitive electrode voltage (voltage of the first capacitor plate) vP and the voltage a degree Qsc near the surface of the semiconductor region 40 in ItAM. The curve (the peak is an approximation to the curve (al) moved in the negative direction of the π pressure vP (leftward in the figure) f0 flat band Sasazho shows the sleeve of the conventional Vrnx-0,9LV,]] Kara V, BD=-1.2
I set it to Vl. In order to increase the amount of space charge in the nitrogen depletion state without substantially changing the flat band voltage, the p+ type semiconductor region 5 is formed. Specifically, p-type substrate 1
The impurity concentration is increased from 1ff1.5×10″1 [pieces/Cll1] to i,5xio″t pieces/Cll11. This increases the readout charge amount (
are doing. The range of voltages that create the accumulation region, depletion region, and inversion region m also vary. By changing the relationship between +V and Qsc as described above, it is possible to effectively utilize the space cylinder and load in the -depletion region. In other words, if v, = 0 (Vl or 5 [Vl = EiJ) JD''f', depending on the information, is stored on the first conductive plate 7, which is the i-electrode,
The amount of charge changes according to the curve tel. In other words, no inversion layer is formed and a deep depletion state occurs. As a result, the amount of charge QD when V = 0 [v] or the amount of charge QD□ when vP = 5 [v] is accumulated. For example, the charge JiQDL corresponds to a signal "0", and the charge amount QDH corresponds to a signal "1". Difference between two charges △QD=QD,
-QDL = 5.6 x 10 + 2 [pcs/cdl] allows storing 1 bit of information in a memory cell. This amount of charge is equal to or greater than that of the conventional DRAM memory cell described above. In this way, a sufficient amount of charge can be obtained without using an inversion layer. FIG. 3 +DI shows a case in which holes in an accumulated state in an accumulation region are mainly used as charges stored as information. This is shown in Figure 2 tA1. (This corresponds to a case where an extremely shallow p″r type ion implantation region is formed, not a case where a p+ type semiconductor region as deep as B1 is formed. In other words, the implanted boron ions or This is an example of a shallow implantation.The same parts as in the third drawing are designated by the same reference numerals.
The explanation will be omitted. The curves if) and tgl are curves that are approximate to the curves tar and tb+, respectively, shifted by a constant value ζ in the positive direction (to the right in the figure) of the voltage . Specifically, the flat band voltage has been increased from the conventional vFBI""-0,9V) to V, BA-+5.2 LV). For this purpose, boron ions are implanted very shallowly to increase the interfacial charge. The range of the voltage V, which forms the storage region, the depletion region, and the inversion region m, similarly changes by the change in flatband voltage. As described above, by changing the relationship between vP and Q10, the accumulated holes can be used effectively. In other words, the first conductive plate 9 serves as a capacitance pole.
When VP = (ILVI or 5.2 [Vl is marked 7JlI) according to the information, the amount of charge as accumulated information changes according to the curves (fl and (gl). In other words, one inversion region is used and one process is When QAL is V, -5 [V], the charge amount QAH is accumulated.The charge amount QAL is, for example, a signal.
0", the charge amount QAH corresponds to the signal "1"K. The difference between the two charge amounts ΔQA = ΔQAL - ΔQAH is greater than the conventional charge amount 691. In this way, it is possible to The charge amount QAL is held by the holes in the accumulated state, and the charge amount QAII is held by the space charge in the depletion region. Although the positive and negative signs are reversed, there is no restriction on ζ, and the difference in charge amount is shown by ΔQA.Also, when Vp=5 [Vl', QAH is held by the positive plate in the accumulation state on the left side of VFllA in the figure. The curves (fJ and (gl) are controlled by the dose amount of impurity ions. In this example, the dose amount is the same as in the case of Fig. 3 (2). In addition to the principle shown in 770, it is also possible to create a DRAM using a combination of these two methods.At the same time, the amount of interfacial charge is increased by a known method, and at the same time, the amount of space charge in the depletion region is also increased. Also, the same applies when an n-type semiconductor substrate is used. In this case, the charge that becomes one positive charge is a space charge consisting of electrons in an accumulated state or donors in a depleted state. (a) The specific manufacturing method of Example I will be explained. In each figure of FIG. 4 to FIG. tBl in each figure of FIGS. 4 to 11 is a sectional view taken along the cutting line (2) corresponding to the respective figure number. First, in order to form a DRAM W1, , a p-type semiconductor substrate 1 made of single-crystal silicon (81) is prepared.On this semiconductor substrate 1, as shown in No. 41 and IBI, there are arranged between adjacent memory cells and peripheral circuits.For example, address selection Thick field insulating film (<8102 film) for electrically isolating semiconductor elements (indicated by - in the figure) that constitute circuits, readout circuits, write circuits, etc.
form 2. (σ) The field insulating film 2 is formed by a well-known technique of selectively thermally oxidizing a silicon substrate using a silicon nitride film as a mask. After the steps shown in FIGS. 4(2) and 4(B), an insulating film 3A is formed in order to form a second conductive plate in the pores. An insulating film 3B and an insulating film 30 are formed on the entire surface of the semiconductor substrate 1. The insulating film 3C is an etching-resistant mask for forming pores, and is made of, for example, silicon dioxide t-(Siot
) It is better to use a membrane. The insulating film 3B is an impurity introduction mask for forming the second conductive plate, and may be made of, for example, a silicon nitride (SisN*) film. The insulating film 3A is. The semiconductor substrate 1, the silicon nitride film 3B, and σ) are used to relieve stress, and for example, a silicon dioxide film may be used. The insulating film 3A can be formed by thermally oxidizing the surface of the semiconductor substrate 10 (.degree. C. fN).
Thermal oxidation technology, chemical vapor deposition [T; -0V D (
Ochemical Vapor Deposition
). Then, the insulating film 30 in the storage capacitor element formation area is selectively turned to form a first mask for forming pores. Using this first mask, anisotropic σ) dry etching is performed, and the insulating film 3BeaU is removed in an S-fold manner to form a second mask of the insulating film 3B. The substrate 1 is removed to form pores 4 as shown in Figure 51, IBI. The length W of this pore 4 is i-1
, 5, L μm], and the depth ζ from the surface of the semiconductor substrate 1 may be approximately 2 to 4 μm. After the step shown in FIG. 5(2), 5), the insulating film 30 serving as the first mask is selectively removed, and the insulating film 3B serving as the second mask is completely exposed. Using this second mask, impurities are added near the exposed surface of the semiconductor substrate 1 in the pore 4, and as shown in FIG. A semiconductor region 5 is formed. This semiconductor region 5 is applied to a first conductive plate, which will be described later, in order to obtain a charge amount or a depletion layer charge amount which becomes more information stored in the storage capacitor element in the storage capacitor element forming part. Threshold voltage (vth) higher than operating voltage
The shape is good. for example. Poron (B) ions at a concentration of about IXIU'8 (atoms/cd!) or higher at 900 to 1000 L°C]
Introduced and formed by degree of heat diffusion technology. In this case, the depth of the semiconductor region 50 from the surface of the semiconductor substrate 1 toward the inside thereof is 0.3 C μmEJm. After the steps shown in FIG. 6(4) and (I31), the insulating films 3B and 3A are selectively removed, and as shown in FIG. An insulating film 6 is formed.This insulating film 6 consists of a silicon nitride film formed by the OVD method with a film thickness of 1.
In order to relieve the stress between the M silicon nitride film and the semiconductor substrate 1, a
[A] A fourth silicon dioxide film having a film thickness of about 3014, and a second silicon dioxide film having a film thickness of about 3014, for example, provided on the nitride film in order to remove pinholes in the nitride film. It is also possible to use a material composed of a membrane. The first and second silicon dioxide films may be formed by thermal oxidation of the surfaces of the semiconductor substrate and silicon nitride film, respectively. After the step shown in FIG. 7, IB) Vc, the first conductive plate formed in a later step and Mli! The insulating film 6 is selectively removed at the connecting portion with one of the semiconductor regions constituting the 3FET, forming a contact hole 7. After this, the polycrystalline film that will become the first Sakai plate is A silicon film is formed over the entire surface by the JVD method. The polycrystalline silicon film may have a thickness of, for example, about 1500 to 3000 [A]. This polycrystalline silicon film is coated with phosphorus to obtain conductivity. Arsenic (As) ion impurities of about 1 x 1014 atoms/cdll are treated to diffuse them.
After ion implantation with an energy of about 30 (j (eV)),
Perform heat treatment. As a result of this treatment, impurities are diffused into the vicinity of the surface of the semiconductor substrate 1 in the connection hole 7 portion, which constitutes the MISFET that will be formed in a later step. A type semiconductor region 8 is formed. The n" type semiconductor region 8 is provided apart from the p" type semiconductor region 5. This is to prevent the breakdown voltage of the junction from deteriorating due to the formation of a junction between high impurity concentration regions. The depth of the semiconductor region 8 is about +'0.2 Lμm]. After this, the polycrystalline silicon film is selectively patterned, and as shown in FIG.
As shown in U, a first dawning plate 9 is formed, one end of which is electrically connected to the semiconductor region 8 and extends over the insulating film 6 provided to cover the pore 4 . One first conductive plate 9 is provided independently for each memory cell. As a result, the memory capacitor element 0 of the mesori cell is formed. 8th opening, (After the step shown in Bl, the exposed insulating film 6, mainly the silicon nitride film, is used as an i-splash for heat-resistant treatment, and the first opening is made by thermal oxidation technology.
An insulating film (SiOt film) 10 covering the conductive plate 9 is formed. This insulating film 1O has a thickness of, for example, 2,000 to 3,000 [A
It should be around 1. If the pore 4 portion is not filled by this, the filling material 1, for example, a polycrystalline silicon film,
It is necessary to fill the trench with an insulating film. Polycrystalline silicon must be made into an insulator by oxidation. After that, the exposed insulating film 6 is selectively removed, and the 9th layer (
As shown in B1, an insulating film 11 for forming a gate insulating film is formed in the removed portion by thermal oxidation of the exposed surface iMj of the semiconductor substrate 10. This insulating film 1
1 has a film thickness of about 200 LA), for example. Fig. 9 (At, (BIK designation a) fK, M
A polycrystalline silicon film is formed on the entire surface in order to form the gate electrode of l S ii' ET, word scarlet, and semiconductor elements of the peripheral circuit. This polycrystalline silicon film is subjected to the same treatment as described above to reduce its resistance. After this, the polycrystalline silicon film is selectively patterned to form the gate electrode 12.
．． A word@(WL) 13 and a semiconductor element (not shown) of a peripheral circuit are formed. The gate electrode 12 is electrically connected to the gate electrode 12 of another memory cell adjacent in the column direction, and has a word +w13 extending in the column direction.
is configured. Further, the gate electrode 12.
As the word line (WL) 13, molybdenum (Mo),
A high melting point metal layer such as tungsten (W) or titanium (Ti). A 2/1 structure consisting of a silicide or polycrystalline silicon layer which is a compound of the high melting point metal with silicon and a high melting point metal layer or a silicide layer of the high melting point metal thereon may be used. After this, in the M l 8 F'ET forming part, using the gate electrode 12 as a mask for impurity introduction, M l S k' E '1' is applied to the vicinity of the surface of the semiconductor substrate 1 where the insulating film 11 is exposed To form the source and drain regions of the self-aligned
ligment), an n+ type impurity is introduced. This introduced impurity is stretched and diffused, as shown in Figure 10 (5).
) As shown in step 1, an n++ semiconductor region 14 that will become a source region and a drain region is formed. The semiconductor region 8 is electrically connected to the -10,000 semiconductor region 14 . As a result, the memory cell switching transistor I
'(MlsFET)Q is formed at J16. Further, as the n+ type impurity, an arsenic ion impurity may be used and introduced by an ion implantation technique that penetrates the insulating film 11. The depth of the n+ type region is as shallow as about 0.2 μm. After the step shown in FIG. 10 (5) (Bl), an insulating film 15 is formed over the entire surface in order to electrically isolate the gate electrode 12 and word line (WL) 13 from the bit line that will be formed in a later step. The insulating film 15 is made of 7-osilicate phosphosilicate glass (psi) that can soften the undulations on the surface and capture sodium (Na) ions that affect the IJ air quality.
It is better to use a membrane. After this, in order to connect the other semiconductor region 14 to a bit line to be formed in a later step, the insulating film 15.11 on the semiconductor region 14 is selectively removed to form a connection hole 16. . This connection hole 16 is valved and electrically connected to the semiconductor region 14 to form a bit line (BL) 17 extending in the five row direction as shown in FIG. 11(5) 2g3). This bit line (BL) 17 may be formed of aluminum (A/), for example. Thereafter, a PSG film and a silicon nitride film are formed by a plasma OVD method as a final protective film. Through these series of manufacturing steps, the DRAM of this embodiment is completed. Next, the specific operation of Example I of the present invention will be described. The operation of this embodiment will be explained using FIG. 2 (At, tB'l). The operation of a predetermined memory cell will be described first. A control pressure is selectively applied to the gate electrode 12 to
8FETQ is made conductive (ON). After this, a voltage corresponding to the information is applied to the bit line (BL) 17 electrically connected to the semiconductor region 14 via the connection hole 16. This allows the bit line (BL
)17 information is N11S F E T Q
The voltage is applied to the first induction plate 9 through the . The semiconductor region 5 serving as the second conductive plate is electrically connected to the semiconductor substrate 1, and is maintained at a fixed potential of V88K. That is, if there is a potential difference between the potential of the second conductive plate and the information voltage applied to the first conductive plate 9,
Charges serving as information are accumulated in the insulating film 6, which is the intervening portion between them, and written into the memory capacitive element C of the memory cell. When storing information in a memory cell, the MIS
All you have to do is turn off FETQ. Also, when reading information from memory cells. An operation opposite to the write operation described above may be performed. According to this embodiment, a memory capacitor element using pore technology and M
1) RAM that uses a series circuit with ISFET as a memory cell
In the storage capacitive element. an insulating film provided on a predetermined main surface of the semiconductor substrate and on the surface of the semiconductor substrate in the pore, one end of which is provided above the insulating film, and the other end of which is electrically connected to one semiconductor region of the MISFET; It can be configured by a first conductive plate provided as a first conductive plate, and a semiconductor region serving as a second conductive plate provided near a predetermined semiconductor substrate surface and in a pore near the semiconductor substrate surface. As a result, the charge serving as the information can be accumulated in the insulating film at the intervening part between the first conductive turtle plate and the second conductive 1n plate, and the depletion region formed inside the semiconductor substrate can be removed from the pores. It can be suppressed by the second guiding city great. Therefore, it is possible to prevent the respective depletion regions between adjacent storage capacitor elements from being coupled together, and it is possible to prevent a leakage phenomenon between them. Furthermore, since the leakage phenomenon can be prevented, the leakage current between the respective storage capacitor elements can be reduced. As a result, it is possible to improve the charge retention time that serves as information in the storage capacitor element, and reduce the frequency of rewriting operations.Thus, the operating time of the DRAM can be improved. The charges that serve as information stored in the storage capacitor can be the charges in the accumulation region where the accumulation layer is formed or the narrow depletion layer region.Therefore, the electrons accumulated in the wide depletion region or the inversion layer region can be Since there is no need to store information, it is possible to prevent the influence of unfavorable minority carriers caused by α rays and injection from peripheral circuits.Furthermore, according to Kyō et al., storage capacitor elements Since there is no need to consider the degree of influence caused by unnecessary minority carriers, the area occupied by them can be reduced.This makes it possible to increase the integration density of DRAMs.Embodiment I] This embodiment , DltAMO+ memory cell.The structure thereof will be explained, and the manufacturing method thereof will be omitted since it is almost the same as in Example I.In this example, in addition to the first city plate soil of Example I, This is an example in which the third conductive plate to which a fixed potential is applied is straddled to increase and stabilize the capacitance value.
FIG. 12 is a plan view of a main part of an ItAM memory cell, and is a cross-sectional view taken along the line (5) in FIG. 12 (5). 12 (5) and (B), 6A indicates the insulating film provided to at least cover the first conductive plate 9. 6
This is an insulating film having the same structure as the above, and is used to constitute a storage capacitor element. This insulating film 6A is configured to accumulate hole charges, which serve as information, by the first conductive plate 9 and a third electrode (hereinafter referred to as a third conductive plate) to be described later. Further, the first conductive plates 9 of adjacent memory cells are electrically isolated. A third conductive plate 18 is provided above the insulating film 6 and connected and integrated with the third conductive plate of other memory cells in the same memory cell array, and serves as a storage capacitor. It is for configuring the element. A fixed potential, for example, the same potential as the substrate is applied to the third conductive plate 18. The storage capacitive element of the memory cell is connected to the first conductive plate 9. Capacitor C consisting of semiconductor region 5 and insulating film 6 which is the second conductive plate
and a first conductive plate 9. It is configured by connecting the third conductive plate 18 and the capacitor C1 made of the insulating film 6A in parallel circuit. IOA is the third conductive plate 1
8, and is an insulating film provided to cover the third conductive plate V
-) 18 and the word line (WL) 13 electrically. When a concrete memory cell array is constructed using the memory cells shown in the twelfth color space (Bl), it becomes as shown in FIG. 13. 13 is a schematic plan view of a main part of a memory cell array for explanation. In order to make the drawing easier to see, an insulating film in which six conductors should be provided between layers is not shown in FIG. 13. In the figure, the plane is the same as that of Embodiment I except for the third conductive plate 18. Next, the concrete operation of Embodiment 2 of the present invention will be explained. The operation of this embodiment is shown in FIG. 12 ( The operation of a predetermined memory cell will be explained using Al, (Bl. First, the case of writing information to the memory cell will be explained. A control voltage is selectively applied to the gate electrode 12 constituting the Ml 5FETQ of the memory cell. Then, the Ml 5
Turn on FETQ. After this, bit # (B
L) Apply a voltage serving as information to 17. To this, X:
Therefore, the voltage serving as information on the bit line (BL) 17 is MI
It is applied to the first conductive plate 9 via SFETQ. The semiconductor region 5 serving as the second conductive plate is electrically connected to the semiconductor substrate 1 and held at a predetermined fixed potential v8g, and for example, the third conductive plate 18 is also held at a fixed potential v88. That is, if there is a potential difference between the potentials of the second conductive plate 18 and the third conductive plate 18 and the information voltage applied to the first conductive plate 9, the insulating film 6 and the insulating film 6A, which are the intervening parts thereof, Charges that serve as information are accumulated in the storage capacitive element of the memory cell. will be written to. When storing information in a memory cell, the MI
5 FET (1-OFF). Also, when reading the 1-ft information of the memory cell, it is sufficient to perform the operation opposite to the above-mentioned winding operation. Reduction of each quantity and M
DILAM whose memory cell is a series circuit with ISFET
In this case, eleven effects similar to those in Example I can be obtained, and furthermore, an insulating film is provided on the top of the first conductive plate.
By providing the third conductive plate, the amount of charge accumulated by the first conductive plate and the second conductive plate and the amount of charge accumulated by the first conductive plate and the third conductive plate can be stored in a capacitive element for storage. The amount accumulated can be measured. As a result, the amount of charge storage in the area occupied by the storage capacitor element can be increased by about twice as compared to the first embodiment, and it is possible to further increase the integration of L) RAM. In addition, by providing the third special plate with a fixed potential above the first conductive plate, it is possible to prevent the word line to which a control voltage whose voltage varies from positive to negative from affecting the first conductive plate. Therefore, the amount of holes accumulated in the storage capacitor can be stabilized. As a result, it is possible to stabilize the read and write operations of the DRAM, and it is possible to achieve high reliability of the DRAJI. [Embodiment 2] In this embodiment, the structure of the memory cell /L/ of a DRAM will be explained, and the manufacturing method thereof will be omitted since it is almost the same as that of the above-mentioned embodiment I. This embodiment is an example in which the field insulating film provided between memory cells in Embodiment R is reduced to achieve higher integration. 8g14 Figure (4) is a plan view of the main part of the RAM memory cell for explaining the structure of this embodiment.
111Bl is a sectional view taken along the cutting line V in FIG. 14(2). In all the figures of this embodiment, parts having the same functions as those of the embodiment i are given the same reference numerals, and repeated explanations thereof will be omitted. In No. 14111Bl, 12A is a semiconductor substrate between predetermined memory cells and peripheral circuits (not shown) 1, for example, between semiconductor elements constituting an address selection circuit, readout circuit, write-in circuit, etc., for example, between MISFETs] Main surface part σ) is a field insulating film provided for electrically isolating them. The memory cell is the fourteenth
As shown in the figure (OIK), the field insulating film 2AKJ is formed in a pair of patterns repeating in the row direction:
It's shaped like that. Two field insulating films are provided between adjacent memory cells in the column direction in the memory cell array. Note that 14A is a region where an n+ type semiconductor region that will become a card ring is to be formed. Reference numeral 5A denotes a second conductive plate p" provided near the surface of the semiconductor substrate 1 in the storage capacitive element formation area and integrally provided with adjacent storage capacitive elements in the row direction.
This is a type of semiconductor region. This situation is shown in No. 1491 (01).It is used to configure a storage capacitor and at the same time electrically isolate adjacent storage capacitors in the row direction. To provide a threshold voltage higher than the operating voltage applied to the first conductive plate in the vicinity of the surface of the semiconductor substrate 1 in order to obtain hole charges or depletion layer 11 charges which become a lot of information stored in the semiconductor substrate 1. Furthermore, the semiconductor region 5A has a structure for suppressing the extension of a depletion region formed from the surface portion of the semiconductor substrate 1 underneath the first conductive plate toward the inside thereof when a voltage is applied to the first conductive plate. Note that the semiconductor region 5A only needs to have a higher impurity concentration than the semiconductor substrate 1.
Fig. 14 (The cross section along cut 1B-B in q is the 7th
It is the same as the one in which the field insulating film 2 existing between two adjacent pores 4 is omitted in Figure U (the insulating film 6
(not shown). According to this embodiment, a memory capacitor element using pore technology and M
In a DRAM in which a series circuit with an ISFET is used as a memory cell, the same effect as in Example 1.11 can be obtained, and furthermore, the storage capacitor element is connected to the other storage capacitor element adjacent in one row direction. K because they can be electrically separated from each other by a semiconductor region which is a second conductive plate. There is no need for a field insulating film occupying a large area in the DRAM, and it is possible to increase the productivity of the DRAM. [Embodiment (2)] In this embodiment, the structure of a mesori cell of a DRAM will be explained, and the manufacturing method thereof will be omitted since it is almost the same as that of the above-mentioned embodiment (2). This embodiment is an example in which the number of field insulating films provided between memory cells in Embodiment 2 is reduced to achieve higher integration. Alternatively, in Example 2, a third conductive plate is provided to sandwich the insulating film on the first conductive plate to increase the storage capacity. FIG. 15(3) shows D for explaining the structure of this embodiment.
FIG. 15 (■) is a plan view of the main part of a RAM memory cell.
FIG. 15 is a sectional view taken along the line xv-xv in FIG. 15(5). The state of part of the memory cell array of this embodiment during the manufacturing process is shown in the same manner as in FIG. 14+a+. In all the figures of this embodiment, parts having the same functions as those of the embodiments II and In are given the same reference numerals, and repeated explanations thereof will be omitted. According to this embodiment, memory cells can be arranged at a higher density in the row direction than in the embodiment (2). This is because there is no field insulating film between memory cells adjacent to each other in the row direction. According to this embodiment, the capacity that can be stored in the memory cell can be increased more than in the embodiment (2). This is the same relationship between Example H and Example (2). Of course, the effects obtained in Examples (1) and (2) can also be obtained in the same manner. [Example 2] Next, a specific manufacturing method for the DRAM of Example 2 of the present invention will be explained, and a specific structure thereof will also be explained. This embodiment is an example in which the provision of two field insulating films for electrically separating memory cells adjacent in the column direction in Embodiment 2 is omitted, and no field insulating film is provided in the memory cell array at all. It is. 16 to 18 are plan views of essential parts of the DRAM memory cell array in each manufacturing process for explaining the manufacturing method of this embodiment. In all the figures of this embodiment, parts having the same functions as those of the above-mentioned embodiments I and II are given the same reference numerals, and repeated explanations thereof will be omitted. First, a field insulating film is formed on the semiconductor substrate 1K by selective thermal oxidation of the substrate 1 in order to electrically isolate semiconductor elements (not shown) of one peripheral circuit except for the memory cell array section. Then, the semiconductor substrate 1 is exposed by forming the pores 4 at .degree. After this, a mask 19 for resisting impurity introduction is selectively formed on the top surface of the semiconductor substrate 1, which is a region where a switching MISFET to be formed in a later step is to be formed. Thereafter, p-type impurities are introduced into the surface of the semiconductor substrate 1 other than the mask 19 and into the surface of the semiconductor substrate 1 within the pores 4 using the mask 19 . As a result, as shown in FIG. 16, the second
It becomes a conductive plate. In addition, p'' type semiconductor regions 5B are formed to electrically isolate adjacent memory cells in the row and column directions. After the process shown in FIG. An insulating film 6 is formed on the first insulating film 6, which will be formed in a later step.
The insulating film 6 is selectively removed at the electrical connection portion between the conductive lid plate and a part of the semiconductor region constituting the MISFET, and a connection hole 7 is formed. Thereafter, a polycrystalline silicon film serving as a fourteenth electrode plate is formed over the entire surface, and n+ type semiconductor regions 8 are selectively formed by As ion implantation. After this, apply the polycrystalline silicon film:! ! ! Selective patterning is performed to form a first conductive plate 9 as shown in FIG. In addition, the cross section along the cut edge (2)-xvn is the same as that shown in FIG. 8 (B with the field insulating film 2 omitted. After the process shown in FIG. A storage capacitor element CI is formed by forming a third conductive plate (third conductive plate) 18, and after forming insulating films 1UA and 11, a gate electrode 12 and a word line (WL) 1 are formed.
3 and forming the semiconductor region 14.
15FETQ is formed, and an insulating film 15. After forming the connection hole 16, as shown in FIG.
form 7. In FIG. 18, in order to make the drawing easier to see, the insulating film to be provided between the isoelectric nodes is shown 1f. In addition, the cross section along the cutting line -XVI is the same as that shown in FIG.
M is completed. After this, the above examples! , In the same manner as If, a haze-protecting film or the like is applied. Note that in this embodiment as well, the p''' type semiconductor region 5B and the n
The +-type hemi-rostral body region 8 needs to be provided apart from it, as in the other embodiments. According to this embodiment, a storage capacitor element using pore technology and M
IJIL that connects the series circuit with ISFET to the memory cell
In AM, the above Example 1. The same effect as in II can be obtained, and furthermore, the memory cell of D) LAM is connected to the other memory adjacent in the row direction and the column direction by the semiconductor region which is the second conductive plate that constitutes the storage capacitor element. Since it can be electrically isolated from the cells, there is no need for any field insulating film in the memory cell array, making it possible to achieve high integration of AM. It goes without saying that the formation of the third conductive grating 18 may be omitted.This is the same as the relationship between Examples (2) and (2) or Examples (2) and 1v.D) In this case, the plane of the tAM memory cell. The cross section and the cross section during the manufacturing process are those of Example 1. [This will be clear from the explanation of [and ■]. Embodiment 2] This embodiment describes the structure and method of using a DRAM memory cell. In Examples I to V, when higher integration is achieved,
p+ type semiconductor regions 5, 5A serving as second conductive plates;
5B and the nf type semiconductor region 14 of MISFETQ are in close proximity or form a pn junction. These semiconductor regions5. 5A, 5B, and 14 have high impurity concentrations and are therefore unfavorable in terms of electrical characteristics. This embodiment improves these. This is an example of achieving even higher integration. FIG. 19 shows a DRA for explaining embodiment ① of the present invention.
FIG. 2 is an equivalent circuit diagram showing a main part of a memory array of M. It should be noted that for Examples Vl to Embodiment 2, the &i.me open bit line method is adopted and 16 cases are explained for 7CD RAM. Oite in the 19th @, bit line B Lu -B LH-B
L, , BL, . . . are sense amplifiers SA1. S.A.
. . . are provided in a pair extending in the row direction from both ends of the line. SW is a switch element connected to a pair of pins iBl, and is used to short-circuit them. As a result, the memory cell array does not require a dummy cell having a capacitive element with a charge storage amount 1/2 that of the memory cell M. Next, the specific structure of Example 2 of the present invention will be explained. The 20th Guard is the fl of this example! D for explaining the structure
FIG. 1 is a plan view of a main part of a RAM memory cell, and FIG.
tI3) is a sectional view taken along the xx-xx cutting line of the 20th Guard. 1. C. In FIG. 20(5), in order to make the drawing easier to see, the insulating film that should be provided between each conductor layer is not shown. In Fig. 20, (B), 9A is provided independently for each memory cell on the upper part of the insulating film 6 of the storage capacitor element forming part, and is located at one end or one of M l S )'ET to be described later. Q) A first guide plate, which is electrically connected to the semiconductor region and provided as in the embodiments I to V above. IOB
is an insulating film provided to accommodate the first electric brake) 9A, and as a king, the first electric brake) 9A and 11811"BT placed above it, which will be described later, are also adjacent. The insulating film 10B is used to electrically isolate the first conductive plates 9A between the first conductive plates 9A and the word line (WL).
It is also possible to insert the pore 41Bi together with the first conductive plate 9A and flatten the upper surface thereof. 7A is the first guide car play) 9A and fVl 1 S described later
A connection hole is provided by selectively removing a portion of the insulating film 10B that is connected to one semiconductor region of the FET,
It is for electrically connecting them. 20 is connected to one end of the first guiding plate 9A at a predetermined portion, and is arranged in pair with the adjacent capacitive element 0 in a predetermined direction on top of the capacitive element O via the r5 film JOB. This is a semiconductor plate made of single-crystal silicon, and is used to configure the ■i 5FET. II
A is an insulating film provided to at least cover the semiconductor plate 20, and serves as a gate insulating film of the MISFET. 14A is gate electrode 1
This is an n+ type semiconductor region provided in a direction from the depth of the semiconductor plate 20 on both sides of the semiconductor plate 20, and serves as a north region and a drain region to constitute a MISFET. Switching transistor, namely MlSF E
TQ is the gate electrode 12. Semiconductor region 14A. Semiconductor plate 2 () and insulating film 11A,! = [, J
: It is composed of: - The semiconductor region 14A is connected ζ4 to one end of the fourteenth plate 9A via the connecting hole 7A. Next, a specific manufacturing method of Example 5 of the present invention will be described. 21-25 are plan views of main parts of the DRAM in each manufacturing process for explaining the manufacturing method '12r of this embodiment, and each of FIGS. In the figure, (B) is a cross-sectional view taken along the cutting line corresponding to each figure number.In addition, the peripheral circuit of DRAM is The manufacturing process of the constituent Ml 5FET (left figure in the figure) will also be explained.If, excluding the memory cell array part, an insulating film 21 is formed on the cut surface of the p-type silicon semiconductor substrate in the area where the MISNET is to be formed. A p-type channel stopper region 22 and a field insulating film 2B are formed on the upper main surface of the semiconductor substrate 1 between the regions where the 1M1SFET is to be formed.After this, the method of Example I is applied to the memory cell array region.
In the same manner as above, the pore 4 is released, and a p+ type semiconductor/body region 5B, which becomes a second conductive plate, is formed near the surface of the semiconductor substrate 1 and in the vicinity of the surface of the semiconductor substrate 1 exposed inside the pore 4.
form. Then, as shown at tBl in FIG. 21(5), an insulating film 6 made of Sin is formed over the entire surface. After the step shown in FIG. 21(5) + tE, a first α-conductor plate 9A is formed on the insulating film 6 so as to cover the pore 4 in the memory cell array portion. 1st guide city play) 9
In A, a polycrystalline silicon film formed by the 0V1 method was used, and the film thickness was 800 to 1200 [A1
The condition is good to a certain degree. As a result, the storage capacitive element C of the memory cell is formed. After this, the first conductive plate)
An insulating film 10B is formed on the entire surface so as to cover the first
The insulating film 10B in the portion to be connected to the conductor plate 9A and the semiconductor region of the MlSFE"J) is selectively removed to form a connection hole 7A. The insulating film 10B is
For example, a silicon oxide film (S iOt ) formed by the OVD method may be used, and the film thickness may be approximately 3,000 to 4,000 LA. And, as shown in Figure 22, [F]),
To form a semiconductor plate of single crystal silicon, O
A polycrystalline silicon film 20A is formed over the entire surface by the VD method. Polycrystalline silicon film 2OA. For example, the film thickness may be about 2500 to 350 HA.The polycrystalline silicon film 2OA is designed to valve the connection hole 7A and connect to the 14th ton plate 9A. ), (B), the polycrystalline silicon film 2OA is made into a single crystal silicon film.
For example, heat treatment technology using 0W argon laser (Ar-Laser), specifically, energy 3 to 15 [W],
Scanning speed [5 to 100 [cm/S]], substrate temperature 300
If laser annealing is performed under the conditions of [°C] and a beam diameter of 30 [μm], this will work. Then, an impurity for controlling the threshold voltage of the 5Ml5FET is introduced into the main surface of the single crystal silicon film, at least in a portion where the channel of the MlSFET is to be formed. This is, for example, lXl0”L
Valency/cf] Boron ions with a purity of 50 to 70 [
It is preferable to perform heat treatment after ion implantation at an energy of about 1000 keV]. After this, as shown in FIG. ) 9A and constitutes another storage capacitor element adjacent to the other end via the connection hole 7A. lW play) At least 1t connected to 9A, the part where the channel of MlsFET should be formed is a p-type semicircular play) 2
0 is formed, and further, predetermined portions of the insulating films 10B, 6 and 21 are selectively removed, and p? Nl5 constituting the surface of the semiconductor region 5B of the mold and the peripheral circuit
The top surface of the semiconductor substrate 1 in the FET forming portion is exposed. After the step shown in 131, the semiconductor plate 20 exposed in the memory cell array section, the first conductive plate 9A, the p+ type semiconductor region 5B, and one peripheral circuit are removed by a thermal oxidation technique. An insulating film 11A made of Sin so as to cover the surface portion of the semiconductor substrate 1 exposed in the MISF'ET forming portion constituting the
11B is formed. Insulating film 11A. 11B mainly covers the gate insulating film of the MISFET.
The film thickness is reduced to 200-30% by thermal oxidation so that it can be
0 [It may be formed to about A1. After this, insulating film 1
A gate electrode 12 and a word line (WL) 13 electrically connected to the gate electrode 12 and extending in the column direction are formed above the gate electrode 1A, and a gate pole 12A is formed above the insulating film 11B. Then, at a second temperature (as shown in Bl, in the memory cell array part), an n"" type semiconductor region 14A is formed on the semiconductor plate 20 with the insulating film 11A on both sides of the gate electrode 12. At the same time, one peripheral circuit is formed. In the M 1 S FET forming part constituting the gate electrode 12A, an n+ type semiconductor region 4B is formed on the main surface of the semiconductor substrate 1 via the insulating film 11B on both sides of the gate electrode 12A. The MlsFETQ of the memory cell and the MIsFETQt of the peripheral circuit are formed by this.
The semiconductor region 14A of S k'ETQ is stretched to a depth equal to or greater than the film thickness of the semiconductor plate 20 so as not to be diffused. FIG. 24(2), (After the step shown in Bl, an insulating film 15 is formed on the entire surface in the same manner as in Example 1. Insulating film 1
5 consists of a phosphorus silicate glass (PSG) film. After this, the predetermined semiconductor region 14A. 14B upper insulating film 11A. IIB. 15 is selectively removed to form a connection hole 16.16A. And the 25th
As shown in FIG.
A is electrically connected to the semiconductor region 14B and is formed as a wiring 17A' on the insulating film 15. After this, PSG film and plasma OV film are used as the final protective film.
A silicon nitride film Y3b is formed by method D. The DRAM of this embodiment is completed through these series of manufacturing steps. Using the memory cell formed in this way. A concrete memory cell array is constructed as shown in FIG. 26. FIG. 26 is a schematic plan view of a main part of a memory cell array for explaining Embodiment 2 of the present invention. A memory cell array can be constructed by repeatedly arranging the two memory cell notches shown in FIG. 20 in a matrix. Note that in FIG. 26, in order to make the drawing easier to see, an insulating film that should be provided between each conductive layer is not shown. The specific operation of this embodiment is substantially the same as that of Embodiment I, so a description thereof will be omitted here. In this example, a memory capacitor element using pore technology and M
DRAM whose memory cells are series circuits with ISI"ET
In this case, the same effect as in the first embodiment can be obtained, and furthermore, the MISFET can be placed above the storage capacitor element. The area required for providing MlSl'ET is 11<1, which enables high integration of DRAM. Further, the Ml 8FET is connected to the memory valley fir. M l S k
The breakdown voltage in the reverse direction due to the junction between the n+ type semiconductor region of the ET and the p+ type semiconductor region serving as the second conductive plate of the storage capacitor element is not deteriorated. This allows DRAMs to be highly integrated. In addition, by providing the MISFET on the semiconductor plate, 1M1S11
'Unnecessary parasitic capacitance caused by the pn junction between the semiconductor region of the ET and the semiconductor plate can be reduced. This makes it possible to reduce unnecessary damage added to the bit lines, thereby making it possible to omit information and speed up line input/output operations of the DRAM. Furthermore, by providing the MlSFET on the semiconductor plate, the diffusion depth of the semiconductor region of the MISFET can be defined by the thickness of the semiconductor plate, which prevents unnecessary diffusion of impurities into the region where the channel should be formed.
The effective channel length of the ISFET can be secured. This can prevent short channel effects. Of course, the effects obtained in Examples I to V can also be obtained in the same manner. [Example ■] This example concerns a DRAM memory cell. The structure and manufacturing method will be explained below. In this example, a third conductive plate 18 to which a fixed potential is applied is further provided on the first conductive gray plate 9A of Example (2),
This is an example of increasing and stabilizing the capacitance value. This is the same as the relationship of Example I to Example I. FIG. 27 tAl is a plan view of a main part of a DRAM memory cell for explaining the specific structure of this embodiment;
Figure (Bl is a sectional view taken along the ℃■ - ℃ (to) cutting line in Figure 27 (5). In addition, Figure 27 (2) is a cross-sectional view taken between each conductor TlLrtI in order to make the drawing easier to see. The insulating film to be formed is not shown in the figure.
Since it is almost the same as , it is omitted here. Next, a specific manufacturing method of Example 2 of the present invention will be explained. 4 in Figures 28-30! In Figure r, (4) indicates D in each manufacturing process for explaining the manufacturing method of this example.
28 to 3 are plan views of main parts of a RAM memory cell; FIG.
In each figure in Figure 0, (BJ is a cross-sectional view taken along the cutting line 4 corresponding to the respective figure number. First, in the memory cell array part of the semiconductor substrate l. A p'' type semiconductor region 5B, which becomes a second conductive plate, is formed in the vicinity of the surface of the semiconductor substrate 1 and in the vicinity of the surface of the semiconductor substrate 1 exposed in the pore 4. Then, StU is formed on the entire surface. , and as shown in FIG. 28 (2) and (No. 8), a polycrystalline silicon film that has been subjected to a predetermined patterning process in order to form a first conductive plate on the top of the insulating film 6. A film 9B is formed. After the step shown in FIG.
Form A. Then, as shown in FIG. 29(B), a polycrystalline silicon film 18A which has been patterned in a predetermined manner is formed to form a third conductive plate. After the steps shown in FIGS. 29(3) and (B), the exposed absolute f#! Thermal oxidation is performed using the nitride film of the film 6A as an oxidation-resistant mask, an insulating film 1osv is formed on the entire surface so as to cover the polycrystalline silicon film 18A, and the first conductive grating 9A and M 1 SI! 'ET -1 semiconductor region of the insulating film 6Afir in the portion to be connected is selectively removed to form a connection hole 7A. After this, a p-type semiconductor plate 20 is formed on the insulating film 10B in the portion where the storage capacitor element is to be formed, and along with this formation, unnecessary insulating films JOB, 6A, 6 and unnecessary polycrystalline silicon film are formed. 1
8A and 9B are selectively removed to form a first conductive plate 9A and a third conductive gray plate 1B, as shown in Figure 301 (B). FIG. 30 (5), (After the step shown in Bl, by performing the steps after the step shown in FIG. 23 of Example Vl, ff3), as shown in FIG. 27 1 (Al, mountain). The DRAM of this embodiment is completed. Thereafter, a protective film is applied in the same manner as in the previous example. A concrete memory cell array using the memory cells J16 formed in this way is shown in FIG. 31. FIG. 31 is a schematic plan view of a main part of a memory cell array for explaining Example 2 of the present invention. A memory cell array is constructed by repeatedly arranging two memory cells shown in FIG. 27. Note that in FIG. 31, in order to make the drawing easier to see, an insulating film to be provided between each conductive layer is not shown. Note that the specific operation of this embodiment is substantially the same as that of the embodiment (2), and therefore will not be described here. According to this embodiment 11, it is possible to obtain the same effect as in the above embodiment (2) in a DILAM whose memory cell is a memory capacitive element using pore technology and a blood test circuit of M I S F E '1'. Furthermore, by providing a third conductive plate above the 14% plate with an insulating film interposed therebetween, it is possible to obtain the same effects as in Example 2 and ILV. [Example %]If ] In this example, the structure of a DRAM memory cell will be explained, and the manufacturing method thereof is almost the same as that of the above-mentioned example (2), so the explanation thereof will be omitted. This example is Example Vl odor'''C first conductive, plate and M
This is an example of reducing the amount of work required to connect the LSFET to the semiconductor region, further increasing integration, and facilitating mask alignment for these connections. No. 324 is a plan view of the main part of a DRAM memory cell for explaining the specific structure of this embodiment, and FIG. 32 (
t3+&! , IW 32 Figure 1A (1) XXXII
-XXX[[This is a sectional view taken along the cutting line. In addition, the third
24 times. In order to make the drawing easier to see, an insulating film to be provided between each conductor t# is not shown. In FIG. 32, (■), 90 is a first conductive plate provided on the insulating film 6 so as to be embedded in the pore 4. The first conductive plate 90 has a substantially flat upper surface. A connection hole 7B is provided by selectively removing the insulating film JOB above the first conductive plate 9C, and is for electrically connecting the first conductive plate 9C and the MISFET. Note that the specific operation of this embodiment is substantially the same as that of embodiment I, and therefore will not be described here. According to this embodiment, a memory capacitor element using pore technology and M
It is possible to obtain the same effect as in the above-mentioned Example ⑶ in a DRAM whose memory cell is a series circuit with ``l S k' E i'', and ζ et al.
By electrically connecting the T with the semiconductor region at the upper part of the first s-electrode plate embedded in the pore, the area required for the connection can be reduced. This makes it possible to: l) achieve high integration of RAM; Furthermore, by electrically connecting the storage capacitive element and the MISFET to the semiconductor region above the first conductive plate embedded in the pore, it is possible to facilitate mask alignment for their connection. Effect] In 1) RAM in which a series circuit of a storage capacitor and M1SFB'l' formed by pore technology is used as a memory cell, (11. an insulating film provided on the surface of the semiconductor substrate in the M1Sk″ET; 1 conductive plate, and a semiconductor region serving as a second conductive plate provided near the surface of a predetermined semiconductor substrate and near the surface of the semiconductor substrate in the pore. The charge pA1 can be accumulated at both ends of the insulating film in the intervening portion between the conductive plate and the second conductive plate, and the depletion region formed inside the semiconductor substrate from the pore can be transferred to the second conductive plate. Therefore, it is possible to prevent the coupling of respective depletion regions between adjacent storage capacitor elements, and to prevent the leakage phenomenon. (2) Preventing the leakage phenomenon As a result, the leakage current between each storage capacitor element can be reduced.This improves the charge retention time that serves as information in the storage capacitor element, and reduces the frequency of rewriting operations. Therefore, the operating time of the DRAM can be improved. (3) The charge that becomes the information stored in the storage capacitor 11 elements, the t in the storage region where the storage layer is formed or the narrow depletion region. (TJ can also be used. Therefore, since there is no need to use deuterons accumulated in a wide depletion region or inversion layer region as information, unnecessary minority carriers generated by α rays or injection from peripheral circuits are eliminated. (4) Since it is not necessary to consider the shadow caused by unnecessary minority carriers caused by α rays, the area occupied by the storage capacitive element can be reduced. This makes it possible to make the DRAM into a sieve. (5) By providing a third conductive plate on top of the first conductive plate constituting the storage capacitor with an insulating film interposed therebetween, The amount of charge that can be accumulated by the first conductive plate and the second conductive plate can be multiplied by the amount of charge that can be accumulated by the first conductive plate and the third conductive plate.By this, the amount of charge that can be accumulated by the first conductive plate and the second conductive plate can be multiplied by S. (6), above 1) ILAM memory cells are arranged in the row direction, column direction, or the Since it can be electrically isolated from other adjacent memory cells in both directions, there is no need for a field insulating film formed by selective thermal oxidation technology on the semiconductor substrate, making it possible to increase the integration density of IJRAM. can. (7) By providing a fixed third conductive plate above the first conductive plate constituting the storage capacitor, the word line to which the control voltage whose voltage fluctuates is 1=117J0 is connected to the first conductive plate. The influence on the conductive plate can be prevented, and the amount of charge accumulated in the storage capacitor element can be stabilized. (8) According to (7) above, writing and reading operations of the DRAM can be stabilized, and high reliability of the DRAM can be achieved. (9) A semiconductor region of the first conductivity type constituting the capacitance of the memory cell, and a second semiconductor region connected to the MlSl''ET of the memory cell.
Since the semiconductor value ranges of the conductivity type are provided at a distance from each other, the breakdown voltage in the reverse direction of the junction does not deteriorate. (101, the MlSk'
By arranging the ET M', it is possible to eliminate the need for an area for providing the MlSFET. 1) High integration of RAM can be achieved. aυ, by arranging the MISFET above the storage capacitor, the first
The conductivity type semiconductor range and the second conductivity type semiconductor region constituting the Ml 5FET of the memory cell are separated by an insulating film.
Since the capacitors can be spaced apart from each other, the breakdown voltage in the reverse direction of the junction is not deteriorated. (12+, By providing the flsFET on the semiconductor plate, compared to the case where it is provided on the semiconductor substrate, the MIS
Unnecessary parasitic capacitance fI' caused by the pn junction between the 14th cave-shaped semiconductor region of the FET and the second conductivity type semiconductor plate
can be reduced. This makes it possible to reduce unnecessary parasitic capacitance added to the bit line connected to the semiconductor region, thereby making it possible to increase the speed of information writing and reading operations of the DRAM. Q3) By providing the MISFET with a semiconductor plate (JC), the diffusion depth ζ of the semiconductor region of the MISPET can be defined by the thickness of the semiconductor plate, thereby preventing unnecessary diffusion of impurities into the region where the channel is to be formed. death,
It is possible to ensure the effective channel length of M 1 S PET. This can prevent short channel effects. I, embedded in the pores of the first conductive plate of the storage capacitive element, and MISFE on the top of the first conductive plate;
By electrically connecting to the semiconductor region of T, it is possible to reduce the area required for connecting the first conductive plate and the MISFET, thereby making it possible to increase the integration density of the DRAM. Q5i, said (11 to (61, (1G+), (Ill and (141) can significantly reduce the area occupied by the memory cell, and moreover I) it is possible to increase the integration density of the RAM. A synergistic effect can be obtained.The invention made by the present inventor has been specifically explained based on Examples above, but the present invention is not limited to the above Examples, and can be modified without departing from the gist thereof. It goes without saying that various modifications can be made. For example, each of the above embodiments uses a p-type semiconductor substrate to
Although the tAM was constructed, a p-type well region may be provided in a -II type semiconductor substrate, and 1) a RAM memory cell may be constructed within the well region. Further, in each of the above embodiments, the p-type semiconductor region is used as the second conductive plate to accumulate information charges, but an n-type semiconductor substrate is used and the n-type semiconductor region is used as the second conductive plate to store information and charges. accumulate,
You can. Alternatively, an n-type well region may be provided in a p-type semiconductor substrate, and l) a RAM memory cell may be formed within the well region. Further, an ion implantation method may be used as a method for forming the semiconductor region that is the second conductive acid plate. For example, in Example I, ion implantation is performed in the state shown in FIG. 1B1. An impurity such as poron is introduced into the bottom of the pore 4. By subsequent annealing, boron is diffused and a semiconductor region is created at the bottom of the pore 4.
It bubbles up along the sidewalls of the pore toward the substrate surface. Therefore, a semiconductor region is also formed on a part of the side wall of the pore. The semiconductor region along this side wall does not reach the vicinity of the substrate surface (the region where the semiconductor region 8 of the opposite conductivity type is formed). According to this, the capacity of the memory cell will decrease somewhat, but
It is possible to eliminate the need for a mask overlap margin for arranging semiconductor regions 5 and 8 of opposite conductivity types to be spaced apart by t. Therefore, higher integration can be achieved in Examples (1) to (2). Further, in the above embodiments I to V, DRAMs employing a halt pit line method have been described, but an open bit line method may also be employed. In addition, the above embodiments ■ to ■ are DRs that adopt the one-oven bit line method.
Although AMK has been described, a halt pit line method may also be adopted.

[Brief explanation of drawings]

FIG. 1 shows a DRAM for explaining Embodiment 1 of the present invention.
FIG. 2 (2) is an equivalent circuit diagram showing the main part of the memory cell array of 1. FIG. (G) F view taken along the section line 1 and 5 in Figure (5). The third protector and tBl are graphs for explaining the present invention in detail. Figure 4 (2), Figure 5 Figure 6, Figure 7, Figure 8 (4), Figure 9, Figure 10, and Figure 11 are examples of the present invention. FIG. 3 is a plan view of a main part of a DRAM memory cell in a process. Figure 4 (B), 5 Figure 1 (E) Figure 6 (B), Figure 7
Figure 1B1. Figure 7 1B1. Figure 9 (B), Figure 10 (B)
1 and 11 (El is a cross-sectional view taken along the cutting line of the IAI diagram corresponding to each figure number. FIG. 12 (5) is a diagram of a DRAM memory cell for explaining the structure of Embodiment 5 of the present invention. Main part plan view, Fig. 7 1B1
12(5) is a cross-sectional view taken along the line ■-■ in FIG. 12(5). FIG. 13 is a schematic plan view of a main part of a memory cell array for explaining an embodiment of the present invention. The 141st prisoner is a plan view of the main part of L) RAM memory cell for explaining the structure of the embodiment (2) of the present invention, FIG. 14 18+
is a sectional view taken along the tan xtv-xtv cutting line in FIG. FIG. 2 is a plan view of a main part of a DRAM memory cell for explaining the structure of (2). Figure 15 1) 31 is Figure 15 (AJ(1>XV -
16 to 18 are plan views of essential parts of a DRAM memory cell array in each manufacturing process for explaining the manufacturing method of Example V of the present invention. FIG. 19 shows a DRA for explaining embodiment ① of the present invention.
20(5) is a plan view of the main part of a DRAM memory cell for explaining the structure of the embodiment Vl of the present invention, 2nd t)
It(But, Fig. 20(At(7) XX -XX
Cross-sectional view at 9J disconnection, Figure 21, Figure 22 (5), Figure 23 (2), Figure 24
FIG.
Main part plan view, Fig. 21 () Jl, Fig. 22 (B1. Fig. 23 (B),
FIG. 24 1BI and FIG. 24 1BI are Mr. 100 views taken along the cutting line of the opening corresponding to each figure number. FIG. 26 is a schematic plan view of a main part of a memory cell array for explaining embodiment (2) of the present invention; FIG. 27 (4) is a
FIG. 27 is a plan view of a main part of a DRAM memory cell for explaining the structure of the embodiment (2) of the present invention; FIG. Prisoner, Figure 29 (5) and Figure 30 (4) are
Figure 28 (B1. Figure 29 old and Figure 30 (131) is a plan view of the main part of the It AM memory cell in each manufacturing process to explain the manufacturing method of Examples to 11 of the present invention. A cross-sectional view taken along the cutting line of Figure (5) corresponding to each book. Figure 31 is a schematic plan view of a main part of a memory cell array for explaining Embodiment 1 of the present invention. 1) Main part plan view of a RAM memory cell for explaining the structure of 11 of the embodiment (2) of the invention.
It is a sectional view taken along the X[l cutting line. In the figure, 1... semiconductor substrate, 2.2A, 2B... field insulating film, 4... pore, 6.6A, 10. IOA
. 10B, 100, 11. IIA, IIB, 15... Insulating film, 5.5A, 5B... Semiconductor region (second conductive plate), 7, 7A, 7B, 16.16A... Connection hole,
8.14.14A, 14B...Semiconductor region. 9.9A, 90...first conductive plate, 12.12A
... Gate electrode, 13 ... Word line (WL), 17
... Bit line, 17A... Wiring (BL), 1B, 1
8A...Third conductive plate, 20...Semiconductor plate, 9B, 18A, 2OA...Polycrystalline silicon film, 2
2...Channel stopper area-Q=Qt...M
l S FET, O, 0, . . . storage capacitive element. Figure 1 Figure 2 Figure 2 and F3) Figure 4 (A) Figure 4 (B) Figure 5 (AI Figure 5 (B) Figure 6 L/l) Figure 6 (E) Figure j Figure rA) Figure 7 (B) Figure 8 /A) Figure 8 (B) Figure 9 1'ki (A) Figure 9 (B) Figure 10 (AI Figure 10 (B) Figure 11 ( 13) Fig. 14 (B) Fig. 14 (c) Fig. 16 Fig. 17 Fig. 19 Fig. 2 O[4 (!B)] Fig. 27 Fig. 28 (A) (B) Fig. 29 CΔ Figure 30

Claims (1)

[Scope of Claims] l. A pore formed inward from a full surface of a first conductivity type semiconductor substrate, a capacitive element provided using the pore, and a capacitive element provided therein; 16. A semiconductor integrated circuit device comprising a series circuit element constituted by an insulated gate field effect transistor connected in series with the capacitive element, wherein the capacitive element is connected to the entire surface of the semiconductor substrate. A first insulating film is formed to cover the surface of the semiconductor substrate within the pore provided in the pore, one end thereof is electrically connected to the insulated gate field effect transistor, and the other end is electrically connected to the first insulating film. If the first conductive plate provided on the upper part of the insulating film and the first conductive plate provided in the surface area of the semiconductor substrate below the first insulating film are of the same conductivity type as the semiconductor substrate, (has an impurity concentration higher than that of the first conductive plate). and a semiconductor region serving as a second conductive plate, and the insulated gate field effect transistor is disposed above the capacitive element, and the semiconductor integrated circuit device is characterized in that the temperature is set at ℃.2. Semiconductor substrate C) - A pore formed inward from a raw surface portion, a capacitive element provided using the pore, and a capacitive element connected in series with the capacitive element. In a semi-duplex integrated circuit device comprising a series circuit element constituted by an insulated gate field effect transistor, the capacitive element covers the surface of the semiconductor substrate within a pore provided in the whole surface of the semiconductor substrate. a first insulating film formed over the first insulating film, one end of which is electrically connected to the insulated gate field effect transistor, and the other end of the first conductive film provided on the first insulating film; a plate; a second semiconductor region serving as a plate; a second conductive region having a first conductivity type and having an impurity concentration equal to or higher than that of the semiconductor substrate, provided on the main surface of the semiconductor substrate under the first insulating film; a second insulating film provided above the first conductive plate; and a third conductive plate provided at least above the second insulating film, and the insulated gate field effect transistor is disposed above the capacitor. 1. A semiconductor integrated circuit device, characterized in that it is arranged as follows. 3. A pore formed inwardly from the entire surface of the semiconductor substrate of the first conductivity type, a capacitor provided using the pore, and each of the above-mentioned capacitive elements. A series circuit element constituted by an insulated gate field effect transistor connected in series with Plr and a plurality of bit lines extending in the row direction at regular intervals and a predetermined
In a semiconductor integrated circuit device including a plurality of capacitive elements, the capacitive elements are provided on a whole surface of the semiconductor substrate at predetermined intersections with a plurality of word lines extending in the column direction at intervals.
Further, a first insulating film formed to cover the semiconductor substrate in the pore portion, one end thereof is electrically connected to the insulated gate field effect transistor, and the other end or the upper part of the first insulating film is connected to the first insulating film. a first conductive plate provided, and a first conductive type provided on the main surface of the semiconductor substrate below the JP3 film and electrically connected to at least one adjacent other capacitive element; impurity fm higher than that of the semiconductor substrate
and a second half-barrel body σ1 area serving as a second conductive plate having K, and the insulated gate type electric field transistor is disposed above the capacitive element.1. A semiconductor integrated circuit device characterized by c. 4. A pore formed inward from the entire surface of the semiconductor substrate of the first conductivity type, a capacitive element provided using the pore, and A series circuit element constituted by the capacitive element and an insulated gate field effect transistor connected in series is connected to a plurality of bits i extending in the row direction at predetermined intervals and in the column direction at predetermined intervals. In a semi-transparent integrated circuit device comprising a plurality of σ) fill storage capacitance elements, at a predetermined intersection with a plurality of extending word lines σ), a semiconductor substrate in a pore provided in a solid surface of a semiconductor substrate is filled. a first layer formed over the substrate;
an insulating film, one end of which is electrically connected to the insulated gate field effect transistor, and the other end of which is provided on top of the first insulating film, and a first guide plate; The first impurity type, which is provided on the main surface of the semiconductor substrate at the bottom of the film and is electrically connected to at least one adjacent other capacitance, which has a higher impurity content than the semiconductor substrate. a second semiconductor region serving as a second binding plate having thick edges; a second insulating film provided on the top of the first conductive plate; and a third semiconductor region provided on at least ten parts of the second conductive plate.
The capacitor is composed of a plate and a capacitive element. A semiconductor integrated circuit device characterized in that the insulated gate field effect transistors are arranged. 5. Claims characterized in that the accumulation of charge in the capacitive element is performed via the first insulating film in an intervening portion between the first conductive plate and the second semiconductor region serving as the second conductive plate. The semiconductor integrated circuit device according to items 1 and 3. 6. The charge of the capacitive element is accumulated in the first insulating film in the intervening portion between the first conductive plate and the second semiconductor region which becomes the second conductive plate, and in the first conductive plate and the third conductive plate. The second M in the intervening part with! 3. The semiconductor integrated circuit device according to claim 2 and 4, characterized in that the semiconductor integrated circuit device is formed through a green membrane. 7.I11 The insulated gate m-interference field effect transistor. A first Sakai-type semiconductor plate made of single-crystal silicon provided above the capacitive element with an insulating film interposed therebetween is provided with a pair of second conductor plates spaced apart from each other, one of which is used as a source region and a drain region. 5. The semiconductor integrated circuit device jt according to claim 1, wherein the semiconductor integrated circuit device jt is constructed by providing a type of semiconductor region.