JPS60136234A - Tester of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the comprehensive testing efficiency by detecting failures at the earliest possible stage of the testing items by providing a means for changing the order of performance of the testing items arbitrarily. CONSTITUTION:A test summary counter 1 comprising peformance counters 2 (2a-2n) and failure counters 3 (3a-3n) of corresponding number to that of the testing items which count number of performance and that of failures of the test for each testing item is provided. At a certain time, an arbitrary number is preset in a decrement counter 4 and when a decrement becomes 0 at every start of the tests, a CPU5 accesses the contents in the performance counters 2 and the failure counters 3 and a rate of failure of each testing item is calculated. Then, for the tests after that, a testing program in a memory device 6 is amended automatically so as to perform the test from the testing item of a higher rate of falilure in order.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a testing device for semiconductor integrated circuits.

In general, testing of semiconductor integrated circuits (hereinafter referred to as IC) consists of multiple test items, and the order in which these test items are executed is determined when creating the test program.
From now on, this execution order will remain unchanged unless the test program is affected by an earthquake. Normally, when creating an eggplant program, the failure detection rate of each test item is estimated. dll L, is created to be executed in descending order of guest items, but in the case of mass production, the order of the test items may not necessarily be optimal depending on the logs, etc. to be tested, and failures may occur. Since even test items that do not affect the judgment of the IC are executed, the test PA time of the IC under test is often wasted. In the case of special eζ and LSl, the above phenomenon is particularly important because the number of boost items is increasing year by year due to higher integration, higher performance, and higher functionality of ICs under test.

However, an object of the present invention is to detect defects in the IC under test as early as possible at the guest item stage.

According to the test apparatus of the present invention, for a test group of an IC under test consisting of a plurality of test items, the execution order of each of the test items of the test group is arbitrarily arranged at a predetermined frequency. The present invention provides a means for changing the number of defects, thereby making it possible to optimize defect detection.

A detailed description will be given below with reference to the drawings.

FIG. 1 is a flowchart showing the test execution order in a test program that has conventionally been generally performed, and FIG. 2 is an embodiment of the test apparatus of the present invention. According to the example shown in Figure 1, this test program is composed of N boost items, and the execution order is from guest 1 to test 2, test 3, etc. Execute. In order to minimize the time required to detect defects in the IC under test, it is desirable to assign the test items with the highest defect detection rate to Test 1, and the following
+r<, Test 2 should include the dust item with the second highest defect detection rate, and Test 3 should include the guest item with the third highest defect detection rate.

However, the test items that result in these defects are the IC under test.
Since the distribution varies depending on the lot, etc., efficient testing cannot be expected unless the order of execution of each test item is reviewed at appropriate intervals.

In the present invention, for example, an execution counter 2 (28 to 2n
) and a fail counter a (aa~311) for the number of test items, using a test device equipped with a 1st summary counter section 1. ') 5 conducts the test according to the test program written in the machine.At this time, the decrement counter 4 reads '()1.'. At other times, the test will be conducted according to the current 1st Zorogsim dust flow sequence. If the decrement 4 is 110, the CPU accesses the P' contents of the beauty counter 2 and the noil counter 3 for each dust item of the test summary counter section 1, and Counter contents 716 line Counter contents) (]l-Calculate and based on the result, automatically modify the guest program in 6K1ONSOFF16 so that in subsequent tests, the test items will be executed in order starting from the defective rate test item. do.

An arbitrary value is set at the time of entry into the 9th buccrement sword Sonta 4, and after that, every time the test starts, when the decrement llo is reached, the CPU 5 performs a drastic reduction of the defective rate, and the b degree tickment counter 4 All you have to do is reset the value to an arbitrary value and return the above operation line. As described above, according to the test method of the present invention, the defective rate for each guest item constituting the test group of the fiQIc under test is determined based on the test results up to a certain point, and the dust with the high defective rate is determined. Since the test program is automatically corrected and tested so as to be executed sequentially starting from the item, the rate of unnecessary execution of tests that do not result in defects is greatly reduced, and the overall testing efficiency can be improved. In addition, in the above explanation, it was described that the frequency of review is determined by the gain increment counter 4.
For example, it is possible to perform a % line by interrupting every certain time, etc.
Of course it is possible.

[Brief explanation of the drawing]

Figure 1 is a chart showing the order of major lines in a general exam.
FIG. 2 is a block diagram of an embodiment of a testing device for carrying out the testing method according to the present invention. , In the figure, 1...Guest summary counter section, 2a to 2n...Execution counter, 3a
~3n...Fail counter, 4...
5...' central processing unit, 6... storage device. Tsumugi/Zuatsu 2 drawings

Claims (1)

[Claims] A device for testing a semiconductor integrated circuit under test using a test group consisting of a plurality of test items, comprising means for arbitrarily rearranging the execution order of each test item in the test group. Circuit testing equipment.