JPS6013493U - rate measuring device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention;
FIGS. 2A and 2B are diagrams each showing the rate display of the same device. 2...Measurement signal forming circuit, 7...Measurement cycle setting section.

Claims (1)

[Scope of utility model registration request] a reference clock generation circuit that generates a reference clock signal;
A measurement signal forming circuit that outputs a rectangular wave by lowering the source oscillation pulse of the clock under test at a fixed ratio, and a gate circuit that opens and closes at the rise and fall of the rectangular wave to turn on and off the reference clock signal. , a counting circuit that counts the reference clock signal from the gate circuit, a rate indicator that displays the rate of the clock to be measured based on the count contents of the counting circuit, and a rate indicator that can change the frequency division ratio by an external signal. A rate measuring device comprising measurement cycle setting means for counting the reference clock signal via a frequency generator and starting a measurement cycle of the counting circuit every time a predetermined number of counts is counted.