JPS60134566A - Picture quality adjusting circuit - Google Patents

Picture quality adjusting circuit

Info

Publication number
JPS60134566A
JPS60134566A JP24326283A JP24326283A JPS60134566A JP S60134566 A JPS60134566 A JP S60134566A JP 24326283 A JP24326283 A JP 24326283A JP 24326283 A JP24326283 A JP 24326283A JP S60134566 A JPS60134566 A JP S60134566A
Authority
JP
Japan
Prior art keywords
circuit
signal
video signal
input
video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24326283A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kurisaki
一浩 栗崎
Kenichi Hirata
健一 平田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP24326283A priority Critical patent/JPS60134566A/en
Publication of JPS60134566A publication Critical patent/JPS60134566A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE:To attain stabilization of a reproduced picture by inhibiting the supply of a video signal to a high frequency component emphasis circuit during the period of a synchronizing signal of an inputted video signal. CONSTITUTION:The video signal inputted from a terminal 1 is fed to an integration circuit 3 and also to a synchronizing signal separating circuit 8. The circuit 8 separates a synchronizing signal from the inputted video signal. The separated synchronizing signal is fed to one input of a gate circuit 9. The video input signal from the terminal 1 is fed to the other input of the circuit 9 and the output of the circuit 9 is fed to a double differentiation circuit 2. The part of the synchronizing signal in the video input signal is not differentiated double and neither pre-shoot nor overshoot is added thereto. Thus, the video output signal from a terminal 5 forms a stable reproducing pattern not affected by jittering or the like.

Description

【発明の詳細な説明】 [発明の技術分野] この発明は、画質調整回路に関し、特にたとえば磁気記
録再生装置やテレビジョン受像機等における画質調整回
路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an image quality adjustment circuit, and particularly to an image quality adjustment circuit in, for example, a magnetic recording/reproducing device or a television receiver.

[従来技術] 第1図は従来の画質調整回路を示すブロック図である。[Prior art] FIG. 1 is a block diagram showing a conventional image quality adjustment circuit.

図において、入力端子1には、映像信号が与えられる。In the figure, an input terminal 1 is supplied with a video signal.

この映像信号は、2重微分回路2に与えられるとともに
、積分回路3に与えられる。
This video signal is given to a double differentiating circuit 2 and also to an integrating circuit 3.

2重微分回路2の出力と積分回路3の出力とは可変抵抗
器4で合成され、出力端子5から出力される。
The output of the double differentiating circuit 2 and the output of the integrating circuit 3 are combined by a variable resistor 4 and outputted from an output terminal 5.

上述のような構成において、2重微分回路2は、映像信
号の高域成分を強調し、すなわち輝度信号にプリシュー
トとオーバシュートとをかけ画質をシャープにしている
。一方、積分回路3は、映像信号の低域成分を強調し、
これによって画質をソフトにしている。可変抵抗器4は
2重微分回路2の出力と積分回路3の出力との合成比を
適当に選ぶことによって画質をシャープにする度合ある
いはソフトにする度合を決めている。
In the above configuration, the double differentiator circuit 2 emphasizes the high frequency components of the video signal, that is, applies preshoot and overshoot to the luminance signal to sharpen the image quality. On the other hand, the integrating circuit 3 emphasizes the low frequency components of the video signal,
This softens the image quality. The variable resistor 4 determines the degree to which the image quality is sharpened or softened by appropriately selecting the combination ratio of the output of the double differentiating circuit 2 and the output of the integrating circuit 3.

第2図は第1図の入力端子1に入力される画質調整が行
なわれる前の映像信号の波形図である。
FIG. 2 is a waveform diagram of a video signal input to the input terminal 1 of FIG. 1 before image quality adjustment is performed.

第3図は第1図に示す画質調整回路によって画質調整が
行なわれた俵の映像信号の波形図である。
FIG. 3 is a waveform diagram of a video signal of a bale whose image quality has been adjusted by the image quality adjustment circuit shown in FIG.

これら第2図および第3図から理解されるように、第1
図の従来の画質調整回路では、輝度信号7の部分のみな
らず同期信号6の部分も2重微分、積分され、オーバシ
ュートおよびプリシュートが付加されている。そのため
、第1図のような画質調整回路では、再生画面がジッタ
リング等によって不安定になるという欠点があった。
As understood from these Figures 2 and 3, the first
In the conventional image quality adjustment circuit shown in the figure, not only the luminance signal 7 but also the synchronization signal 6 are double differentiated and integrated, and overshoot and preshoot are added. Therefore, the image quality adjustment circuit as shown in FIG. 1 has the disadvantage that the reproduced screen becomes unstable due to jittering and the like.

[発明の概要] この発明は上記のような従来のものの欠点を除去するた
めになされたもので、映像信号の同期信号の期間は高域
成分強調手段に映像信号が入力されないようにし、それ
によって同期信号部分のオーバシュートおよびプリシュ
ートをなくすことを目的としている。
[Summary of the Invention] This invention has been made to eliminate the drawbacks of the conventional ones as described above, and the video signal is not input to the high-frequency component emphasizing means during the period of the synchronization signal of the video signal. The purpose is to eliminate overshoot and preshoot in the synchronization signal portion.

以下、図面に示す実施例とともにこの発明をより具体的
に説明する。
Hereinafter, this invention will be described in more detail with reference to embodiments shown in the drawings.

[発明の実施例] 第4図はこの発明の一実施例を示すブロック図である。[Embodiments of the invention] FIG. 4 is a block diagram showing one embodiment of the present invention.

なお、この実施例は以下の点を除いて第1図の回路と同
様であり、相当する部分には同一の参照番号を付しその
説明を省略する。図において、この実施例では、入力端
子1から入力される映像信号は積分回路3に与えられる
とともに、同期信号分離回路8に与えられる。同期信号
分離回路8は、入力された映像信号の中から同期信号(
水平同期信号および垂直同期信号)を分離する。
This embodiment is similar to the circuit shown in FIG. 1 except for the following points, and corresponding parts are given the same reference numerals and their explanations will be omitted. In the figure, in this embodiment, a video signal input from an input terminal 1 is applied to an integrating circuit 3 and also to a synchronizing signal separation circuit 8. The synchronization signal separation circuit 8 extracts a synchronization signal (
(horizontal sync signal and vertical sync signal).

この分離された同期信号は、ゲート回路9の一方入力に
与えられる。また、入力端子1から入力される映像信号
は、ゲート回路9の他方入力に与えられる。このゲート
回路9の出力は2重微分回路。
This separated synchronization signal is applied to one input of the gate circuit 9. Further, the video signal input from the input terminal 1 is given to the other input of the gate circuit 9. The output of this gate circuit 9 is a double differential circuit.

2に与えられる。given to 2.

上述のような構成において、ゲート回路9は、同期信号
分離回路8から与えられる同期信号の期間は、2重微分
回路2への映像信号の入力を禁止する。それ以外の期間
ゲート回路9は入力端子1から入力された映像信号をそ
のまま2重微分回路2に与える。したがって、入力端子
1から入力された映像信号のうち同期信号の部分は2重
微分されず、出力端子5からは第5図に示すような映像
信号が得られる。この第5図に示すように、同期信号の
部分はプリシュートおよびオーバシュートが付加されて
おらず、従来のように再生画面がジッタリング等により
不安定になることはない。
In the above-described configuration, the gate circuit 9 prohibits the input of the video signal to the double differentiation circuit 2 during the period of the synchronization signal provided from the synchronization signal separation circuit 8. During other periods, the gate circuit 9 supplies the video signal input from the input terminal 1 to the double differentiator circuit 2 as it is. Therefore, the synchronizing signal portion of the video signal input from the input terminal 1 is not double differentiated, and a video signal as shown in FIG. 5 is obtained from the output terminal 5. As shown in FIG. 5, no preshoot or overshoot is added to the synchronization signal portion, and the playback screen does not become unstable due to jittering or the like as in the conventional case.

[発明の効果] 以上のように、この発明によれば、入力された映像信号
のうち同期信号の期間は高域成分強調手段に映像信号を
与えないようにしているので、同期信号の部分はプリシ
ュートおよびオーバシュートが付加されず、再生画面を
安定なものにできる。
[Effects of the Invention] As described above, according to the present invention, the video signal is not applied to the high-frequency component emphasizing means during the synchronization signal period of the input video signal, so that the synchronization signal portion is Preshoot and overshoot are not added, making the playback screen stable.

【図面の簡単な説明】[Brief explanation of drawings]

第1哩は従来の画質調整回路の一例を示すブロック図で
ある。第2図は第1図の入力端子1に入力される映像信
号を示す波形図である。第3図は第1図に示す出力端子
5から出力される映像信号すなわち画質調整が行なわれ
た映像信号を示1波形図である。第4図はこの発明の一
実施例を示すブロック図である。第5図は第4図に示す
出力端子5から出力される映像信号を示す波形図である
。 図において、1は入力端子、2は2重微分回路、3は積
分回路、4は可変抵抗器、5は出力端子、8は同期信号
分離回路、9はゲート回路を示づ。 代理人 大 岩 増 雄
The first diagram is a block diagram showing an example of a conventional image quality adjustment circuit. FIG. 2 is a waveform diagram showing a video signal input to the input terminal 1 of FIG. 1. FIG. 3 is a waveform diagram showing a video signal outputted from the output terminal 5 shown in FIG. 1, that is, a video signal after image quality adjustment. FIG. 4 is a block diagram showing one embodiment of the present invention. FIG. 5 is a waveform diagram showing the video signal output from the output terminal 5 shown in FIG. In the figure, 1 is an input terminal, 2 is a double differentiating circuit, 3 is an integrating circuit, 4 is a variable resistor, 5 is an output terminal, 8 is a synchronizing signal separation circuit, and 9 is a gate circuit. Agent Masuo Oiwa

Claims (3)

【特許請求の範囲】[Claims] (1) 映像信号の画質を調整するための回路であって
、 映像信号を入力する手段、 前記入力手段から入力された映像信号の画質をシャープ
にするためにその高域成分を強調する高域成分強調手段
、 前記入力手段から入力された映像信号の画質をソフトに
するためにその低域成分を強調する低域成分強調手段、
および 前記入力手段から入力された映像信号に含まれる同期信
号の期間前記高域成分強調手段への映像信号入力を禁止
する手段を備える、画質調整回路。
(1) A circuit for adjusting the image quality of a video signal, comprising means for inputting the video signal, and a high-frequency circuit that emphasizes the high-frequency components of the video signal input from the input means in order to sharpen the image quality. component emphasizing means; low-frequency component emphasizing means for emphasizing the low-frequency components of the video signal input from the input means in order to soften the image quality thereof;
and means for prohibiting input of the video signal to the high-frequency component emphasizing means during a period of a synchronization signal included in the video signal input from the input means.
(2) 前記高域成分強調手段は、2重微分回路である
、特許請求の範囲第1項記載の画質調整回路。
(2) The image quality adjustment circuit according to claim 1, wherein the high frequency component emphasizing means is a double differentiation circuit.
(3) 前記低域成分強調手段は、積分回路である、特
許請求の範囲第1項または第2項記載の画質調整回路。
(3) The image quality adjustment circuit according to claim 1 or 2, wherein the low frequency component emphasizing means is an integrating circuit.
JP24326283A 1983-12-21 1983-12-21 Picture quality adjusting circuit Pending JPS60134566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24326283A JPS60134566A (en) 1983-12-21 1983-12-21 Picture quality adjusting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24326283A JPS60134566A (en) 1983-12-21 1983-12-21 Picture quality adjusting circuit

Publications (1)

Publication Number Publication Date
JPS60134566A true JPS60134566A (en) 1985-07-17

Family

ID=17101248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24326283A Pending JPS60134566A (en) 1983-12-21 1983-12-21 Picture quality adjusting circuit

Country Status (1)

Country Link
JP (1) JPS60134566A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6160077A (en) * 1984-08-31 1986-03-27 Nec Home Electronics Ltd Profile correcting device
JPS6293877U (en) * 1985-11-29 1987-06-15
JPS6449482A (en) * 1987-08-20 1989-02-23 Sanyo Electric Co Luminance signal processing circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6160077A (en) * 1984-08-31 1986-03-27 Nec Home Electronics Ltd Profile correcting device
JPS6293877U (en) * 1985-11-29 1987-06-15
JPS6449482A (en) * 1987-08-20 1989-02-23 Sanyo Electric Co Luminance signal processing circuit

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