JPS60132435A - Synchronizing pattern generating method - Google Patents

Abstract

PURPOSE:To obtain the high capacity for detection of a synchronizing pattern by setting a different data word at the position where the same data word is set to obtain a synchronizing pattern. CONSTITUTION:When a data word train containing synchronizing patterns D and D' is supplied to a coder 2, a data word train 9 containing an error is delivered to the reception side of data from a decoder 8 together with a signal 10 showing the presence or absence of an error of the data. While the same data of each channel are transmitted twice and it is avoided that only patterns D and D' arrive at the place where the same data should be received. Therefore the pattern D is detected at the reception side and the different 32-bit data D' is received. At the same time, it is confirmed that the pattern D' contains no error. Then a synchronizing pattern is defined.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronization pattern generation method that can be used for transmitting digital data.

Conventional Structure and Problems In recent years, with the development of digital signal processing technology, audio signals and video signals have come to be digitally processed. Synchronization is much more important in digital signal transmission than in analog signal transmission. Also, in order to increase the reliability of the data, multiple copies of the same data can be used! ! l repeated 9 times υ
, various error detection and correction codes have been used.

A conventional synchronization pattern generation method will be described below with reference to the drawings. Figure 1 is a data structure diagram showing an example of a conventional synchronization pattern used for a two-channel delta word sequence in which the same data word is written twice. Synchronous pattern, Bq-
73+-... and C8, C5... are data words of the B and C channels, respectively, where one word data has a length of 16 bits.

The WJz diagram is a block diagram showing the flow of these data, where ω is a data word string containing a synchronization pattern,
(2) is an encoder, (3) is a modulator, (4) is modulated data, (5) is a transmission path or recording medium, (6) is modulated data containing errors, (7) is a demodulator, ( 9) is a signal indicating the presence or absence of an error 9 in the uqu data, which is a data word string containing an error.

The operation of the data structure including the synchronization pattern configured as described above will be briefly explained below.

The data word sequence having the data structure shown in Fig. 1 is A, A, BO, CO, BO, Co, Bl, c, ,
13. , c I 1 ... cn-1+ Bo,
CH+ B11-Cn, A+A, B1++ l cn+
+ + ...” ' is input to the encoder (2) in the order of 1
A block is formed, and two two-word synchronization patterns appear consecutively in the first four words of the block.

Each channel data is arranged so that the same data is repeated twice. A data word sequence (1) containing a synchronization pattern inputted to the encoder (2) is added with a special code for error detection and correction, and inputted to the variable θ·'j unit (3). The modulator (3) modulates the data into a form suitable for transmission7.
The inspection data (4) is then sent to the transmission path (5). The transmission path (5) may be a variety of recording media, such as an optical disc, a magnetic disc, a magnetic tape, etc. These transmission paths cause errors in the modulated data (4), and the modulated data (6) containing errors is input to the demodulator (7). The output from the demodulator (7) is input to the decoder (8), where errors are detected and corrected using an error detection and correction code and output as a data word string (9). However, if a large burst error that cannot be corrected by the decoder (8) occurs on the transmission line (5), erroneous data is output to the data word string (9). The side receiving the data word string (9) containing this error uses the nature of the data string that the same data is repeated twice on the same channel and the signal 4 that indicates the presence or absence of data errors. can decode the correct data word sequence. However, if a data error p occurs in both locations where the same data should come, it cannot be corrected.

However, in the above configuration, the same pattern may also appear in the two 32-bit data words of Bm and Crn (m=0.1.2...); It is necessary to ensure that the 32-bit pattern is not the same as the sync pattern.
The 16-bit data of the CfJr channel had the disadvantage that it could not handle all types of data. Also B
, 216 of all 16-bit patterns on the C channel.
If the synchronization pattern is allowed to pass, the 32-bit synchronization pattern is increased to 64 bits or 96 bits to make one block 4X(n+3), 4X(n+4) words in order to reduce the probability that the same pattern will appear. Such measures were necessary.

OBJECTS OF THE INVENTION The purpose of the synchronous pattern generation method of the present invention is to provide a synchronous pattern generation method with very high ability to detect synchronous turns. In the synchronization pattern generation method of the present invention, the same data word appears in a data string arranged so that the same data word is repeated two or more times on the same channel within a data word string of one or more channels. The synchronization pattern is created by placing different data words at the correct positions, and this creates a black mark that significantly increases the ability to detect synchronization patterns within the data word string.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a data structure diagram in an embodiment in which the present invention is applied to a 2-channel data word string in which the same data is written by repeating the same data twice, and D is a 32-bit synchronization pattern; D' is a 32-bit synchronization pattern different from D, BOIBll... and C8, C4.
, . . . are data words of the B and Cf-yannels, respectively, where one word of data has a length of 16 bits.

The operation of the data structure including the synchronization pattern configured in this manner will be discussed below. The data word sequence with the data structure shown in Figure 3 is D+D' IBOIcO.
IBO+C(1, Bl+ C4+B ,+C,,-...
Cn-HIBO* CH+ Bn+Cn+D +D'
IBn+ +cn+2. ... is input to the encoder (2) shown in Figure 2 in this order. Following the route shown in the conventional example below, the erroneous code is sent from the decoder (8) to the data receiving side. Containing data word string (9)
Then, a signal OI indicating the presence or absence of data errors is output.

Further, the same data is sent twice for each channel data, and only the synchronization patterns D and D' are configured so that the same data does not appear in the place where the same data should come. Therefore, on the receiving side, it becomes possible to detect a synchronization pattern by utilizing this property. Finally, on the receiving side, the pattern D is detected, and then the 32-bit data D'
The synchronization pattern can be determined by confirming that D is different from D and that there is no error in D'. In addition, if the same pattern as D occurs in the 32 bits of data words Bm, Cm (m=0.1121-), the conventional method would mistake it for a synchronous pattern, but in this embodiment, the next Since the 32 bits are the same as the 32 bits of Bm and Cm, there is no misidentification.Also, an error occurs in the 32 bit data that should be the same as the next BmlCln, and B(
Even if it differs from the 32-bit data of 11+ Cm,
Using the signal a0 indicating the presence or absence of an error, it can be determined that the pattern is not a synchronous pattern. Note that in the above embodiment, the only condition was that D' be different from D, but D' may also be a fixed pattern as a 32-bit pattern, and in the above embodiment, the bit length of synchronization pattern D is Although the length is set to 32 bits, other lengths may be used as long as the condition that different data words come in the place where the same data word should come is satisfied. For example, in the case of 1 word data of 16 bits as in the above embodiment, the synchronization pattern D may be an integral multiple of 16 bits. Furthermore, in the above embodiment, the number of channels 1V is 24 and the number of repetitions is 2. However, if different data words are placed in the position where the same data word should come, the number of channels can be reduced to 4. Any number of channels may be used, and the number of data repetitions may be any number of times as long as it is 2 or more times.

Effects of the Invention As is clear from the above description, the present invention has the advantage of applying the same data word to a data string arranged in such a way that the same data word is repeated two or more times on the same channel within a data word string of one or more channels. Since the synchronization pattern is created by placing a different data word in the position where the code should come, even if the same pattern as the synchronization pattern occurs in a data word other than the synchronization pattern, it may be mistaken as a synchronization pattern.4 The excellent effect of having no turn is obtained. Furthermore, by using this synchronization pattern generation method for data word strings that can detect false ps on a word-by-word basis, even if an error occurs in the data word string, a high synchronization pattern detection ability can be obtained. is obtained.

[Brief explanation of the drawing]

Figure 1 is a data structure diagram showing an example of a conventional synchronization pattern used for a two-channel data word 1.' column in which the same data is written twice, and Figure 2 is a data flow diagram. The block diagram showing the $3 diagram shows that the same data is
FIG. 2 is a data structure diagram in an embodiment of the present invention in which the present invention is applied to a two-channel data word string written repeatedly. ■)...32-bit length synchronization pattern, (D)'...
・A 32-bit synchronization pattern with a different bit pattern from D, (1)...Data word string containing the synchronization pattern, (9)...@,! l) A data word string containing k, (10... signal agent indicating the presence or absence of data errors) Yoshihiro Hayashimoto

Claims (1)

[Claims] 1. In a data word string of one or more channels, in a data word string arranged so that the same data word is repeated two or more times on the same channel, a different data word is placed in the position where the same data word should appear. A synchronization pattern generation method that generates a synchronization pattern so that 2. The synchronization pattern generation method according to claim 1, wherein false detection of data words in a data word string of one or more channels can be performed word by word.