JPS60154371A - Error detecting system of digital signal - Google Patents

Abstract

PURPOSE:To make the number of erroneous words approximate to the real number of them and to enhance error correcting ability by utilizing a tape format in which erroneous words are detected not only in the row direction of a frame but also in the column direction. CONSTITUTION:A synchronizing signal S, about five information words [W0,0- W0,5]-[W13,0-W13,5], parity words P0-P5 and Q0-Q5 are arrayed and recorded in a matrix, and the 1st error detecting words C0-C16 are recorded at the end in the row direction and the 2nd error detecting words C0' and C5' are recorded at the end in the column direction, respectively, thereby forming a tape format of one frame. These words C0-C16 detect errors in the row direction and if there is even one erroneous word, words in its frame in the row direction are considered to be wrong and a pointer is set up. In the same manner a pointer in the column direction is set up, and if both pointers are set up for one word, it is decided to be wrong, the number of erroneous words is detected by approaching the actual one, and error correcting ability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital signal error detection method, and particularly to a method with improved detection capability.

[Technical background of the invention and its problems]

Recently, in the field of audio equipment, a PCM recording and reproducing device, which is a type of digital signal transmission system, has been developed.

The so-called compact cassette (
When using a magnetic head, it is becoming mainstream to use a multi-track fixed head.

By the way, the problem with systems that record and reproduce (generally transmit) digital signals such as PCM signals is as follows.
An error occurs due to a dropout in the recording medium (generally the transmission path), and playback (generally the transmission)
This means that errors will be mixed into the resulting signal.

For this reason, when recording a digital signal, an error detection word and an error correction (parity) word are generated and recorded together with the original information word, and during playback, errors in the information word are detected based on the error detection word, and then the error is detected. It is common practice to employ an error detection and correction method in which errors are corrected based on error correction words.

FIG. 1 shows a conventional tape format using a multi-track fixed head PCM recording/reproducing apparatus employing such an error detection and correction method, and shows a case where the number of tracks is 16.

Here, each of the tracks 1 to 16 of the magnetic chip 70T is provided with a head via an encoder (not shown), etc., as shown in the drawing.
Word information word (Wo + OpWo p 1-Wo
w ) + (W++ On WIx.

”°Wll g) ”' (Wts to + Wa
s mlo"Wta+s) or A retei word (Po
-Pt -Ps :) (Qo.

Ql...Qll] are arranged and recorded in a matrix format, and an error detection word (CO.

C1...C1,] are recorded.

When reproducing the encoded signal recorded in such a form and applying it to a decoder (not shown), each valley frame in the row direction from the synchronization signal S to the error detection word C1 (however, l-θ to 15) is 1 in each frame by checking with the error detection word described above.
If there is an error in a word, all words in that frame are considered to be errors, and the error pointer corresponding to each word in the frame is set in the error pointer prepared in one-to-one correspondence with the valley word. Stand everything up.

FIG. 2 shows a state in which such a Niji pointer is set up, and the information word (W+, s) in FIG. 1 is shown.

The case where there is an error in (W4.I), (W?, 3), and (Wi2, 6) is taken as an example. 1 Here, the word position indicates a word position where an error occurred, and the number 2 indicates a word position that was considered to be an error even though it was not actually an error.

In addition, Q and x attached next to each error detection word C1 (l#0 to 15) indicate whether there is an error in that frame (x) or not (0 is used for reference). It is something that

Next, to explain the principle of error detection in the above,
When an n-bit CRC code is assumed as the error detection word, error detection is realized by determining the syndrome of the CRC sequence.

Now, we have 6 information words W, 6 parity words P, and 6 each.
In the example shown in Figure 4, the bit is the information bit of one frame.) In the example shown in Figure 4, the bit is 6-n bits and is expressed by the following polynomial (however, i, , = θ ~ 13 times Mr).

Wi=wI, iX"-'-1-w2.iX'-)-
...-1-w6n, IP = Pt X6n-' +
PtX + - 10p6nQ = qt X + (1!X
+・”+q@, n1: Further, regarding the error detection word C, the following relationship holds true.

Ci =x -Wi +R1-G C14=
s Gn-5G= 10 g+"! +... Represented in 10 gn.

Also, Ri, R84, R, are each □□1 It is expressed as

Then, from each word with the above structure, C
The syndrome is determined by the RC code and the reproduced data of the information word or the quality word which is the CRC generation element, and an error is detected in a frame in which the cough syndrome value is not OK.

In other words, each syndrome is Ei, EI41E11+
Then, Wi +Ci = Ri -G+Ei P + Cl4-RI4.G+E.

In the equations Q0Cll1=RII-G1EI5, the syndromes Et, E, 4. E, Il is 0
If it is O, there is no error, and if it is O, there is an error. Then, during subsequent error correction, the state of the above-mentioned step 2 pointer is used as a deciding factor to determine whether or not error correction of the error correction series consisting of parity words and information words is possible or not. This means that there are many cases where it is determined that the error cannot be corrected even though it is possible to correct the error.

FIG. 3 shows an example of the above case. In this example, the error correction sequence A is 1! It consists of a retention word P and three information words W, and in principle, it is possible to correct up to one word error in the error correction series A, but if there is an error of two or more words, it is determined that it is uncorrectable and correction is performed. This is the case where there is no.

Here, if an actual error occurs in the two words indicated by the error of the information word WA, then in the error detection series B, all the words in the frame containing the error word are considered to be errors. Therefore, if only the perfect error word was detected at the time of correction, it would have been possible to correct it, but it is considered that there are two or more words of error in the error correction series A, and it is judged as uncorrectable. This is something that will end up happening.

In other words, in conventional error detection methods, if there is an error in even one word in one frame, all words in that frame are considered to be errors, and the error detection ability is poor, so This has resulted in a serious problem in that the number of erroneous words during correction is determined to be greater than the actual number of erroneous words, which in turn impairs the error correction ability.

'''3・! On='j ji!! )"-y"-,>
p″!−j;’&?#f).

The explanation has been given using the example of a tape format when recording and reproducing information on a magnetic tape using a fixed rack head, but the problem is not limited to this, but can similarly occur when serially recording and reproducing information on a magnetic tape using a rotating head. .

Figure 4 shows an example of a tape format applied to the latter case, in which each word is arranged as shown using a buffer memory. That is, S in the figure is a synchronization signal,
A is q! in buffer memory. r7 frame address, P
, Q is a parity word, W is a clearing word, and C is an error detection word in the frame direction (column direction).

One frame is composed of P, Q, and seven Ws.

FIG. 5 shows the state of the error pointer corresponding to the word in FIG. 4, which is (W2.1) in this figure.

In the case where there is an actual error in the 3 words (mouth) of (Wo, 4) and (ws, y), as a result of the error detection described above, all words (2 parts) of the frame containing that word are Indicates a condition that is considered to be incorrect.

[Purpose of the invention]

Therefore, this invention was developed in view of the above points, and it improves the error detection ability so that the number of erroneous words can be detected as close as possible to the actual number of erroneous words. It is an object of the present invention to provide an extremely good error detection method for digital signals that has been improved so as not to impair the error correction ability during error correction.

[Summary of the invention]

That is, the digital signal error detection method according to the present invention includes a first means for arranging information words and /4'retention words constituting an error-detected digital signal during processing/coding in a matrix format, and the above-mentioned information words and/or matrix. the first row or column direction of the priority word.
and q-th means for adding a second error detection word in the column or row direction of the information word and the parity word; A fourth means for detecting a certain row or column and setting an error pointer in all the words constituting the row or column containing the error, and detecting a column or row without an error using the second error detection word and detecting the error-free column or row. It is characterized by comprising a fifth means for defeating the error pointers of all words constituting an error-free column or row.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to the drawings.

That is, FIG. 6 shows the tape format of the present invention using a multi-track fixed head PCM recording/reproducing apparatus which employs an error detection method as described later, and shows the case where the number of tracks is 17.

Here, each track 1 to 17 of the magnetic tape T is provided with five information words (We, . . . + Wo+ 1 ++・W
,,) e (WI+Ojwl# s...Wr-s'
)...CW,s +O5Wss *t...Was,
s) or parity □ word (Po', Pl...P,
].

(Qo=Qt...Qll) are arranged and recorded in a matrix format, and the first error detection word (Co, C't...C1°) is recorded at the end of the row direction, and further A second error detection word (C'
. , C1...C',) are recorded.

In other words, in the tape format according to the present invention, error detection words (CO, CI...
In addition to this, error detection words (C10, C'!...c's) are recorded in a direction perpendicular to the frame direction (hereinafter referred to as column direction). .

Then, when reproducing the encoded signal recorded in the above format and applying it to a decoder (not shown), etc., the first error detection word ct (where i=0
By checking each frame in the row direction up to 16) using the error detection word 1- in the row direction,
If there is even one word error in each frame, all words in that frame are considered to be errors, and each word in the frame is placed in an error pointer prepared in one-to-one correspondence with the warning word. Set all corresponding error pointers.

Next, the second error detection word CI in the column direction (where 1-=
0 to 5) to check whether there is an error in each column.

Through this check, if there is an error in each column, nothing is done, but if there is no error, all words in that column are determined to be correct and are placed in the valley word of that column. Kill all error pointers.

FIG. 7 shows the state in which such an error pointer is set up and put down.
The information word J that is considered to be an error is an information word that is determined not to be an error as a result of checking with the error detection word in the column direction in the above z, and thereby overturns the error pointer that had been set up until then.

Note that o and × attached to the first error detection word C in the row direction and the second error detection word C' in the column direction indicate the row (
frame) and whether there is an error in the column (×) or not (
2) is shown for reference.

In other words, according to such an error detection method, words that are considered to be errors even though they are not errors are left as they are and subjected to correction, whereas words that are considered to be errors even though they are not errors are corrected. Since the word is subjected to correction in a significantly modified state, it is possible to improve the error detection ability without impairing the error correction ability. ! ishi.

It should be noted that the principle of error detection itself is the same as in the conventional case described above, so its explanation will be omitted.

The above explanation also describes the process of recording and reproducing digital signals on magnetic tape using a multi-track fixed head.
Although formatting has been taken as an example, even when serially recording and reproducing on a magnetic tape using a rotary head, the error detection method according to the invention described above can be simplified by using a panzer memory and arranging it as shown in FIG. It can be applied with the same purpose.

That is, in the diagram @8, S is a synchronization signal, A is the address of each frame in the panzer memory, and P, Q
is a /J retention word, W is an information word, and C is an error detection word in the frame direction (column direction).
, P, Q, and 7 words of W constitute one frame.

Then, C' is an error detection word for 10 words in the row direction that crosses the % frame, and C10 is Ao =Ao
, C1' corresponds to Pop~pe, C/ corresponds to Qo~Q, and C1 (where l=θ~6) corresponds to Wlo
-Wls (however, l=0 to 6).

FIG. 9 shows the state of the error pointer corresponding to each word in FIG. 8. In this figure, as in the case of FIG.
In the case where there is an actual error in three words (part) of y), first, the first error detection word in the column direction detects c,
, C4, all the constituent words (2 parts) of the frame 'c' are considered to be errors and an error pointer is set, but next, check with the second error detection word C' in the row direction. This shows a state in which the error pointer (national capital) of a word with no actual error is moved down in each row direction.

Note that the first and second error detection words c and c' may be interchanged in the row and column directions, if necessary.

Next, a specific example of a multi-track fixed head PCM recording and reproducing apparatus that employs the error detection method according to the present invention as described above will be described.

Figure 10 shows the configuration of the recording system. The audio digital word signal supplied to input terminal 1 is converted into 14 (D/4' parallel channel information words (Wo - W Is) by multiplex 2). in a distributed state,
Encoder JIC is input.

Figure 11 shows the internal configuration of the encoder/3 mentioned above.
The above-mentioned 14 information words W0 to WI8 are input to the input terminal 14.
The first exclusive OR circuit 15 via a to 14n
and is input to and used for generating p/4 lity.
Together with the P parity word generated here, it is input to the first delay circuit 16 and a predetermined delay (0.beta., .1.beta.. . . 14.beta.
8 words) is applied.

Next, the outputs of the 14 information words and the P value word from the first delay circuit 16 are input to the exclusive OR circuit 17 and used for generating the Q quality. Together with the generated Q parity word, it is supplied to the second delay circuit 18 with different predetermined delays (0·α.

1.α...15α, where α is, for example, 24 words).

Then, each output of the information word, P parity word, and Q'' parity word from the second delay circuit 18 is made into one channel via the demultiplexer 19, and the second error detection word C' is generated. CRC used for
The signal is supplied to the C generation circuit 20.

FIG. 12 shows the internal configuration of the CRCC generation circuit 20. In this figure, the generator polynomial 〇'(xl =X''+
The circuit configuration is such that the input signal is divided by X"+X"+1.

The S terminal 38 of this CRCC generation circuit 20 is connected to the C
It is generated by the RCC control circuit 21, and is 111 and C during the destruction data (16 words in this case) period.
A control signal that becomes I□t is supplied during the RCC data period.

Similarly, when it is desired to sequentially output both destruction data and CRCC data from the CRCC generation circuit 20 to the z terminal 39, 111 and CRCC'fh- are input.
If it is desired to output only evening light, a control signal of 10" is supplied.

Then, each word of the output of the demultiplexer 19 supplied to the input terminal 37 at z=O is converted into a serial signal by the 4 parallel serial converter 41, and then passed through the exclusive OR circuit 43 and the AND circuit 48. and passes through the fritz 70 tube circuits 35a, 35b, . . . 35p in sequence.

As a result, when the CRCC data is output from the output terminal Q of the last stage flip-flop circuit 35p and the dart of the AND circuit 44 is opened by the control signal supplied to the S terminal 38, By being supplied to the serial-to-master converter 40 via the OR circuit 45, the signal is converted into a /clarel signal and is output from the output terminal 42.

The CRCC data derived from the output terminal 42 of the CRCC generation circuit 20 is supplied to the CRCC generation circuit 22qIC in FIG.

Further, in FIG. 11, the valley outputs from the second delay circuit 17 are supplied to CRCC generation circuits 22h to 22p, respectively.

Here, cicc generation circuit 22h ~ 22p and 22
q is constructed in the same way as the CRCC generation circuit 20 shown in FIG. 11 and CR during the period
A control signal that becomes eOl is input during the CC data period.

The outputs from the CRCC generation circuits 22a to 22p and 22q are output to output terminals 23a to 23p and 23
q to the modulation units 4a to 4p and 4q in FIG.
~Multi-track recording head 6 via 5p and 5q
It is output to a to 6p and 6q.

As a result, the information is recorded on a magnetic tape (not shown) in the tape format shown in FIG.

FIG. 13 shows a reproduction system, in which signals reproduced by multi-tractor reproduction heads 7a to 7p and 7q are demodulated via reproduction amplifiers 88 to 8p and 8q, respectively, and supplied to sections 9a to 9p> and 9q. By doing so, MFM
After demodulation, the synchronizing signal S is separated into frames and input to the decoder 11.

FIG. 14 shows the internal configuration of the decoder 1).
Each signal input to input terminals 24ts to 24p and 24q is supplied to CRCC detection circuits 25h to 25p and 25q.

Here, each CRCC detection circuit 25a to 25p and 25
The internal configuration of q is the CRCC generation circuit 20 shown in FIG.
However, in this case, the negative data passes through all of the 7 lip-flop circuits 35a to 35p, and the CRCC data passes through the 7 lip-flop circuits 35 to 35p. The output of the valley flip-flop circuits 35&~35p at the time of input is applied to the AND circuit 36, and by setting the switch 52 to the b contact side, the output of the AND circuit 36 is applied to the AND circuit 36 via the inverter 51. Said S terminal 38
With the control and roll signals from the AND circuit 5o, r
- is outputted from the output terminal 37' as a detection result signal.

Here, the output □ from the CRCC detection circuits 25a to 25p is the cancellation data and the detection result signal from the output terminals 42 and 37', and the output from the CRCC detection circuit 25q is the cancellation data from the output terminal 42.

The deletion data outputs from the CRCC detection circuits 25a to 25p are input to the demultiplexer 27 and are also supplied to shift registers 25h to 25p correspondingly.

Here, the demultiplexer 27 has upper 6 pins 25a to 25p.
1? of each word of the cancellation data from C and the cancellation data C' from the CRCC detection circuit 25q. parallel input to 17
It is converted into a word serial word output and supplied to the CRCC detection circuit 28.

The CRCC detection circuit 28 has the same configuration as the CRCC detection circuits 25a to 25p, and detects the same CRCC from the 17 serial words.
Detection is performed and the detection result signal (which becomes the error pointer) is outputted from the output terminal 37'.

In this case, the CRCC detection circuits 25a to 25p, 25q, and 28 are also the same as the CRCC control circuit 2.
The necessary control signals are supplied by a CRCC control circuit 60 similar to that shown in FIG.
It is assumed that this is done on the contact side.

In addition, the detection result signal from the CRCC detection circuit 28 (
1 pit) is input to the shift registers 29a-29p in parallel with each output word from the CRCC detection circuits 25a-25p.

In the CRCC detection circuits 25a to 25p, the CRCC data is input and detected every time the deletion data passes through 8 words, and if the detection result signal is "1", the corresponding channel Set the error pointer bits of shift registers 29a to 29p corresponding to 8 to 8.
Set all widths to °0".

Next, outputs from the shift registers 29a to 29p, each consisting of an information word, a parity word, and an error pointer, are supplied to a third delay circuit 30, where each channel has a different delay (0, α, 1, α...1
5α) is input to the Q decoder 31.

This Q decoder 31 applies an exclusive OR circuit to the 14 information words, the P parity word, and the Q/4' parity word, and if the result is not 101, then each information word, P/4' parity word, and Q If the number of error pointers in the end word that is at 11° is 1, set the value of the result other than 101 in the word whose error pointer is at 111, otherwise do nothing. Second delay circuit 32:
Each channel has a different delay (1·β).

2.β...15β) is inputted to the P decoder 33.

This P decoder 33 applies an exclusive OR circuit to the 14 information words and the P parity word, and when the result is not 101 and the number with which the error pointer of each word is 111 is 1, The value of the result other than "o1" is set in the word whose error pointer is lII, and in other cases, only information data is led out to the output terminals 348-34H without doing anything.

And the output from the P decoder 33 is! The signal is input to the demultiplexer 12 as the output of the decoder 1 shown in FIG. 13, where it is converted into a serial word and output from the output terminal 13 as a reproduced blade.

As a result of the above, words that are considered to be erroneous than those described above are subjected to correction in a significantly modified state, which improves error detection ability and does not impair error correction ability. A multi-track fixed head PCM employing the error detection method according to this invention.
This makes it possible to realize a recording/reproducing device.

It goes without saying that the present invention is not limited to the embodiments described above and illustrated, and that various modifications and applications can be made without departing from the gist of the invention.

〔Effect of the invention〕

Therefore, as described in detail above, according to the present invention, the error detection ability is improved so that the number of error words can be detected as close as possible to the actual number of error words. It becomes possible to provide an extremely improved digital signal error detection method that does not impair the correction ability.

[Brief Description of the Drawings] Figure 1 is a diagram showing a tape format using a conventional error detection method when digital signals are recorded and played back on a magnetic tape using a multi-track fixed head, and Figure 2 shows the error in Figure 1. Figure 3 is a diagram showing the error pointer status to explain the detection method. Figure 3 is a diagram showing the error correction sequence according to Figure 2. Figure 4 is a diagram showing digital signals recorded and reproduced on magnetic tape using a rotating head. 5 is a diagram showing an error pointer state for explaining the error detection method of FIG. 4, and FIG. 6 is a diagram showing a tape format according to the conventional error detection method when A diagram showing a tape format when a digital signal is recorded and reproduced on a magnetic tape using a multi-track fixed head as an example of the detection method, and FIG. 7 is for explaining the error detection method shown in FIG. 6. FIG. 8 is a diagram showing a tape format when a digital signal is recorded and reproduced on a magnetic tape using a rotary head as another embodiment of the present invention.
FIG. 9 is a diagram showing error pointer states for explaining the error detection method of FIG. It is an internal configuration diagram of each part. T...Magnetic tape, S...Synchronization signal, W...Information word, P, Q...Mother stay word, C...Error detection word in the row direction (first), C'.・Column direction (second
) error detection word, 3...encoder, 4... decoder.

Claims (1)

[Claims] A first means for arranging information words and error detection words constituting an error-detected digital signal during encoding in a matrix format, and a first means for adding a first error detection word in the row or column direction of the information words and i4 error detection words. 2 and a second means with respect to the column or row direction of said information word and parity word.
a third means for adding an error detection word, and detecting an erroneous row or column using the first error detection word during decoding and setting an error pointer to all words constituting the erroneous row or column; and a fifth means for detecting an error-free column or row using the second error detection word and defeating the error pointers of all words constituting the error-free column or row. An error detection method for digital signals characterized by the following.