JPS60130987A - Noise reduction circuit - Google Patents

Abstract

PURPOSE:To reduce noise in a reproduced video signal by detecting the timewise position of noise near the leading and trailing edge of the reproduced video signal to change the frequency chracteristic near the leading and trailing edge of the reproduced video signal. CONSTITUTION:An input terminal 16 is connected to a de-emphasis circuit 17 and connected to a summing input terminal of a subtraction circuit 18. An output terminal of the subtraction circuit 18 is connected to a control input terminal of a sharpness control circuit 22 via an absolute value circuit 19, a clip circuit 20 and a delay circuit 21 connected in series. Moreover, the de-emphasis circuit 17, the subtraction circuit 18, the absolute value circuit 19 and the clip circuit 20 constitute a detection circuit. The de-emphasis circuit 17 is connected to a difference input terminal of the subtraction circuit 18 and also connected to a signal input terminal of the sharpness control circuit 22. An output where the high frequency component of the reproduced video signal near the leading and trailing edge of the reproduced video signal is attenuated is obtained from an output terminal 23 of the circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a noise (Ilt sound) reduction circuit, and particularly to a noise reduction circuit used in a magnetic recording/reproducing device or the like.

(Prior Art) FIG. 1 is a block diagram showing an example of a conventional noise reduction circuit using line correlation.

In Fig. 1, 1 is an input terminal, 2 is an FM demodulator, 3 is a low-pass filter (hereinafter referred to as LPF), 4 is a delay circuit, 5 is an F'M demodulator, '6 is LP'F, and '7 is Subtraction times □
8 is a limit circuit, 9 is a subtraction circuit, and 10 is an output terminal.

Input terminal 1 is FM1! [Connected to LPF3 via device 2.] In addition, the input terminal 1 is connected to a subtraction circuit 7 via a delay circuit 4, an FM converter 11g1 unit 5, and an LPF 6 which are connected in series.
is connected to the difference input terminal. The output terminal of the subtraction circuit 7 is connected to the limit circuit 8, and the limit circuit 8 is connected to the subtraction circuit 9.
Connected to the difference input terminal □.

Further, the LPF 3 is connected to the phase input terminal of the subtraction circuit 7 and also to the phase input terminal of the subtraction circuit 9. The output terminal of the subtraction circuit 9 is connected to an output terminal 10.

Input terminal 1 receives the reproduction FMllll! from the previous stage circuit (not shown in FIG. 1). Image signal is supplied. This reproduced FM video signal is supplied to the FMI modulator 2, FM demodulated by the FM demodulator 2, and output as a reproduced video signal L P F 3
The carrier frequency component is removed by LPF3.

Furthermore, the reproduced FM video signal supplied to the input terminal 1 is also supplied to the delay circuit 4, where it is delayed by one horizontal synchronization period (hereinafter simply referred to as H), and is output as a delayed reproduced FM video signal to the FMSM modulator. 5. Delayed playback FMI! Ii
The image signal is FM demodulated by an FM demodulator 5, and is supplied as a delayed reproduction video signal to an LPF 6, where the carrier frequency component is removed.

The operation of the conventional noise reduction circuit shown in FIG. 1 will be explained below with reference to FIGS. 2 and 3.

FIG. 2 is a diagram for explaining the operation of the conventional noise reduction circuit, and FIG. 3 is a diagram for explaining the operation of the conventional noise reduction circuit.

Playback FMIII input to input terminal 1! If the image signal is a signal with line correlation, the subtraction circuit 7
A reproduced video signal on which the noise component shown in FIG. 2 (A>) from PF3 is superimposed, and a reproduced video signal on which the noise component shown in FIG. 2(B) from LPF 6 is superimposed are supplied. Therefore, the subtraction circuit 7 outputs a signal containing only the noise component shown in Fig. 2 (C), which is a signal obtained by subtracting the signal shown in Fig. 2 (13) from the signal shown in Fig. 2 (△). be done.

Further, the subtraction circuit 9 receives the reproduced video signal on which the noise component shown in FIG. ), the subtraction circuit 9 outputs a second signal, which is the signal shown in FIG. 2(C) subtracted from the signal shown in FIG. 2(A). The signal shown in FIG.

Furthermore, if the reproduced FM video signal input to the input terminal 1 is a signal that does not have line correlation, the reproduced video signal output from the LPF 3 becomes the signal shown in FIG. 3 (A>), and is output from the LPF 6. The delayed playback video signal is shown in Figure 3 (
The signal shown in B) will be obtained.

Therefore, the subtraction circuit 7 receives the signal shown in FIG. 3(A),
Since the signal shown in FIG. 3(B) is supplied, the subtraction circuit 7 converts the signal shown in FIG. 3(A>) into the signal shown in FIG. 3(B).
The signal shown in FIG. 3(C), which is the signal obtained by subtracting the signal shown in FIG. 3, is output.

The signal shown in FIG. 3(C) is the output signal of the subtraction circuit 7 when the above-mentioned reproduced FM video signal having line correlation is supplied to the input terminal 1. It is different from the signal. Specifically, the signal shown in FIG. 2(C) is a signal containing only noise components, whereas the signal shown in FIG.
The signal shown in Figure <C) is a signal containing signal components.

Therefore, the subtraction circuit 9 receives the signal shown in FIG.
When the signal shown in FIG. 3(C) is supplied, the subtraction circuit 9 outputs the signal shown in FIG. 3(A) minus the signal shown in FIG. 3(C). A signal as shown in Fig. 3(D) is output.The signal shown in Fig. 3(D) is different from the signal shown in Fig. 3(A).Specifically, the rising edge and The phenomenon of worsening of falling edges and increase of noise occurs.

Therefore, as shown in FIG. 1, a limit circuit 8 is inserted between the output terminal of the subtraction circuit 7 and the input terminal of the subtraction circuit 9. 9, the signal output from the output terminal 10 is prevented from becoming like the signal shown in FIG. 3(D).

That is, during a period in which the reproduced video signal supplied to the input terminal 1 has line correlation from the output terminal 10, a reproduced video signal with reduced noise is output from the output terminal 10.

However, the period when there is no line correlation (subtraction circuit 7
During the period in which signal 0, which has a large amplitude among the output signals and exceeds the lower level of the limit circuit 8, is output from the subtraction circuit 7), a reproduced video signal with no noise reduction is output from the output terminal 1O. .

Furthermore, the reason why the signal output from the subtraction circuit 7 becomes the signal shown in FIG. 3(C) is because the reproduction F M i! I! Not only when the 1m signal has line correlation and is not good, but also when the reproduced FM video signal contains jitter components and there is an error in the temporal position of the rising and falling edges of the signal waveform. ,
Even if the delay time of the delay circuit 4 is not exactly one day, a signal like the one shown in FIG.
By inserting the b-limit circuit 8 between the subtraction circuit 7 and the reduction/exemption circuit 9, the edges of the reproduced video signal are prevented from deteriorating.

However, as mentioned above, the signal input to input terminal 1 does not have line correlation or the reproduced FM video signal contains jitter components, resulting in errors in the temporal positions of the rising and falling edges of the signal waveform. If the delay time of the delay circuit 4 is not exactly one day, etc., the limit circuit 8 is activated. Therefore, it is conceivable to reduce the noise by arranging a circuit as shown in FIG. 4 as a downstream circuit of the noise reduction circuit shown in FIG. 1.

FIG. 4 is a block diagram of another example of the conventional noise reduction circuit.

Figure 4 shows a noise reduction circuit called a crispinning circuit, which is usually used in VTRs (video tape recorders) along with the noise reduction circuit that uses line correlation shown in Figure 1.
It is used in magnetic recording and reproducing devices such as

In FIG. 4, 11 is an input terminal, 12 is a bypass filter (hereinafter referred to as HPF), 13 is a limit circuit, 1
4 is a subtraction circuit, and 15 is an output terminal.

The input terminal 11 is l-1P F 12 connected in series,
It is connected to the difference input terminal of the subtraction U path 14 via the limit circuit 13 and directly to the phase input terminal of the subtraction circuit 14. The output terminal of the subtraction circuit 14 is connected to the output terminal 15.

In the noise reduction circuit shown in FIG. 4, the input terminal 11 has
For example, the output terminal 10 of the noise reduction circuit shown in FIG.
A reproduced video signal is supplied from. The high frequency component signal of the reproduced video signal supplied to the input terminal 11 is
A limit circuit 13 extracts only a small amplitude signal from among the high frequency component signals. The subtraction circuit 14 is supplied with a small amplitude signal of the high frequency component of the reproduced video signal supplied from the input terminal 11 and the reproduced video signal supplied from the limit circuit 13. A signal obtained by subtracting the signal supplied from the limit circuit 13 from the signal supplied to the input terminal 11 is output. Therefore, the output terminal 15 outputs a signal in which the noise components that could not be reduced by the noise reduction circuit shown in FIG. 1 and supplied to the input terminal 11 are reduced.

(Problems to be resolved) However, even if the noise reduction circuits shown in FIGS. 1 and 4 are used, as shown in FIG. The problem was that noise could not be reduced. FIG. 5 is a diagram showing reproduced video signals output from the conventional noise reduction circuits shown in FIGS. 1 and 4. For example, when the conventional noise reduction circuits shown in FIGS. FIG. 3 is a diagram showing a signal obtained by attenuating the high frequency components of a reproduced video signal (a video signal whose high frequency components were amplified by the emphasis circuit at the time of recording) using a de-emphasis circuit from a signal with reduced noise.

Therefore, the present invention detects the temporal position of noise near the rising and falling edges of the reproduced video signal, which cannot be reduced by conventional noise reduction devices, and detects the temporal position of noise near the rising and falling edges of the reproduced video signal. The purpose is to reduce noise in reproduced video signals by varying frequency characteristics.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention outputs a time width detection No. 18 corresponding to the noise component near the edge of the reproduced video signal when a reproduced video signal is supplied. a detection circuit; a delay circuit which is supplied with a detection signal from the detection circuit and outputs a control signal which delays the detection signal by a minute time; The present invention provides a noise reduction circuit comprising a frequency characteristic variable circuit that varies frequency characteristics, and configured to reduce noise components of the reproduced video signal including noise components near the edges of the reproduced video signal.

Embodiment FIG. 6 is a block diagram of a first embodiment of the noise reduction circuit according to the present invention.

In FIG. 6, 16 is an input terminal, 17 is an f-emphasis circuit, 18 is a subtraction circuit, 19 is an absolute value circuit, 2O is a clip circuit, 21 is a delay circuit, 22 is a sitdown control circuit, and 23 is an output terminal. It is.

The input terminal 16 is connected to a de-emphasis circuit 17 and also to a phase input terminal of a tube reduction circuit 18 . The output terminal of the subtraction circuit 18 is an absolute value circuit 19 connected in series.
, a clip circuit 20, and a delay circuit 21 to a control input terminal of a sharpness control circuit 22.

Note that the de-emphasis circuit 17, the subtraction circuit 18, the absolute value circuit 19, and the clipping circuit 20 are elements constituting the detection circuit.

Further, the de-emphasis circuit 17 is connected to the difference input terminal of the subtraction circuit 18 and also to the signal input terminal of the sharpness control circuit 22.

FIG. 7 is a diagram for explaining the operation of the first embodiment of the noise reduction circuit according to the present invention shown in FIG.

The signal shown in FIG. 7 (A>) supplied to the input terminal 16 (
For example, with the conventional noise reduction circuits shown in FIGS. 1 and 4, most of the noise in the reproduced video signal is reduced, and the temporal position of the short time width near the rising and falling edges of the reproduced video signal is The de-emphasis circuit 11 attenuates the high frequency components that have been amplified by the emphasis circuit (not shown in FIG. 6) provided in the recording system. The signal 9 shown in FIG. 7(B) is output.

The subtraction circuit 18 is supplied with a signal as shown in FIG. 7 (△) from the input terminal 16 and a signal as shown in FIG. 7 (B) from the de-emphasis circuit 17. From the signal shown in Figure 7 (△) from 18 onwards, the signal shown in Figure 7 (
Figure 7 (C) is the signal obtained by subtracting the signal shown in B).
A signal is output indicating that the request is accepted. The signal shown in FIG. 7(C) contains noise near the rising, bitter, and falling edges of the reproduced video signal that could not be reduced by the conventional noise reduction circuit shown in FIGS. 1 and 4. The signal has a time width corresponding to the temporal position.

However, the signal shown in FIG. 7(C) contains noise in addition to the signal with a time width corresponding to the temporal position where noise exists near the rising and falling edges of the reproduced video signal mentioned above. , the output of the subtraction circuit 18, which is the signal shown in FIG. 7(C), is supplied to the absolute value circuit 19,
The absolute value circuit 19 converts the signal into a signal having the same amplitude sign as shown in FIG. 7(0), and supplies the signal to the clip circuit 20. The clip circuit 20 is a circuit that outputs only signals of a predetermined level or higher. The clipping circuit 2O removes small amplitude noise components other than the signal shown in FIG. A signal having a time width corresponding to the temporal position where the removed noise near the rising and falling edges of the reproduced video signal exists is input to the delay circuit 21 as a detection signal.

The delay circuit 21 is provided to color the frequency characteristics of the rising and falling edges of the reproduced video signal so that they do not change, and the signal supplied to the delay circuit 21 is a control signal (control input voltage) delayed by a minute amount of time. and is supplied to the sharpness control circuit 22.

The sharpness control circuit 22 is a circuit that varies the frequency characteristics of the reproduced video signal input to the signal input terminal by the control signal (control input voltage) input to the control signal input terminal. The control signal input terminal has a temporal position delayed by a minute time from the rising and falling edges of the reproduced video signal, that is,
The control signal (control input voltage) of the above-mentioned detection signal time width (time width corresponding to the period in which noise exists shown in Fig. 5) is determined from the temporal position excluding the rising and falling edges of the reproduced video signal. Therefore, if this control signal (control input voltage) is used to attenuate the high frequency components of the reproduced video signal input to the sharpness control circuit 22, the sharpness control circuit 2
2, the high frequency components of the reproduced video signal near the rising and falling edges of the reproduced video signal (corresponding to the noise-existing portion shown in FIG. 5) are attenuated. The noise is no longer noticeable.

The first embodiment of the 4T noise reduction circuit according to the present invention described above differs greatly from the conventional de-emphasis circuit and non-linear eye noise reduction circuit, for example, in that the de-emphasis circuit and the non-linear de-emphasis circuit control the rising edge of the reproduced video signal. In contrast, in the first embodiment of the noise reduction circuit according to the present invention, the rising and falling edges of the reproduced video signal are attenuated by signal processing. The point is that the high frequency components of the reproduced video signal in which noise exists near the rising edge, F edge, and falling edge of the reproduced video signal are attenuated without adding any noise. Therefore, without dulling the rising and falling edges of the reproduced video signal,
It is possible to reduce the noise in the reproduced video signal, including the noise shown in FIG. 5, which could not be reduced by the noise reduction circuits shown in FIGS. 1 and 4.

Furthermore, even if the configuration is as shown in FIG. 8 or 9, the noise reduction circuit shown in FIG. It is possible to reduce the noise of the reproduced video signal, including the noise shown above.

FIG. 8 is a block diagram of a second embodiment of the noise reduction circuit according to the present invention, and FIG. 9 is a block diagram of a third embodiment of the noise reduction circuit according to the present invention.

In FIG. 8, the same components as in FIG. 6 are denoted by the same reference numerals, and the reference .beta.2 is omitted.

24 is an l-1PF, 25 is a limit circuit, and 26.27 is a subtraction circuit. The noise reduction circuit shown in FIG.
This is a circuit in which the de-emphasis circuit 1γ, which is the h1 component of the noise reduction circuit shown in the figure, and the subtraction circuit 18 are replaced with the crispening circuit and subtraction circuit 26 shown in FIG.

A reproduced video signal input to the input terminal 1G, for example, a reproduced video signal (a video signal whose high frequency components have been amplified by an emphasis circuit provided in the recording system) by a de-emphasis circuit (not shown in FIG. 8). ) is supplied to the 11PF 24, and therefore, the HPF 24 outputs the high frequency component of the reproduced video signal supplied to the input terminal 16. This high frequency component is supplied to the limit circuit 25 and also to the phase input terminal of the subtraction circuit 2G.

The limit circuit 25 outputs only a small amplitude signal of the high frequency component of the supplied reproduced video signal. This small amplitude signal is supplied to the difference input terminal of the subtraction circuit 26 and also to the difference input terminal of the subtraction circuit 27.

As described above, the subtraction circuit 26 is supplied with the high frequency component of the reproduced video signal from the HP F 24 and the small amplitude signal of the high frequency component of the reproduced video signal from the limit circuit 25. From the subtraction circuit 26, the HPF 24
The reproduced images 1τ, 4B, which are the signals obtained by subtracting the signal supplied from the limit circuit 25 from the signal supplied from the
A signal excluding small amplitude signals among the high frequency components of Q,
In other words, the subtraction circuit 18 of the noise reduction circuit shown in FIG.
A signal similar to that output from is output.

The subtraction circuit 27 receives a reproduced video signal from the input terminal 1G,
Since the small amplitude signal of the high frequency component of the reproduced video signal is supplied from the limit circuit 27, the subtraction circuit 27 subtracts the signal supplied from the limit circuit 25 from the signal supplied from the input terminal 16. A signal similar to the signal output from the output terminal 15 of the crispinning circuit shown in FIG. 4 is output.

The signal output from the subtraction circuit 26 is supplied to the absolute value circuit 19. Also, the circuit configuration after the absolute value circuit 19 is the sixth
It is the same as the noise reduction circuit shown in the figure, and therefore, the signal processing after the absolute value circuit 19 is the same as the noise reduction circuit shown in FIG. 6, so the explanation thereof will be omitted.

Furthermore, the reproduced video signal and the control signal (Fi (control input voltage)) supplied to the sharpness control circuit 23 are the same as those of the noise reduction circuit shown in FIG. 6, so their explanation will be omitted.

Therefore, in the second embodiment of the noise reduction circuit according to the present invention shown in FIG. 8, similar to the first embodiment of the noise reduction circuit according to the present invention shown in FIG. It is possible to reduce noise, including noise, in the reproduced video signal.

Next, the third noise reduction circuit according to the present invention shown in FIG.
An example will be explained. In FIG. 9, the same components as in FIG. 6 are given the same reference numerals, and their explanation will be omitted. 28
is a comparator.

The noise reduction circuit shown in FIG. 9 is a circuit in which the clip circuit 20, which is a component of the noise reduction circuit shown in FIG. 6, is replaced by a comparator 728.

That is, the clip level potential in the clip circuit 20 of the noise reduction circuit shown in FIG. 6 is supplied to the comparator 28 as a reference signal, and this reference potential and the absolute value circuit 1
The delay circuit 21 outputs the signal compared with the signal supplied from 9.
is supplied to.

Further, since other components and signals supplied to the components are the same as those of the noise reduction circuit shown in FIG. 6, their explanations will be omitted.

Therefore, the third embodiment of the noise reduction circuit according to the present invention shown in FIG. 9 is similar to the first embodiment of the noise reduction circuit according to the present invention shown in FIG. The noise of the reproduced video signal can be reduced.

In addition, in the above-mentioned explanation of the embodiment of the noise reduction circuit according to the present invention, it was explained that the noise of the reproduced video signal, including the noise near the rising and falling edges of the reproduced video signal, is reduced. Absolute value circuit 1
9 may be omitted and the noise of the reproduced video signal may be reduced by including only the noise in the vicinity of the rising and trailing edges of the reproduced video signal.

Furthermore, the absolute value circuit 19 can be omitted by setting the clip level of the clip circuit 20 for amplitudes in both positive and negative directions around the reference level.

Furthermore, the noise reduction circuit according to the present invention is based on the NTSC system, P
Needless to say, it is possible to apply the present invention regardless of the AL method or the SECAM method.

(Effects of the Invention) Since the present invention has the above-described configuration, it has the advantage that it is possible to reduce noise in the reproduced video signal, including noise near the edges of the reproduced video signal.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an example of a conventional noise reduction circuit that uses line correlation, Figure 2 is a diagram for explaining the operation of the conventional noise reduction circuit, and Figure 3 is a diagram of the conventional noise reduction circuit. FIG. 4 is a block diagram of another example of the conventional noise reduction circuit; FIG. 5 is a diagram showing the reproduced video signal output from the conventional noise reduction circuit; FIG. 6 is a diagram for explaining the operation. 7 is a block system diagram of the first embodiment of the noise reduction circuit according to the present invention, and FIG. 7 is a diagram for explaining the operation of the first embodiment of the noise reduction circuit according to the present invention shown in FIG. , FIG. 8 is a block diagram of a second embodiment of the noise reduction circuit according to the present invention, and FIG. 9 is a block diagram of a third embodiment of the noise reduction circuit according to the present invention. 1... Input terminal, 2... FM demodulator, 3... Low pass filter <LPF), 4... Delay circuit, 5-F
M return 1[, 6・LPF, 7・111E[l, 8... limit circuit, 9... subtraction circuit, 10... output terminal,
11...Input terminal, 12...Bypass filter (H
P F ), 13...Limit circuit, 14...Subtraction circuit, 15...Output terminal, 16...Input terminal, 17
...De-emphasis circuit, 18...Subtraction circuit, 1
9... Absolute value n path, 20... Clip circuit, 21.
...Delay circuit, 22...Sharpness control circuit, 23...Output terminal, 24...HPF125...
・Limit circuit, 26, 27... Subtraction circuit, 28...
·comparator. Patent applicant: Japan Victor Co., Ltd.

Claims (1)

[Claims] a detection circuit which is supplied with a reproduced video signal and outputs a detection signal having a time width corresponding to a noise component near the edge of the reproduced video signal; and 'Ithg[! A detection signal is supplied from the detection circuit, and the detection signal is delayed by a minute time.1) A delay circuit that outputs a delayed control signal, and a control signal is supplied from the delay circuit, and the frequency characteristics of the reproduced video signal are varied by the control signal. a frequency characteristic variable circuit configured to reduce noise components of the reproduced video signal including noise components near edges of the reproduced video signal.