JPS58179030A - Noise reduction circuit - Google Patents

Abstract

PURPOSE:To reduce the conspicuousness of a noise area, by decreasing the difference of signal levels between a noiseless area and a noise area. CONSTITUTION:An input signal (a) is converted into a signal (f) by an LPF8 and via a delay circuit 3 and then into a signal (f') by an attenuator 9. the signal (f') is added with a signal (c) given from an LPF2 with the same phase. In this case, the rise of the signal (g) is slow compared with the signal (c). Then the signal (g) is subtracted from the signal (a) to obtain only the high band component. The signal (a) is turned into a signal (b) with the amplituide limited by a limiter 6. Then a signal (h) is subtracted from the signal (a) by an adder 5, and a reproduced luminance signal (k) from which the noise component is excluded is extracted out of an output terminal 7. In this case, the rise of the output (k) becomes slow to suppress the conspicuousness of a deteriorated area on a reproduced screeen. Furthermore the level itself is attnuated by delay circuits 11 and 12, attenuators 13 and 14 and an adder 15 respectively to suppress the deterioration of the screen less conspicuous.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noise reduction circuit, and provides a noise reduction circuit that reduces the difference between the signal level of a part that does not generate noise and the signal level of a very quiet part, and makes the noise part conspicuous. The purpose is to provide

A small household magnetic recording/reproducing device f (hereinafter referred to as a VTR) performs various types of signal processing, and some of these processings cause signal deterioration. That-
For example, the reproduction system 1 is provided with a so-called noise reduction circuit for removing noise components superimposed on the FM-demodulated reproduced luminance signal, and various circuits have been proposed in the past.

FIG. 1 shows an example q) block diagram of a conventional noise reduction circuit. In the same figure, the FM demodulated signal a (Fig. 2) containing noise components that entered the input terminal 1 is filtered through a low-pass filter consisting of a resistor and a capacitor as shown in Fig. 3 (t). At step 16, high-frequency components including noise components are removed to form a signal U (FIG. 2(B)), which is supplied to an adder 17 in reverse phase. Since a low-pass filter generally has an integral action, the signal U rises with a certain time constant,
The waveform is somewhat distorted.

On the other hand, the reproduced luminance signal a is in the same phase as the adder 17 and the adder 1.
8. In the adder 17, the signal a is subtracted from the signal a to produce only the high frequency component V as shown in the figure (q), and in the limiter 19, only the large width signal component which is the signal component is controlled at the limiter level L'. Only the small-width components considered to be noise components are output as shown in FIG. 2 and are supplied to the adder 18 in reverse phase.

In the adder 18, the noise component W of the output of the limiter 19 is subtracted from the signal a, and from the output terminal 7 the noise component W of the output of the limiter 19 is subtracted from the signal a.
The reproduced luminance signal X from which the 9n noise components shown in FIG. 1 have been removed is extracted.

However, this conventional circuit has 9 circuits as shown in Figure 2 (G).
There is a drawback that a noise component remains immediately after the rise of the signal, making it impossible to obtain a high-quality image.

Therefore, in order to eliminate this drawback, the applicant proposed the noise reduction circuit described below.

FIG. 4 shows a block diagram of an example of a noise reduction circuit previously proposed by the applicant. The reproduced luminance signal a (m5 figure) containing the noise component that has entered terminal 1 has a rise time (0.5 μssc to 2 μ5e) of low-pass filter 2, which will be described later.
c) When 5-Δ, the signal is delayed by the delay circuit 3 having a delay amount of (IH-Δ) (H is one horizontal scanning period). Ru
In other words, the output of the delay circuit 3 is a signal approximately before IH of the signal a as shown in FIG.
High-frequency components including noise components are removed from the signal C (fQ'' in FIG. 5), which is supplied to the adder 4 in reverse phase.

The low-pass filter 2 is, for example, a 6th-order Bessel filter with m configurations as shown in Fig. 6, and its frequency characteristics are as shown in Fig. 8, and its frequency characteristics are as shown in Fig. 8.

On the other hand, the reproduced luminance signal a is supplied to the adder 5 in the same phase. In the adder 41, the signal C is subtracted from the signal a to obtain only the high-frequency component, and in the limiter 6, only the dog & 1IiA signal component, which is the signal component, is limited in width at the limiter level L, and the noise component ( !: Only possible small-field width components are output as shown in Fig. 5 (b) l, and are supplied to the adder 5 in reverse phase. Since the H level signal is subtracted from the signal a, it is possible to reliably separate and extract the noise component of the signal a, especially immediately after the rise.

In the Calo calculator 5, the noise component d of the output of the IJ Mitsutaro is subtracted from the signal a, and the reproduced luminance signal e from which the noise component has been removed as shown in FIG. 5(g) is taken out from the output terminal 7. Note that when subtracting signal C from signal a,
Since the signal C has a certain rise time constant, it is not possible to completely extract the noise component of this rising portion, and therefore some noise remains just before the rise of the signal e when it is read in the adder 5. In general, the noise just before the edge of the ~'14-L survey signal is smaller than that just after the edge.
Also, since the noise in this part is less noticeable than that immediately after the edge, there is virtually no problem even if it cannot be completely removed.

Therefore, if we consider the signal deterioration just before this edge, the degree of conspicuousness of this signal deterioration can be determined by the rising edge y of the output e transitioning from the black level to the white level, as shown in Figure 5, or similarly from the white level to the white level. It is related to the time constant of the fall of the transition to the black level, and in order to make this signal deterioration more inconspicuous, it is necessary to make the time constant of the rise or fall as gentle as possible. This rise or fall is caused by the output C of the Ujizuka filter 2 (see Fig. 5).
This is because there is a time constant in the rise of C1), and if this rise is too steep, the white part in front of the edge that changes from white to black on the screen, or the gray to gray that is as high as # than Kone, will appear on the screen. There is a black shading on the edges, which gives a good quality 1.
I! L image cannot be obtained.

- When considering the level of the force that causes deterioration on the playback screen, it can be seen that in Figure 5 (El and 2
The smaller the difference between the level where the noise component exists and the level where it does not exist, the smaller the difference in brightness between the shaded area and the area without the touch, and the less conspicuous the shaded area becomes. You can get Io.

The present invention satisfies the above requirements, and together with Figures 9 and below, the -? I will explain about the Soviet V1M1Tari.

FIG. 9 shows a block diagram of the first embodiment of the noise reduction circuit according to the present invention, and in the same figure, the same parts as those in FIG. 4 are given the same numbers. Among the four filters 1, 8 is a low-pass filter composed of a capacitor and a resistor, and its delay amount is set smaller than that of the low-pass filter 2.

The signal taken out from the delay circuit 3 is filtered by a low-pass filter 8 to remove its local components, resulting in signals f and f, shown by solid lines in FIG. The level is wiped out by the P2 attenuator 9, and the level is varied from 2% to 5% with respect to the level of the signal f. be done. The signal C ((C) in the same figure) which has been completely extracted from the low-pass filter 2 is supplied to the in-phase amplifier 0 and is amplified, resulting in the signal shown by the broken line in (C) of the same figure. 2. In this case, the signal C, which has a large delay with respect to 1+5b, is used.
i against b! ! ! Since the signal f' having a small extension is added, the rise of the tra No. 2 signal S, which is the result of the addition, is gentler than the rise of the 4i+jc signal S.

No. 1g t is supplied in reverse phase to an adder 41, where signal 1 is subtracted from signal a to obtain only the high frequency component, and in limiter 6, only the large width signal component is subjected to heavy wheel restriction at limiter level L. The signal shown in FIG. In the adder 5, the signal a is subtracted from the signal a, and from the output terminal 7, a reproduced luminance signal i from which noise components have been removed as shown in the figure is taken out and supplied to the adder 15 in phase. In this case, in the adder 5, the maximum slope until reaching the limiter level L is smaller than that of the signal C (the rise is gradual with respect to the signal C). is subtracted from the signal a, the rise y' of the output i is compared to the rise y of the output e by the circuit shown in FIG. 4, which is configured to subtract using the signal d obtained from the signal C. It is gradual.

In other words, in this embodiment, as shown in FIG. 10 (moon), the degree of level change from signal level 1 to level 11 is made gradual to make the degraded portion less noticeable on the playback screen. Compared to the case shown in Figure 4, where the degree of level change is relatively steep, it is possible to reduce the black border that occurs in the white part in front of the edge that changes from white to black at the top of the screen, and it is possible to obtain a high-quality image. .

On the other hand, the signal f from the low-pass filter 8 is transmitted to the delay circuit 11.1.
2, the signal j shown in the figure (Q, (Hl),
It is attenuated by attenuators 13 and 14 and becomes
, 2% to 7% with respect to the level of signal i shown in (J)
The signals J' * '' at a level of about
The amount of delay is +! , is set depending on the rise time and level of the rise time y' of the signal i taken out from the device 5. The adder 15 converts the signal i to the signal j
By subtracting ' and ', the level of the rising edge y' of the signal i shown in FIG.

As mentioned above, the adder lO has a configuration in which the level is gradually raised to make the degraded portion less noticeable on the screen.
In No. 5, the level itself is attenuated to make it less noticeable.

If the signal level 11 of signal i is attenuated in this way,
level l. The difference between and level 11 becomes smaller, and the brightness of the shaded area on the playback screen can be reduced, making the shaded area even more noticeable.
It is possible to obtain even better quality images.

In addition, when subtracting the signal from the signal a in the adder 5, in addition to setting the level amount of the signal a and the signal to 1'1 (in this case, the noise component is best suppressed), for example, the limiter 6 If these are set to, for example, 1:0.7 by attenuating the output of the signal i, the level 11 of the noise component in the signal i becomes low (level 61'), while the level l.

A noise component remains in l12. If this is done, the degree of modification of the SN ratio will be reduced and a small amount of noise will be generated on the entire screen, but it will be at a level l. Since there is little change from level 11' to level 11', the brightness of the shading on the screen is reduced, resulting in a well-balanced image.

FIG. 11 shows a block system diagram of a second embodiment of the circuit of the present invention, in which the same components as in FIG. 9 are given the same numbers. In this device, a signal as shown in Fig. 10 (Bl) enters terminal 1, and is delayed by delay circuit 3' to obtain signal a shown in Fig. The signal is supplied to the filter 2.8 to obtain signals c and f shown in (C) and (DJ) in the same figure.

In this case, the delay amount of the delay circuit 3' is set to the rise time t of the low-pass filter 2 (FIG. 10(C)).

The operation and effects of this device can be more easily understood than the embodiment shown in FIG. 9, so the explanation thereof will be omitted.

Note that the embodiment shown in the 11th figure is similar to the embodiment shown in the 9th figure,
The input value in the adder 5 may be set as 1:07.

Furthermore, in each of the above embodiments, V of the output signal i of addition C^5
In addition to the delay circuits 11 and 12, a delay circuit may be provided in parallel with the delay circuits 11 and 12 depending on the uplink, or, conversely, if only the delay circuit 11 is sufficient, only this delay circuit may be used.

Further, in each of the embodiments, a filter having an appropriate amount of delay may be used instead of the delay circuit.

Furthermore, in each of the above embodiments, the signal S may be supplied to the delay circuits 11.12J instead of the signal f.

Further, the subtraction amount by which the signal a is subtracted from the signal a in the adder 5 is not limited to 1:0.7, and may be appropriately selected depending on the level of noise components included in the information signal. good.

As mentioned above, the noise reduction circuit according to the present invention is
A delay circuit that delays an information signal by a predetermined amount, a filter circuit that removes high-frequency components of the output of the delay circuit or the information signal, and a filter circuit that removes the output of the filter circuit from the output of the delay circuit or the information signal. PL to separate and extract the area components
, a limiter that limits the amplitude of the large width component that is a signal component for the output of the arithmetic circuit of No. 1, and outputs the small S+= component that is considered to be a noise component as is, and a delay circuit. a second arithmetic circuit that subtracts the output of the limiter from the output or the ``sad signal''; and a signal obtained by delaying the output of the delay circuit or the information signal by a predetermined amount and then attenuating the signal from the output of the second arithmetic circuit. Since it consists of a subtraction circuit, it is possible to reduce the level change between the level of the part from which the noise component is removed and the level of the part where the noise component exists during the output of the second arithmetic circuit, and thereby, for example, VT
When this R reproduction system ζ is applied, the difference between the brightness of the non-deteriorated part and the brightness of the degraded part on the reproduced screen can be reduced compared to using the output of the second arithmetic circuit as is, and the shading can be made more noticeable.
Great deal, good quality li! It has an axial length such that Ili & can be obtained.

[Brief explanation of drawings]

1 and 2 (A1-(E) are respectively a block system diagram of an example of a conventional circuit and a signal waveform diagram for explaining its operation.
The figure is a concrete circuit diagram of a mid-low pass filter, and Figures 4 and 5 (Al-2) are block diagrams and block diagrams of an example of the noise reduction circuit that I first proposed. 6 is a specific circuit diagram of the low-pass filter shown in FIG. 4, and FIGS. 7 and 8 are a frequency characteristic diagram and an output characteristic diagram of the low-pass filter shown in FIG. 4, respectively. 9 and 10 (2) to (■) are a block system diagram of the first embodiment of the circuit of the present invention and a signal waveform diagram for explaining its operation, respectively.
FIG. 1 is a block diagram of a second embodiment of the circuit of the present invention. l... Reproduction luminance signal input terminal, 2, 8... Low pass filter, 3, 11, 12... Delay circuit, 4, 5° 10.
15... Adder, 6... Limiter, 7--Fist output terminal, 13, 14... Attenuator. Figure 1 Figure 21 Nu 1 No. 1: (1 Me 1 Figure 1 Figure 8 Figure 1 Figure 1) Figure 10 Figure 11 l 1 Figure 11

Claims (3)

[Claims] (1) In a noise reduction circuit that separates and extracts a noise component from an information signal, calculates the information signal and the noise component, and removes the noise component from the information signal, the information signal is a filter circuit that removes a high-frequency component of the output of the delay circuit or the information signal; and a filter circuit that subtracts the output of the filter circuit from the output of the delay circuit or the information signal to separate the high-frequency component. and a first arithmetic circuit that extracts the output from the first arithmetic circuit, and limits the width of large width components that are signal components, and outputs small width components that are considered to be noise components as they are. a limiter; a second arithmetic circuit that subtracts the output of the limiter from the output of the delay circuit or the information signal; A noise reduction circuit comprising a delay/arithmetic circuit that subtracts from the output of the second arithmetic circuit. (2) The delay arithmetic circuit includes a plurality of delay circuits that are supplied with the output of the delay circuit or the information signal in parallel and each having a different delay time, a plurality of attenuators that attenuate the output of the plurality of delay circuits, respectively; 2. The noise reduction circuit according to claim 1, comprising an arithmetic unit that subtracts the outputs of the plurality of attenuators from the output of the second arithmetic circuit. (3) The subtraction amount in the second arithmetic circuit is set to be smaller than the subtraction amount by which the noise component is best suppressed. Noise reduction circuit.