JPS60129725A - Surface field-effect device - Google Patents

Abstract

PURPOSE:To diversify functions by providing a gate area at one side of an insulating film covering a semiconductor area, and using part of a semiconductor area to which surface electric field effect extends as an optical waveguide. CONSTITUTION:An insulating layer 2 and a semiconductor film 3 are formed on a substrate 1, and a source 4 and a drain 5 are provided at both sides with the insulating layer 2 between; and electrodes 6 and 7 to which a voltage is applied are formed on the semiconductor film with the insulating film 2 between while overlapping the source 4 and drain 5. An inversion layer 8 formed on the surface of the substrate 1 is coupled with the source 4 and drain 5 and a depletion layer 9 is controlled with the voltage applied between the inversion layer 8 and an electrode 1t for the substrate. Light to be guided is entered from the side of the source 4 through a passive optical waveguide 11 to propagate a depletion layer 9 under a channel from a depletion layer 4d under the source 4 and is guided to a passive waveguide 12 through a depletion layer 5d under the drain 5. Consequently, functions are diversified.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surface field effect device in which a part of a semiconductor region where the surface field effect can reach is an electromagnetic wave dielectric waveguide, which utilizes the interaction between the semiconductor and electromagnetic waves such as light to achieve functions. In order to effectively increase the diversity, a change in the potential distribution is formed on the semiconductor surface, thereby reducing the effect of light on the semiconductor surface, the change of the channel on the semiconductor surface, and the effect of the depletion layer due to the surface field effect junction. Control.

A depletion layer beneath or near the channel is formed simultaneously with the generation of the field-induced junction. In this channel and depletion layer,
A potential can be supplied from the source, drain, etc. through the conductive layer of the inversion layer.

The present invention utilizes a semiconductor layer having such a depletion layer as a dielectric guide layer for electromagnetic waves such as light (hereinafter referred to as light).

The main structure and operation of the present invention will first be conceptually explained with reference to a sectional view of a basic embodiment of the surface field effect device of the present invention shown in FIG.

An insulating film 2 is formed on the surface of the semiconductor substrate 1, and a semiconducting film 3 is further formed on this insulating film, preferably using a semiconductor such as SiC that is transparent in that region.

Also, the boundary of the part where the semiconducting film 3 disappears and a part of it overlaps.
A source 4, which is a diffusion layer or an impurity-introduced layer having a conductivity type different from that of the substrate, is formed into the semiconductor substrate through the insulating film 2 by wrapping.
, a drain 5 is provided.

The semiconducting film 3 has electrode layers 6 and 7 for applying voltage, and these electrode layers 6 and 7 are connected to the source 4 and drain 5, respectively.
They are formed with an insulating film 2 in between so as to partially overlap.

By applying different potentials to the gate control electrode layers 6 and 7, it is possible to distribute the potential drop across the semiconducting film 3 in a planar manner.
etal-Resistivelayer-1ngul
It can also be seen as a type of field effect device.

However, in the present invention, the means for changing the potential distribution in the gate region is not limited to the resistive layer, as will be apparent from the description below. The basic structure of the variable potential distribution insulated gate field effect device (Variable Di
Distribution of PotentialIn
Sulated Gate Field Effect
Device; abbreviated as Vari-PIGFED)
can be called.

The inversion layer 8 formed on the surface of the source 4. It is connected to the drain 5, and the depletion layer 9 is connected to the inversion layer 8 and the substrate electrode 1t.
The width of the depletion layer is controlled by the voltage applied between the two. Actually, the potential of the inversion layer 8 is the source 4, drain 5
varies from source to drain depending on the potential of

In FIG. 1, guided light enters from the source side via a passive leading wavepath 11 and then descends to the source 4,
It is desirable to be able to propagate guided waves with little loss.

The condition for the leading waveguide is that it has a larger refractive index than the surrounding material layers. Ta205 coexisting with Si planar film
Waveguides such as membranes are described in U.S. Pat. No. 4,003. E132 (
1977); ”0ptoelectronic 5
ericonductorDevice”.

The refractive index of the Ta2es film is 2.10 to 2.20. The refractive index of other related substances is 541
! What is the refractive index of 5i02 at a wavelength of 1A? , 48, and S
That of i is 4.05-0.028j. Si'C
There is no detailed data regarding this, but it is thought to be about 2.81 at a wavelength of about 11000A.

In order to separate the Ta205 film waveguides 11 and 12 from the SiC substrate, an oxide film of SiC (Si02
) 10 was interposed between each Taz0s film 11.12 and the substrate 1, and there was no leakage of light to the substrate at 7000 people, and approximately 300
If the thickness is reduced to 0, leak light will occur. Conversely, if you want to supply optical input to devices that are in contact with the top and bottom of a series of optical waveguides, only that part is connected to the intervening 5i.
By intentionally making the 0z film thinner, the desired optical couple can be achieved.

Generally, the mode of the leading waveguide is determined by its own refractive index n and thickness W, and the refractive index n2 of the layer above the refractive index noz of the layer below. Both TE waves and Tl1l waves, for example Ta2es
It is shown in the second US patent that the angle θl at which the guided light wave intersects the interface of I)l is different.

On the other hand, modulation due to depletion layers in compound semiconductors has been reported in detail in pn junctions of GaP and the like.

In this example, MlS is transparent and stable in the visible light region.
From the viewpoint of the structure, SiC is used to construct the Vari-DPIGFE port described above.

1 The refractive index of the depletion layer changes depending on the electric field. In the case of the example, the potential difference applied to the depletion layer at each point of the channel is the potential applied to the north pn junction, the potential applied to the drain pn junction, and the potential applied to the substrate bias terminal 1t. It depends on many variables, such as the potential, the potential drop resulting from the electrodes 6 and 7 distributed in the gate region. Therefore, it can be seen that this depletion layer waveguide 9 is an active waveguide, unlike a mere passive waveguide 11, 12.

Furthermore, the depletion layer of a normal pn junction has a metallurgical structure and has an existing pn boundary, but the channel and the depletion layer below it due to the surface electric field induced junction in this embodiment device are
Crystallographically, it is pseudo, and it occurs and disappears depending on the distribution of the electric field near the surface. Therefore, by successively changing each terminal voltage of the device of this embodiment with an appropriate time sequence, the depletion layer waveguide can be made locally movable.

Furthermore, it was explained that the channel leading to characteristic 5 of this type of surface field effect device is rectangular with a constant width and shape so that guided waves can be modulated, but even if the source side is integral, the drain It is also possible to consider a structure in which the sides are divided. Such an embodiment will be explained with reference to FIG.

In this case, there is only one junction on the source side, which is designated by the symbol S in FIG. In order to control the surface potential at the source end, the Vari-
A gate electrode Go for DPIGFED is arranged.

On the other hand, on the drain side, from the first drain old to the seventh drain D
7, and in order to control the surface potential of each drain end, GB corresponding to electrode 7 in the first embodiment.
I, GB2. GB3. ~． There are seven gate region electrodes of GB7.

In addition, in the case of the second illustrated embodiment, which has seven channels from the source side of the tree, unlike the first illustrated embodiment,
Although there is a three-stage gate I region control electrode group Go, GAi, and GBi in the gate I region, in the spirit of the present invention, it is sufficient if it is '/ari-DPIGFED.

That is, it is sufficient that the gate region has a variable potential distribution structure, and it is a design issue as to how many control electrodes are arranged in the gate region. Therefore, it can be placed in the transport as needed.

In Fig. 2, the optical input guided wave guided by the passive common waveguide PG(0) is a multi-branch channel type Var.
Exiting the i-DPIGFED, how each branch's passive waveguides PG(1), PG(2), , , , , , PG
Let's consider whether it will be divided into (7).

Various operating modes are possible, but here we will consider the drive pulses for the gate region electrode group as shown in FIG.

The potential of the channel S and the potential of the source side electrode C0 are
1, the kited wave that has passed through the common waveguide PC(0) is kited to the first branch PC(1) by the potential gradient of the surface channel and becomes output light. .

At the next timing, electrodes GBI, GAI are deenergized so that the channel closes, and instead electrodes GB2.
Channel C2 is generated by the gate potential of G^2,
Considering that the other electrodes GAi, GBi are given a bias that closes the channel Ci, the guided wave is now output to the second output waveguide PC(2) regarding the channel C2.

If the bias relationship of the gate section is set so that the seven channels C1-07 are generated sequentially in this way, this device will work as a multi-branch channel optical guide switch.

It also becomes possible to perform an operation in which a conductive via is provided to the gate electrode GO on the source side.

Furthermore, in the above example, the channels Cl-C7 were opened and closed sequentially, but if the gates are driven so that a plurality of channels are generated simultaneously, the input guided wave from the input waveguide pc(o) is transferred to the output waveguide. The output is simultaneously divided and output into multiple selected waveguides in the PG(i) group. However, dividing the output means dividing the power of the input light, so depending on the application, this point may be need to be taken into consideration.

As can be seen from the embodiments described above, the Vari-
Active waveguides and multi-branch channel optical guide switches using DPIGFEDs create a variable potential distribution in the gate region of the insulating crotch, and change this by applying a voltage to a control electrode installed in the gate region, allowing channel switching and other functions. It modulates the mode of light waves.

By the way, it is conceivable that this may become a problem for applications such as opto-electronic integrated circuits (OE-ICs).

The object of the present invention is to provide an active light guide switch and the like as already mentioned. However, when considering driving such a Vari-DPIGFED device with various input signals as in the previous embodiment, the switching operation of the field-effect transistor or field-effect tetrode of the Vari-DPIGFED, which has a source and a drain, cannot be controlled. It is good to understand this. Also, as will be explained later, in order to efficiently perform high-speed operation and switch operation, it is good to consider the means of generating a variable potential distribution on the insulating film. In some cases, a semiconducting film or a resistive film (such as polysilicon) alone is not sufficient.

Furthermore, it is more desirable that the potential changes not only due to the switch due to the change in the potential in the gate region, but also due to the optical input.

These points will be explained in detail below.The first method is used to detect a photoresponse.

Techniques for forming a single crystal film on an insulating film are made possible by laser annealing, electron beam annealing, and the like.

A PNPN thyristor is characterized in that it has an off state and an on state, and in the off state, when a breakover voltage or higher is applied from the anode, for example, it exhibits negative resistance and is reversed to the on state. and.

When current is passed through the two layers of the third control electrode, the breakover voltage shifts to a smaller value.

Furthermore, when light is input to the control electrode, a current is generated and the device can be turned on. Once this device enters the on state, in order to return to the off state, the anode current must be lowered below a value called the holding current, or a reverse voltage must be applied for a certain period of time called the turn-off time. ie, the device is latched.

The gate region of N-channel MO9 is coated with photosensitive Va.
It can also be an r i -DP IGFED.

On the other hand, a Josephson junction element is an element that can be driven at low voltage, consumes low power, and operates at high speed. This element is hereinafter abbreviated as J, J, and one J or JL generally has an Ij-Vj characteristic of at most 2.5■
Although only a voltage step of about V is shown, this is connected in series with n
When connected, a voltage step of 2.5 mV x n can be generated.

As will be explained later, by operating the Vari-DPIGFED at extremely low temperatures and setting a J,J,array consisting of multiple series J,J,as a switch mechanism in the gate region, a transistor with low power consumption and high speed operation becomes possible. Become.

Next, we will explain the operation of Vari-DPIGFED from FET to FET.
An explanation will be given to understand it as an ET tetrode.

Conventional MIS) transistors use a metal electrode or highly doped silicon for the gate, so they have a structure where saturation occurs near the semiconductor layer.However, if the channel near the source and far from the drain Saturation due to depletion of channel carriers or saturation of carrier velocity can occur at any position within the region, or a low concentration region of channel carriers can be created by controlling the carrier distribution.
It would be convenient if it were possible to set a high concentration region.In particular, if it were possible to create a structure in which the channel is wide open on the drain side from that point following saturation due to carrier velocity saturation, the channel would be effectively shortened. The result is the same as in the previous example, and a higher transformer conductance (G-peng) can be obtained.

It can be seen that for this purpose, it is sufficient to have an arbitrary potential distribution in the gate region. As a means of achieving this, in addition to a highly conductive metal or other conductor, a semi-conducting film can be used in the gate area to provide a positional cloth in contact with the film, increasing the diversity of functions and improving its performance. The basic idea and analysis thereof are described in detail in the first US patent.

In such MRIS type, Vari-DP, IGFE port defined in a broader sense in this specification, the conventional M
Compared to IS transistors, significantly higher Gm and gain can be obtained. In other words, this Vari-11PI
In a GFED, even if an extremely small signal is applied to the first gate electrode near the source, a sufficiently large output can be obtained by connecting an appropriate load to the drain end.

Also, depending on the design and the settings of the first and second gate voltages and drain voltages, it is possible to exhibit pentode characteristics even when the drain voltage is extremely small, and in that sense, it is possible to obtain ideal switching characteristics. I can do it.

In any case, such a Vari-DPIGFED can desirably be operated at a considerably low power supply voltage, such as when a continuous inverter amplifier is configured.

On the other hand, as described above, when such a Vari-DPIGFED is used as a component of the present invention, it is desirable that the voltage of the gate manual pulse input to the first gate electrode is as low as possible. To this end, it is conceivable to operate the channel region, which is mainly controlled by the first gate electrode near the source, below the threshold voltage Vth of a normal M(S transistor. Such operation is called a subthreshold region. It is known that the dependence of gate voltage on drain current is quite different above the threshold voltage: in this region, a small increase in gate voltage causes the drain current to increase exponentially.

To achieve such a small gate input voltage, it is possible to create a pressure 1 source and apply it to the gate, but one way to generate a more accurate and small voltage step is to use the method described above. Josephson junction device (J, J
, ).

One typical structure of J, J, is one in which an insulating film of several 1 OA or a semiconductor film of about 200 to 800 OA is sandwiched between two superconducting metals. , 800 people in CdS.

The static characteristics of J and J are as shown in Fig. 4, and until the element current 1j exceeds the critical current value l-,
Although it is in a zero voltage state where no significant voltage is generated across the element,
When the critical current value I■ is exceeded, a change in the quantum mechanical coupling state between the two superconductors causes a change in the coupling of the wave functions across the tunnel barrier, as shown at point a in Figure 4. As such, the device transitions from a voltage state where a finite voltage ΔVg is generated across the device to a resistance state. The voltage ΔVg at this time is called the gap voltage, and in the case of first-class superconductors such as Nb and Pb, about a pair of broken quasiparticles are involved, and in the curve section C where the device current Ij further increases, there is resistance. The Ij-Vj characteristic is as follows.

In addition, when the element current is reduced from this quasiparticle state, it does not jump to the zero voltage state immediately after returning to point a, but instead returns to the zero voltage state for the first time after point b, creating hysteresis. The point is called the knee point.

There are J and J that use a semiconductor layer instead of an insulating film as a tunnel barrier layer, but in both J and J, the transition operation is not only determined by the current flowing through the element itself, but also by the external magnetic field. Since the critical current value I can be changed by selective application and its magnitude, the transition operation of J and J can also be defined by the magnetic field.

Further, by using the semiconductor layer as a tunnel barrier layer and the coupling between the conductors becoming stronger, the critical current Is increases to Imp.

Therefore, after increasing these ■■ by introducing pulsed light of an appropriate duration into several J, J at multiple locations, a critical current is generated through a resistor connected in series. value I
■That's it! (2) Let's consider applying a current pulse with a magnitude less than p. At this time, assume that the current pulse is also applied to other resistor parts J, , +, + that are not hit by the optical pulse.

Then, J, J, which is hit by the light pulse will not transition to the voltage state because the critical current value increases, but J, J, which is not hit by the light pulse will transition to the voltage state. I can do it. Since "J" is a latch operation, J, J, which has been selectively transitioned to a voltage state, can maintain its voltage state even after the optical pulse is removed.

:1 Selective voltage state transition is negative logic for optical input.)
1'-.

On the other hand, to adopt a positive logic configuration such that ``J'' transitions to the voltage state - with respect to optical input.

If the resistance component H connected in series with J and J is made to have photoresponsiveness so that when there is light input, the resistance value Ro changes from the previous resistance value Ro to a lower resistance value RP, this will reduce the current. Since J can be increased, a current exceeding the critical current value can be supplied to the series connected J.

The resistance component R connected in series to J and J can be formed using a semiconductor layer such as a polysilicon layer or crystalline silicon.

In order to improve the photoresponsiveness with the resistance component R using a semiconductor layer, a PN junction, PIN junction, MS junction, etc. may be used.
When operated under reverse bias conditions, it has higher sensitivity than a simple semiconductor layer. Of course, the resistance component whose resistance value decreases due to the photoresponse will be J, J, etc. for the appropriately selected optical input pulse when inputted with an appropriately selected voltage level and pulse timing to an appropriate component other than the above. It is possible to control the phenomenon in which the voltage transitions from a zero voltage state to a voltage state. Note that J and J shown in the fourth diagram show only the first quadrant, but the fourth quadrant can also be used.

One of the characteristics of J, J as described above is that the resistance is zero unless it enters the quasi-particle state, so it has low power consumption in terms of wood, and can be driven at low voltage.

In the present invention, as is clear from the above, the two-state transition function between the zero voltage state and the voltage state of J, J is captured as a selective voltage step generation means, and therefore this is used as a variable voltage step generation means. - A combination with DPIGFED is also included within the scope of the present invention.

The F part electrode E1 is formed in an island shape, and then an insulating film or a semiconductor film is formed as a tunnel barrier layer B only around the junction using lithography and microfabrication technology.Then, the upper electrode E2 is formed as a lower electrode. Similarly, it is formed using lithography and microfabrication technology so as not to be in direct contact with El.

Another method of formation is to make full use of microfabrication techniques such as etching, as shown in Figure 5 (B), or to create a V-shaped groove in which the groove width becomes narrower as it gets deeper from the surface. It is also possible to cut the superconductor film and process it by controlling the closest distance between the islands of each superconductor to about several tens to 1000 λ. picture. □1.
2.0ゎIt is sufficient that the distances between the individual etched grooves of the eight junctions are the same, and it is inevitable that the gap distances differ along the line of one groove. Ideally, it would be desirable if processing accuracy could be improved by advances in technologies such as ion beam lithography and electron beam lithography, especially if various self-alignment methods and direct pattern forming methods were established. 1
．． It is becoming easier to create a series configuration of J, by forming a gap interval between the grooves using a technique using a planar configuration, and then forming a semiconductor layer B corresponding to a barrier in the gap portion.

In this case, the semiconductor layer does not necessarily have to be a crystal layer, but may be an amorphous film (a-9i) or a polycrystalline film (caS).
Furthermore, by combining the barrier layer B of the single-crystal semiconductor film with the above-mentioned superconductor film formation process, etc., such a series J, J configuration is also possible. .

In the J, J array shown in No. 5A and B, all J,
When J, transitions to a voltage state, a stepped voltage step as shown in FIG. 5C is formed.

Various uses can be considered for such stepped voltage steps.

One is that the potential at both ends of the series J, J array configuration is J
, J, is n times larger than the case where there are − pieces, so
This voltage of nXΔVg is used as a voltage pulse.

Again, this stepwise potential is S, 11
It is to distribute the insulation crotch between 470 and 470 mm. - As an example, the gate potential distribution in such a case is shown in FIG. 5(C).

In such a case, the gate voltage of Var 1-DPIGFED will be 400, and even if ΔVg = 4■V, there will be 2
50 pieces are required. Therefore, for example, when a large voltage drop of IV or more is required in the gate region, it is advantageous to partially use a semiconductor crystal layer such as Si or a polycrystalline layer.

FIGS. 6(A) and 6(B) show a cross-sectional view and a plan view of the vicinity of the gate portion in such a case.

In FIG. 6A, an n middle layer source 8'l and an n middle layer drain 62 are formed on a substrate 83. The gate insulating film 84 of the channel 6B can have an appropriate value depending on the gate voltage distribution, and can be changed from about 50 OA to about 100 OA. Further, it is more effective to use a thin insulating film structure only in the channel portion. The insulating portion other than the gate region is covered with a thick insulating film. Most of the region covering the channel 88 in the gate portion is covered with a resistance layer (R) 85. This resistance layer yes, electrode old and electrode M3 as intermediate electrode
There are,n,J,J,series arrays between them. By adjusting the voltage applied to the electrode N4, when the electrode N4 is VO2, n
Individual J, J.

Whether it is in a zero voltage state or a voltage state can be controlled by a small voltage VGI applied to the electrode Ml.

The voltage distribution relationship in the gate region at this time is referred to as a voltage state. In this case, the channel is kept relatively wide open within a range of 0.1jllll as shown in Figure 6(C).
In the figure (b), when the in-channel potential distribution Web(y) is close to a linear distribution, a short channel effect can be expected.

However, since the electric field is sufficiently strong in the source end subthreshold region of 0.171 m to submicron, a high electric field is formed to the extent that velocity saturation occurs. On the other hand, other parts have a high carrier concentration, so the resistance is small, and there is no depletion of i-carriers near the drain.

These states, S, can be easily understood by considering the in-channel potential distribution Vch (ma) in FIG. 6(D) and the in-channel carrier component 41ρ(ri) shown in FIG. 6(E).

In the above description, the subthreshold region 87 with locally controlled impurity concentration was provided;
This is not necessarily a necessary condition and will be considered further.

FIG. 6F corresponds to the configuration shown in FIGS. 6A and 6B.

a second region I in which the gate region almost covers the channel region;
The first region I continues from the first gate electrode and hardly covers the channel region.

FIG. 6G shows a structure in which light is applied to the first region I, where the semiconductor barriers J, J and the array are located, and no light is input to the second region II, such as the resistive layer R.

In FIG. 6H, the first region I is composed of the series J and Jt7 lays described above, and the second region II is a semiconductor layer or optically variable (resistance) element (resistance) such as a PM bonded PINI, MS junction, or PNPN junction. Photo Variable
In the case of nonlinear P, V, E, the 8th G, 80. , the gate region potential distribution, the channel potential distribution, and the channel carrier distribution shown in the BE diagram change depending on the gate potential distribution of the second region II, and are multiple.
The case is shown in which it is constructed with general P, V, and E elements. In this case as well, in the change in potential distribution between VGI and VO2, there is a region with a large potential distribution at P, V, E, (II) in the second region II, and a small potential drop in the first region I. If the optical input switch is performed while holding the state, high G
■It is possible to drive this device while maintaining operation. Note that a method using leading waves is advantageous in bringing light input to a specific part of each region. Furthermore, the Varj-DPIGFED shown in FIG.
When used as a switch, the channel length may range from several meters to several tens of meters.

Next, according to FIG. 7, as described above, a plurality of J, J, (IX J, J,, intestinal
An example of a Y-shaped optical branch path having resistor layers (R1, R2) in an insulated gate region will be described. The figure 7 shape will be explained with reference to Fig. 7A as a plan view and Fig. 78-E showing cross sections of each part. First, P in Fig. 78
As shown in FIG. 7B, which is the I-P2 cross section, the Evita, axially grown SiC layer or SiC substrate 71 has a gate region insulating film 72, and this insulating film 72
2, a resistance layer R made of poly-Si or crystalline Sj, etc.
1, R2 are formed. Furthermore, the gate region other than the resistive layer is covered with a superconducting metal MHI (MBIL, NBIR) in the common source S-second drain DB channel.

QXJ is connected to the control gate terminal GBI near the source.
, J, (semiconductor barrier), and nXJ, J near the control gate terminal 0 day 2 near the drain voltage.

is located.

On the other hand, in the channel extending from the source S to the first drain voltage, switching from the B channel to the A channel occurs midway.

Assume that the figure-7 channel intersection angle (ψ1+ψ2) is always continuous.

With the elongated region 78 dividing the channel as a boundary, one side is dominated by the potential distribution of the GBI-CB2 system, and the other side is dominated by the GAI
-Dominated by the potential distribution of the GA2 system.

The source S has a depletion layer B1 and an electrode St. The drains D and DB have depletion layers, AB, and electrodes DAt and DBt, respectively.

Electrodes GA 1 and GA2 are provided to control the potential of the gate region connected to the drain OA. Further, electrodes GBI and GB2 are provided to control the potential of the gate region extending from the source S to the drain DB.

” When a voltage is passed and supplied to each terminal, the inversion layer 70
A waveguide depletion layer 73 according to the present invention is generated therebelow. In this Vari-DPIGFED optical branch, there is a passive waveguide (e.g. TazOs layer) on the left side of the figure.
PC(0) and on the right side a similar passive waveguide PC(0)
There are 1) and PG(2).

In some cases, it is undesirable to have a thick layer on the side of the waveguide from the viewpoint of waveguide control.

For this purpose, in this embodiment, a buried insulating layer 75 formed in SiC or the like is provided. This portion can be formed, for example, by high-energy ion implantation of oxygen O, nitrogen N, or the like.

The semiconductor layer 74 between the channel depletion layer ions 73 and the buried insulating layer 75 is a variable adjustment gap. Forming the insulating layer 74 with a small refractive index under the channel in this way is convenient because it can prevent the depletion layer from expanding on the drain side even if the drain voltage is increased.

As a method of not increasing the thickness of the depletion layer in the channel on the drain side, it is possible to gradually increase the substrate concentration by ion implantation or the like as the channel approaches the drain side.

Furthermore, below the passive waveguides PG(1) and PG(2),
Separation↓'S2□□Ah, ah7゜□1□yo Tl-T2□tsux
=T,' As shown in FIG. 7E, when the waveguide portion of SiC or the like is geometrically clearly separated by its oxide film 77 and the flattening insulating film 78, the guided wave becomes It is thought that there will be less leakage.

If a Y-shaped optical branching guide is designed as shown in Figure 7, when the channel formed by electrodes GAI-GA2 is closed, the guided wave will proceed in the direction of the channel 5-DB if it is open; When the channel by GAI-GA2 is open and the channel on the drain potential side is closed by C due to the potential of electrode MBIR, the guided wave travels straight and is output to the waveguide pG(t) on the drain potential side. To go.

Switching of these potential distributions is performed using the Vari-
This can be done based on the principle of turning on and off the DPIGFED channel. However, multiple J and J that have a photosensitizing effect
, and the gate region is formed of a resistance layer, so low voltage driving is possible.
The angle of D bending is such that total reflection is possible, so ψ
There may be a safe design example at around 1 + ψ2 × 5°. When bending a waveguide at a large angle, one must be prepared for leakage light.

In any case, if the optical branching switch shown in FIG. 7 is used, the electrodes GAI-GA2 . A channel switch can be caused by a change in the potential pulse of the electrodes Ge1-GB2, and a channel switch can also be caused by introducing optical input into the gate region.

For example, a waveguide made of superconducting metal such as Ta205.
If it is placed on XJ, J, photosensitive semiconductor layers R1, R2, etc., various optical input logical operations as described with reference to FIG. 6 become possible.

It is also possible to receive the guided wave traveling in a portion other than the Y-shaped branch by a photosensitive Vari-[1 PIGFED, and use the inverter output to invert the voltage distribution in the branch to perform channel switching. We have described the case of forming a variable potential distribution structure consisting of this. In this case, one feature is that the element has a latch action.

Note that when micro-bridge types are used for J, J, the form of static characteristics is different from that shown in Figure 4, but since there is a zero voltage state and a voltage state as well, the difference between them is Transitions can be used.

On the other hand, if we consider the case where a single-crystalline semiconductor layer is provided in the gate region to realize a variable potential distribution, there are many different types, but if we choose a structure that is sensitive to light, we can choose a PN junction,
There are PIN junctions, PNPN thyristor structures, etc. Among these, a latch operation occurs due to a light pulse, and under appropriate bias conditions, the forward OFF state (high resistance state) changes to the ON state S (low resistance state) after passing through the negative resistance region. As already mentioned, a PNPN thyristor structure can be mentioned.

1 This off state S (high resistance state) and off state (low resistance 1
By changing the potential distribution between the gray state and the gray state, it is also possible to switch the optical branch path of the DPIGFED type. If we compare the low resistance state to the zero voltage state in the case of J, JL, and the high resistance state to the sum of the gap voltages of each J, J, in the series J, J, array, the seventh
An operation similar to that described in the figure becomes possible.

FIG. 8 shows an embodiment in which the gate region has a PNPN thyristor structure using a crystal film formed by laser annealing or the like. This embodiment has a configuration that can be easily compared with the embodiment shown in FIG. 7 as a whole.

In this example, since normal temperature operation is possible, the electrode MB
L, MBR, HA, etc. may be ordinary metal electrodes, and the control gate electrode GBI is in ohmic contact with the P layer of the PMPM configuration. Similarly, the gate electrode GB2 is also in ohmic contact with the N layer. The control electrode GAI is in ohmic contact with the P layer,
Control electrode GA2 is in ohmic contact with resistive layer R2.

The shallow ion implantation is configured to allow connection between channels outside the direct reach of the brown potential. Gate control terminals GAl, CA2. It is unavoidable that the potentials supplied to GBI and Cl1I2, the drain potentials VDA and VDB, and the source potential vs are not driven at low voltages as in the seventh illustrated embodiment.

FIG. 8 shows one example of a configuration using PNPN@structure and resistive layers R1 and R2, and it goes without saying that there may be many other types of configurations in the case of semiconductor layers. , Vari-RO FE that adopts a PNPN thyristor configuration in the gate region instead of the optical branch path of the PIGFED.
A T configuration is also possible. J, J, array shown in Figure 5 is PN
It is easy to think of a structure in which a PN thyristor structure is used, or a structure in which J, J, and arrays in FIG. 6 are replaced with a PNPN thyristor structure.
An analogy can be made according to the Vari-DPIGFEII operation described in connection with the figure. In the case shown in FIG. 6, it is necessary to optimally design the resistance layer region 85 covering the channel region and the on-resistance-off-resistance ratio: I', 7q of the PMPM thyristor structure.

can be done.

In each of the above embodiments, Vari-DPIGFED
The structure of the MOSFET was horizontal compared to a normal MOSFET. On the other hand, in comparison with a normal NOSFET, a vertical structure, that is, a structure in which the drain is located in the semiconductor region and does not directly contact the insulating film for controlling the surface electric field, may be adopted. Generally speaking,
These vertical structures, including structures similar to VMO9, are capable of higher voltage operation.

Therefore, when such structures are combined with the present invention,
A high electric field can be applied to a depletion layer waveguide to produce large electro-optical changes.

An example of such a case will be shown and explained in FIG. In the cross-sectional view of the device shown in FIG. 9, various configurations of the substrate portion are possible.

In the case of a single semiconductor, in FIG. 9A, for example, consider that the insulating substrate 31 is a ν(n-) type or π"lp) type substrate, and the drain 82 is a semiconductor such as ', 1 conductor. Also, if we consider a heterostructure, for example, an N intermediate layer 9 of Si is formed on the insulating substrate 81.
It is also conceivable to deposit Si0 layer 93 by epitaxial growth or the like after depositing Si0 layer 93 as a crystalline film.

In the crystal layer 93, there are P-type regions 94a and 134b formed by diffusion or ion implantation.

The n-soil layers 95a and 95b act as source regions (S).

As mentioned above, the n soil layer 32 on the other side is
), the device has n10 layers 82-n single layer or p single layer (133a-Hb-He)-1 layer (94a
, 94b) -n intermediate layer (95a, 95b), and has the impurity storage 4 and material configuration of a normal vertical surface field effect device. Insulation required for surface ``city effect'' 11! i! 9El is made of silicon oxide, silicon nitride, etc., and the voltage component 11i is a voltage component 4j formed between the low resistance portion 87 formed on the insulation 11936 and 98a, 98b. 910, each of the above regions 87, 118a, 98
It is formed by applying a voltage from b.

Various mechanisms can be considered for forming the voltage distribution, and the 111 crystal layer is replaced by the 99. '1110 can be done. In this case, the layers 119 and 910 can be further subjected to a suitable process to form a PN junction, a PIN junction, a Schottky junction, a PNPN switch mechanism, etc.

In such a case, contact portions 97, 98a, 9
By applying various potentials to the insulating film 86
The potential distribution formed between the layers 9'9 and 910 can be changed temporally and spatially at high speed.

Furthermore, the junction structure described in item (d) can also react with high sensitivity to electromagnetic waves such as light and change the potential distribution.

n number of 10λ to 200λ using l-phosphorography
By forming a gap between the positions of 1 and 2 and burying an insulating material or an amorphous semiconductor between the gaps, n pieces of J, J are formed.

can also be formed.

For example, if a voltage distribution mechanism is formed in the region 88 by n J, J, and series resistors, and a voltage is applied from contacts 98a, +17, the series array consisting of n J, J, It is possible to make a transition from the state to a voltage state of n×Δvg. As mentioned above, ΔVg is the gap voltage of J, +: determined by the electrode material. As mentioned above, the transition of these superconducting junctions to the voltage state can also be controlled by an external magnetic field near the junction. Also, game 1
The sixth method for forming a change in potential 1 (j) in the region is
The methods shown in each figure can be applied.

In the configuration shown in FIG. 9A, the portion or region 9
3c is the cloth part 9 based on the same principle as the vertical MO3FET.
3c, an insulating layer 912 having a lower refractive index than this depletion layer 93c is further formed, and the waveguide 93c is connected to 93c from the middle.
It is divided into an L part and a 93cR part.

When a figure 7-shaped waveguide is formed by such division and a light wave kite wave is switched, as mentioned above, generally, if the angle is about 5" or less that allows for total reflection, , the direction of the light wave kite wave can be switched.When performing such a switch function, the waveguide portion 93cL,
The refractive index condition of 93cR is switched to a surface electric field distribution in which one side is right-handed, depending on the potential distribution of the gate region and the source and drain potentials.

As shown in the wtj9C diagram, waveguides 93c and 9 with the same width
14c, gradually approach the point 7 shown in the same figure (B).
After tapering and merging with the shape branch structure, one H4,j of the same width (the combined width of both waveguides)
14, 9° A separation layer 913 is provided to separate the field effect differential and the ear. These can be formed of a suitable insulating material or the like. In order to further improve the optical waveguide conditions with the active guide waveguide described in 2.
It is also conceivable to replace the area around c with a low refractive index layer with less optical loss.

To do this, as shown in Figure 1O, the shaded area 10
It is also possible to change 0 into an insulating material by implanting ions of oxygen, nitrogen, or the like. Even if this is done to improve the waveguide conditions, the characteristics of the vertical surface field effect device can be maintained well. Since the other parts may be the same as the components shown in each of FIGS. 9 and 9, the same reference numerals as in each of FIGS.

Furthermore, in the structure of the device shown in FIGS. 9 and 10, a voltage distribution of 1.1. can also be given to the state of the waveguide in the direction perpendicular to the plane of the paper. ″-Vertical Var
i-DPIGFE (4a construction method of optical branch path using l).

The same concept as explained with reference to 1tS7 and FIG. 8 can be applied.

In FIGS. 1 and 2, the explanation has been made assuming that the substrate is in the form of a plate made of crystals such as SiC.

a-3i:)lliJ, a-9iC:H membrane noyouna, low? Depending on conditions, it is also possible to use a semiconductor that can be formed on an insulating film or on an insulating substrate. Further, a semiconductor layer such as S'iC or CdS can also be formed as a polycrystalline material by sputter deposition or the like.

In addition to the semiconductors that can be formed at low temperatures as described in the above two or three examples, there are various types of semiconductor films that can be formed at low temperatures depending on the selection of materials and thin film formation methods. These semiconductor 8I films can also be used as elements of each embodiment of the present invention or similar structures. Also, as a matter of course, it can also be used as a part of the thin film for the 1st place distribution in the 1 area. -':,',:, , direction, Sl is 1.2J1m ~9
J1m (7) High transparency in the infrared range/). Therefore, this material can be used as an active waveguide in the infrared region in the present invention.

By the way, when considering 0E-1C for the N-type channel in MOSFET in 4.2, it is desirable that the light generating element can be formed into a monolithic structure.

On sapphire substrates and spinel substrates, the SO8 structure of Si is formed, and at the same time, compound semiconductor crystals are grown.

Therefore, as an idea based on what I wrote,
A light emitting device (e.g. light emitting diode, I' conductor DH laser) on a sapphire substrate and a Var in an SOS configuration.
There is a connection with i-DPIGFED. As mentioned above, Ta205 has a proven track record as a waveguide.

If there is a thin 5I02 film on the surface of this Taz0511ff, part of the exposed 1ζ light can leak through it, and -
The light input to J, J, and the shade of the 4′-guided 2-” body barrier becomes 11 diodes.

Another important idea is the use of SiCJ, % plates, or SiC epitaxially grown films. Si
C is a highly heat-resistant semiconductor compared to Si, and its sublimation point and melting point are significantly higher, making it difficult to manufacture.
It has become possible to epitaxially grow SiC through a carbonized layer of 1.

SiC has 6H type (hexagonal) and 3C type (
There are crystals of cubic. The 8H type has an energy camp of about 3, OeV, and an electron mobility of 480c+m2/at room temperature.
Vsec, 3C type has energy gear approximately 2.2e
V, electron mobility is 1000 cm27 Vsec.

Epitaxial growth using vapor phase growth on SiC substrates or Si or sapphire substrates has also been attempted.
Under normal conditions, a good crystalline film can be obtained and sec, (Es=
2X 105V/am), and for GaAs, Vs=2
X107cm/sec, (Es=3X 105V
/ cm). It is also characterized by high thermal conductivity.

A Si Sol structure can also be created on a SiC substrate by laser annealing. SiC is a semiconductor that can be processed at high temperatures compared to other compound semiconductors, and is good at relatively high temperature processes and 1!7Il staining.

Considering OE-[:, the SiC PN junction is an old-fashioned light-emitting diode, and the light-emitting source can be easily made monolithic. The spectral mode of emission varies depending on the doping impurity and the center within the band.

In addition, SiC itself is doped with impurities and the MO3 composition is Sl
The SiC MO3I transistor can be modified to form a Vati-DPIGFED using J and j of the present invention.

, SiC is a transparent semiconductor, so visible or infrared light with energy smaller than the gate gap of SiC passes through the substrate and enters the gate J. , J, can be optically excited, resulting in a highly reliable device configuration. Propagation through a waveguide can be used to introduce optical input.

In addition, Va i i -DP with light wave kite wave powered by two people.
When it is desired to drive an IGFED, an island of the same conductivity type as the source and train is provided in the channel to create a dual-gate structure, and the gate section is also provided with J, J, P, V, E, and layers separately for each channel. Assuming that you have placed
It also becomes possible to turn on an FET with optical input only by two people.

These also provide diversified functions and improved performance as constituent elements of the OE-IC.

- As mentioned above, the Vari-DPIGFE of the present invention
By using an optical branch path based on D, the traveling direction of light waves from one light source can be changed using a switch mechanism.

Therefore, by connecting these branch paths in a branch-like manner, it is possible to develop a path under the optical path in a tree-like manner. Such a device will play an important role in the 0E-IC configuration-1-1rii, which utilizes signal transmission by optical kite waves in a solid state.

In addition, according to a person's invention, Vari-
By configuring 0E-Summer C by combining it with DPIGFED, etc., it is possible to diversify functions and improve the speed of parallel processing.

[Brief explanation of the drawing]

Figure 1 is a theoretical cross-sectional view of a branch path and modulation of optical power by the surface field effect device (Vari-DPIGFED) with a variable potential distribution insulated gate structure of the present invention, and Figure 2 is a cross-sectional view of multiple optical power outputs from one optical power element. A schematic configuration diagram of the Vari-Dρ GFED optical branching path of the present invention that branches and distributes the to-be-chilled F-wave into the branching path of the device shown in FIG. An explanatory diagram of an example of a pulse sequence. Fig. 4 is an explanatory diagram of a typical Ij-Vj static '4□ν characteristic of a Josephson junction. Fig. 5 is an illustration of an array in the case of a series array configuration method of J, J, and junctions. Figure 6 is an explanatory diagram of the potential distribution of
Vari-DPIGFED with part, and further generalized J, J, ten P, V, E, structure, first, second P, V,
E, each explanatory diagram when the structure is made into a gate region, Fig. 7 is a schematic configuration diagram of an embodiment in which the Vari-DPIGFED optical branch path is configured in a Y-shape, and Fig. 8 is a diagram in which the structure is replaced with a J, J, junction. Adopting a PNPN configuration, this and jI! Y-shaped Var consisting of , antilayer, and metal electrode
A schematic configuration diagram of an embodiment in which an i-DPIGFED optical branch path is configured, FIG. 9 is an n"-p-n--n"V
A cross-sectional view of the ari-DPIGFED and an explanatory diagram of its active guiding waveguide.
- Structural sectional view of another example using DPIGFED. It is. In the figure, 1.63, 71.91 are the substrates, 2, 84, 72.
98 is a gate insulating film; 3, 85. R, R1, R2, 9
9,910 is a semiconducting film or a resistive layer; 4. Ell, 95
a, S is source, 5, 62.92. D is Dray 7, B,
? , GAi, and GBi are the electronic designated agents established in the Game 1 area.

Claims (1)

[Claims] 1) In an insulated game I type surface field effect device. There is an insulating film covering the semiconductor region, and a gate region is provided on the other side of the insulating film to enable a non-uniform potential distribution for controlling the surface electric field of the semiconductor region, and a gate region is provided on the other side of the insulating film to control the surface electric field of the semiconductor region. A surface field effect device characterized in that a part of a semiconductor region is used as a guiding wavepath. 2. The surface field effect device according to claim l), characterized in that ≧1', the surface field effect device has a plurality of terminals for applying voltage or passing current to the conductor i. device. 3) A surface field effect device according to claim 1) or 2), which has a non-uniform impurity source density distribution portion in order to control the surface electric field of the semiconductor region. Characteristic surface field effect device.