JPS5938747B2 - Semiconductor device and its usage - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device whose main purpose is to perform high-speed switching and control oscillation at high speed.

Conventional field-effect transistors (hereinafter referred to as FETs) control current (channel current) due to surface charges induced by voltage applied to a gate provided on a semiconductor, and in principle, the current The characteristic is a single value function of voltage and has no history characteristic.

That is, if the voltage application state changes, the current changes accordingly, and there is no switching effect due to history. Furthermore, oscillation characteristics cannot be obtained in principle. On the other hand, a tunnel diode with a diatron negative resistance that utilizes the tunnel effect in a degenerate PN junction has attracted much attention for its high frequency characteristics because it utilizes the tunnel effect. However, there are problems with the reproducibility of the device and compatibility with other integrated circuits, so it is not currently being used on a large scale. An object of the present invention is to organically combine a conventional field-effect FET and a tunnel diode to enable integration, and to provide a semiconductor device that has unprecedented high-speed switching and oscillation functions. . To achieve this objective, the present invention provides at least three sources, a source, a drain, and a gate.
In a field effect transistor having two regions, a tunnel junction made of a degenerate semiconductor Pn junction is formed in one or both of the source region and the drain region.

Here, a degenerate semiconductor refers to a semiconductor in which the impurity concentration approaches or increases the effective density of states, and the Fermi unit is located in the conduction band if it is n-type, or in the valence band if it is p-type, If a junction is formed with a degenerate semiconductor for both n-type and p-type semiconductors, a tunnel junction can be created, and the tunnel junction of the present invention refers to this. For example, the impurity concentration required to degenerate an n-type semiconductor is 2×10
For 113Si, 6×101'3 is the standard. Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows a first embodiment of this invention, {
100} shows a field effect transistor whose substrate 1 is a P-type semiconductor.

On this (100) plane semiconductor substrate 1, recessed n+ type semiconductor regions 2 and 3 are provided. Moreover, above the deposit regions 2 and 3, degenerate P+ type semiconductor regions 4a and 4
b, and a tunnel junction 8 is formed between the regions 2, 3 and the region 4. A V-shaped groove is cut into such a semiconductor layer, and a gate electrode 6 (terminal G) is provided on the surface of the removed semiconductor region with an insulating film 5 interposed therebetween. Area 2, 3
Contact is made with an n+ type diffusion region 7.

From the regions 2 and 3 and the two regions 4a and 4b, terminals S, D, B, .B2 are formed as shown in the figure. As described below, the operation of this element is to use the Bl and B2 terminals as bias terminals, but one way to use them is to use S and B2 as drains, and another way to use them is to use D and B2 as bias terminals.
The solution is to use Bl as the source and drain. Furthermore, it is also possible to use B2, Bl or Bl, B2 as the source and drain. In addition, in some cases, S,
If one side of D is used as a source and the other as a drain, it operates as a normal MOSFET. Such an element is
It can be formed using conventional IC technology.

That is, an n+ layer 2 is formed on a (100) plane P-type semiconductor substrate 1.
. Insulating film 5,
A conductive gate 6 is attached. For example, in the case of Si, this selective etching is carried out using a hydrazine aqueous solution {
Since the etching rate for the {100} plane is much higher than the etching rate for the {111} plane, when a {100} plane wafer is etched using a mask,
111} side faces are obtained.

-V compound semiconductors such as GaAs can also be subjected to anisotropic selective etching. This n+ layer 2, 3, P+4
For the epitaxial growth of a and 4b, even if an evaporation method in an ultra-high vacuum or a molecular beam epitaxial method is used, P+-n
+ It is possible to form a steep joint with no sagging on the joint surface.

In the structure of FIG. 1, contacts in the second and third regions are obtained by n+ diffusion 7 through the P+ layer.

The operation of the above embodiment will be explained using FIG. 2.

FIG. 2a is for explaining the switching operation of the device according to the present invention, and the N-shaped solid line shows the current-voltage characteristics at the tunnel junction 8, and the dynatron-type negative resistance due to the tunnel effect is shown in FIG. is proposed. Here, for convenience of explanation, the channel resistance formed on the surface of the region 1 is considered to be the load of the tunnel diode having the tunnel junction 8.
In this case, the voltage VD applied to the channel section and the flowing current 1
The relationship with 0 is 0 ゛ L'' ゛ in the low voltage region.
− − − is the gate voltage.

is a single-valued function of Here, Z is the channel width, L is the channel length, μn is the electron surface mobility, Cl is the gate insulating film capacitance, and VT is the threshold voltage. For simplicity, if T: 0V, the channel resistance RC-VTV/10 is Z, nC
iVO, which is inversely proportional to the gate voltage.

Hereinafter, in Figure 1, S and D are source and drain terminals, and B
Consider the case where 2 is used as a power supply (bias) terminal.

Now, when the bias of region 4b is fixed at point a as shown in Figure 2a, the channel resistance of the FET, which is considered as a load, can be changed by the voltage applied to the gate 6, and as the channel approaches the on state, the load The straight line will stand, and as it approaches the off state, the load straight line will bounce.

That is, the state of the load curve 1 can be realized by appropriately adjusting the gate voltage. In this case, they intersect at three points B, c, and d, but point b becomes an unstable point, and either point C or d becomes an operating point. Here, when the state is set to C, if a gate bias is applied so that the channel becomes more conductive than the channel resistance which becomes the load linear state of 2, the operating point moves to around d, and the gate When the bias is returned to the original load curve state of 1, point d becomes the operating point, and the operating point is switched from c to d. Similarly,
If d is the operating point, if a voltage is applied to the gate so that the channel becomes non-conducting beyond the channel resistance that is in the load curve state of 3, the operating point will move to near C, and the gate bias will change to the original value. When the load curve is set to 1, C becomes the operating point, and the operating point is switched from d to c. Actual operation can be performed using pulses. The output is from the drain terminal D through the resistor, and the voltage corresponding to the C state and the d state,
It can be taken out as E, f. The switching operation in this case is based on the tunnel effect, and extremely high-speed switching is possible. Furthermore, as shown in Figure 2b, if the channel resistance expressed by the load line is 4, the negative resistance of the tunnel diode is larger,
Oscillation is obtained.

In this state, if the channel resistance is made non-conducting as shown by the load straight line 5, the operating point becomes g.
to h, and oscillation is stopped. That is, oscillation can be started and stopped by the gate voltage. Third
The figure shows a second embodiment of the invention.

This is because in the first embodiment (FIG. 1), a part of the P-type semiconductor substrate is used as a channel forming part of the FET, whereas a region 10 on the n+ substrate 9 in the {100} orientation is . In this structure, the exposed slope of the P layer 10 is a channel forming part of an FET in which a gate electrode 6 is provided with an insulating film 5 interposed therebetween. In the degenerate n+ layer and the degenerate P+ layer, terminals D and B2 are formed as shown. Furthermore, a terminal S is formed on the n+ type substrate 9. That is, the n+ type substrate 9
acts as a source, and the slope obtained by anisotropic selective etching of the P region 10 above it becomes the channel forming part of the FET structure, and the regions 11 and 12 form a degenerate semiconductor NP junction, forming a tunnel junction 8. Form. The operating principle of the FET using the n+ type substrate 9, the P region 10, the degenerate n+ region 11, and the degenerate P+ region 12 as a source, a channel forming portion, and a drain in this embodiment is the same as that in the first embodiment. In FIG. 3, a part of the P+ layer 12 of the uppermost semiconductor layer, which is one of the degenerate semiconductor layers forming the tunnel junction, is removed by selective etching in order to make ohmic contact with the N+ layer 11. FIG. 4 shows a third embodiment of the present invention, which attempts to obtain a structure equivalent to that of the first embodiment using a type having a planar gate 6. In FIG.

That is, n +
A region 2, and n+ and P+ regions 3 and 4 are provided, terminals S, D, and B2 are formed in each, and a gate electrode 6 is provided via an insulating film 5 so as to bridge these regions 2 and 3. be. Moreover, the degenerate P+ is caused by diffusion on the surface of the degenerate n+ region 3.
A region 4 is formed to create a tunnel junction. This diffusion is done using DSA (DiffuslOnSelfAllgnme).
nt) can be easily formed using technology. In this case, S, B
If 2 is used as the source and bias terminal, the operation will be exactly the same as that shown in FIG. FIG. 5 shows a fourth embodiment of the invention.

In the same figure, the conductive gate 3 is In2O3, snO2
, made of a translucent conductive material such as polysilicon. According to this embodiment, the light irradiation 17 is applied to the channel portion.
By doing so, a photoexcited carrier can be generated and the channel resistance can be reduced. in this case,
Set the bias of B2 terminal and G terminal appropriately and
When the operating point is brought to point c by setting the load straight line state 1 in FIG. a, the operating point can be moved to point d by light irradiation, and switching can be performed.
Also, set the bias of the B2 terminal and the G terminal to
When the load curve 5 in FIG. b is maintained, oscillation can be caused by light irradiation, and oscillation can be controlled by light input. FIG. 6 shows a fifth embodiment of the present invention, which has the same structure as FIG. It has a means 16 and is adapted to function as a non-volatile semiconductor memory depending on the polarity or magnitude of the charge in the charge holding means 16.

The memory structure has a double structure in which an insulating film 14 made of SiO2 or the like is attached on the channel forming part, and an insulating film 15 having a trap such as Si3N4, Al2O3 or the like as a charge retaining means is formed thereon. Further, a structure in which grains of conductive material such as MO, W, polycrystalline Si, etc. are attached on the first layer insulating film 14 as a charge retention means and the second insulating film 15 is covered thereon, that is, a floating gate structure, etc. is possible. Writing and erasing into the memory can basically be performed by applying appropriate positive and negative voltages to the gate electrode. In this case, by applying a large positive voltage to the gate 6, electrons can be injected into the charge holding means 16 and stored.
Conversely, apply a large negative voltage to the gate or set the gate to 0.
Holes can be injected and stored by applying a large positive voltage to the second and third regions with the voltage set to V to cause an avalanche at the junction with the first region. The structure shown in FIG. 6 allows the operation of the present invention to be performed according to the stored contents. In the description of each embodiment so far, the semiconductor region including the channel forming portion is assumed to be a P-type semiconductor, but the same explanation holds true even if this region is an N-type semiconductor by reversing all polarities.

Further, the semiconductor constituting the present invention may be an elemental semiconductor such as Sl or Ge, or a compound semiconductor such as a -V group semiconductor.

The gate insulating film 5 is made of SiO2, Si3N4, Al2O3,
Any insulating material such as Ta2O5 may be used, and any conductive material may be used as the material forming the gate, such as 1n203,s
Translucent conductive materials such as n02, thin polycrystalline Sl, etc. can also be used. Furthermore, in FIG. 1, an insulated gate type structure is shown above the channel forming region, but a Schottky gate type structure in which a conductive material is directly attached to the semiconductor surface of this channel forming region also has the same operating principle as described above. Operation is possible. As described above, the present invention can provide a semiconductor device capable of high-speed switching and oscillation by forming a tunnel junction in a field effect transistor. Therefore, according to the semiconductor device according to the present invention, firstly, the FET
It has become possible to integrate a tunnel diode and a tunnel diode.

Second, it is possible to obtain a semiconductor device having high-speed switching and oscillation functions that have not been seen before. The third feature is that it can be manufactured using conventional IC technology and can also be constructed using a multilayer epitaxial semiconductor substrate in an ultra-high vacuum. The fourth feature is that the high-speed switching action and oscillation action can also be controlled by light.
The fifth feature is that conventional non-volatile semiconductor memory can be incorporated. Therefore, to summarize the advantages of the present invention, the structure of the present invention can realize high-speed switching action and control of oscillation characteristics that have not been achieved with conventional field effect FETs, and moreover, can be achieved within the scope of conventional 1C technology. It is easy to manufacture, and its operations can be controlled using light, which has the great advantage of having many applications in semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view showing the first embodiment of the present invention, and the second
FIGS. A and B are explanatory diagrams showing the operating principle of the semiconductor device according to the present invention, and FIGS. 3 to 6 are explanatory diagrams of second to fifth embodiments of the present invention. 1... P-type semiconductor substrate portion, 2... N-type degenerate semiconductor region, 3... N-type degenerate semiconductor region,
4, 4a, 4b...P-type degenerate semiconductor region, 5.
...Insulating film, 6... Conductive gate, 7.
...n+ diffusion region, 8...tunnel junction, 9...n+ semiconductor substrate part, 10...
P-type semiconductor region, 11...n-type degenerate semiconductor region,
12...P-type degenerate semiconductor section, 13...
Semi-transparent gate, 14...first insulating film, 15.
. . . second insulating film, 16 . . . charge retention means, 17 . . . incident light.

Claims (1)

[Scope of Claims] 1. A field effect transistor having at least three regions, a source, a drain, and a gate, including a tunnel junction formed of a degenerate semiconductor Pn junction for either the source region or the drain region. A semiconductor device characterized by: 2. In a field effect transistor having at least three regions: a source, a drain, and a gate, a degenerate semiconductor Pn is used for both the source region and the drain region.
A semiconductor device characterized by having a tunnel junction formed by a junction. 3. A semiconductor device according to claim 1, characterized in that the gate insulating film has charge retention means and functions as a nonvolatile memory. 4. A semiconductor device according to claim 2, characterized in that the gate insulating film has a charge retention means and functions as a non-volatile memory. 5. A field-effect transistor having at least three regions: a source, a drain, and a gate, a semiconductor device comprising a tunnel junction formed of a degenerate semiconductor Pn junction for either the source region or the drain region. A method of using a semiconductor device, wherein switching or oscillation is performed by applying a predetermined bias to the tunnel junction and applying gate bias or irradiating light. 6. In a field effect transistor having at least three deposit regions, a source, a drain, and a gate, a semiconductor device characterized in that it has a tunnel junction formed of a degenerate semiconductor Pn junction for both the source region and the drain region, A method of using a semiconductor device, comprising applying a predetermined bias to the tunnel junction and applying gate bias or irradiating light to cause switching or oscillation.