JPS6012593A - Solid recording/reproducing apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state recording and reproducing device for recording and reproducing audio signals in a solid-state storage element.

[Technical background of the invention and its problems] Conventionally, recording and reproducing devices use magnetic tapes, disks, etc. as storage media, and convert changes in the amplitude of an audio signal into changes in the strength of a magnetic field or the amplitude of a sound groove. Tape recorders and record disks are known that convert changes in size and store temporal changes in association with the running direction of the tape or disk.

However, in such conventional recording and playback devices that have moving parts, the performance of the magnetic head, magnetic tape, needle, etc. has a negative effect on the dynamic range and distortion rate of the signal, and the running speed that drives the magnetic tape or disk has an adverse effect on the dynamic range and distortion rate of the signal. System performance had a negative impact on signal frequency characteristics, wow and fluff, noise, etc. In addition, the lifespan of magnetic tapes and disks as storage media is finite, and furthermore, it is difficult to determine the exact position of the recorded signal on the storage medium. The disadvantage was that it was not easy.

In addition, in order to eliminate the drawbacks of conventional recording and reproducing devices having movable parts, solid state recording and reproducing devices using solid state memory elements as storage media have been published in patent publications, etc. All of these merely disclosed theoretical possibilities, and did not take into account the ease of use as a concrete device. For example, the storage capacity of a solid-state memory element within the main body of a solid-state recording/playback device is limited to a predetermined value, and consideration is not given to expanding the storage capacity or transferring data from the solid-state memory element within the main body. It wasn't.

[Object of the invention] The present invention has been made in response to such conventional circumstances,
A highly practical solid-state recording and playback system that does not cause wow and flutter or level fluctuations, and can display the recording and playback operation to the solid-state memory element in the memory pack when a memory pack containing a packaged solid-state memory element is inserted into the main body. The purpose is to provide equipment.

[Summary of the invention] FIG. 1 is an overall configuration diagram showing the configuration of the present invention.

In the figure, the output of an encoding means 2 for encoding an audio signal input to an input terminal 1 is stored in a first storage means 3 for storing the audio signal encoded by this encoding means 2. The encoded audio signal stored in the first storage means 3 is decoded by the decoding means 4 and output to the output terminal 5. Further, a memory pack 10 having a second storage means configured independently of the first storage means 3 is connected to the main body via the connecting means 6, and the memory pack 10 is connected to the main body. It is detected by the memory pack detection means 7, and based on the output signal of the memory pack detection means 7, the first display means displays that the memory pack 10 is connected to the main body. Further, the second display means 3 indicates that the entire storage area of the second storage means in the memory pack 10 is divided into a plurality of parts, and storage in or reproduction from each partial area is being performed.
- Indicated by 9.

[Embodiment of the Invention] The details of the present invention will be described below with reference to an embodiment shown in the drawings.

2 and 3 are perspective views showing the appearance of one embodiment of the solid-state recording and reproducing device according to the present invention, and FIG. 3 shows the outer cover 38 of the solid-state recording and reproducing device 20 of the present embodiment with the outer cover 38 facing backward. FIG. 3 is a perspective view showing a state in which the inside is visible after being shifted.

In FIGS. 2 and 3, reference numeral 39 denotes a storage element (hereinafter referred to as a control device for storing control data) that stores encoded audio signals and is built in the main body of the solid-state recording and reproducing device 20 and is made of, for example, RAM. The storage area of the audio data storage element 39 is divided into a plurality of partial areas, and the first address of each partial area is the control storage. It is stored in advance in the element.

Reference numeral 28 indicates a display *:r (distinguished from other types of indicator lights described below) corresponding to each partial area of the audio data storage element 39 or the audio data storage element 4-child in the memory pack described later. (referred to as “marker indicator light”)
It is. This marker indicator light 28 lights up corresponding to a partial area read out in accordance with recording or playback to each partial area of the audio data storage element or a skip or repeat operation described later, and is turned on in response to recording or playback to the partial area. Displays playback, skip, and repeat operations.

Reference numerals 33 and 34 indicate indicator lights indicating that the storage capacity of the audio data storage element 39 is nearing its end. In this embodiment, the indicator light 33 has a storage capacity of 20
In this embodiment, the indicator light 34 is turned on 10 seconds before the storage capacity is reached.

Further, in this embodiment, separate from the three audio data storage elements housed in the main body, for example, RAM or 0M
The memory pack inserted through the memory pack insertion port 35 is connected to the connection terminal 40 and connected to the main body. electrically connected. The indicator light 29 is an indicator light that indicates that the memory pack is inserted into the main body and recording to or reproduction from the memory pack is in progress.

Reference numerals 21 to 27 indicate switches for performing various operations of the solid-state recording and reproducing device 20, and reference numeral 21 indicates a recording operation to the audio data storage element 39 in the main body, and a recording operation by inserting the memory pack into the main body. The audio data storage element 3 of
This is a recording/cobby switch used when performing a recording operation to the memory pack following the recording operation to the audio data storage element 39, or when performing a copy operation by transferring the audio data stored in the audio data storage element 39 to the memory pack. , this recording/
When the copy switch 21 is operated, the indicator light 30 lights up.

Reference numeral 22 is a playback switch for playing back the recording signal recorded in the audio data storage element 39, and when the playback switch 22 is operated, the indicator light 31 lights up.

Reference numeral 23 is a cue switch for cueing operation, and when this cue switch 23 is operated, the partial area being played back in the audio data storage element 39 is skipped and the recorded audio signal is transferred to the next partial area. Reproduce.

The symbol @24 is a skip switch corresponding to fast forwarding in a conventional tape recorder. When this skip switch is operated, the marker indicator light 28 blinks sequentially, for example every 0.4 seconds, and the audio data storage element 39 is The first address of each partial area is read out one after another. Then, with this skip switch 24 turned OFF, recording or reproduction is possible from the first address of the partial area next to the current partial area.

Reference numeral 25 is a repeat switch corresponding to the rewind switch of a conventional tape recorder, and by operating this repeat switch 25, the skip switch 24 is activated.
In other words, when the audio data storage element 39 or the memory pack is connected, the marker indicator light 28 changes from the last address of the audio data storage element 39 in the memory pack, for example, 0.4. It blinks sequentially every second, and the three audio data storage elements or the partial areas of the audio data storage element in the memory pack are sequentially read out from the rear address. When the repeat switch 25 is turned OFF, scanning of the partial area of the audio data storage element 39 or the audio data storage element in the memory pack is completed, and recording starts from the partial area next to the partial area at the time of stop. Or playback becomes possible.

Reference numeral 26 is a stop switch that instructs to stop each operation, and when this switch is operated, the indicator light 32 lights up.

Reference numeral 27 is a power switch of the solid-state recording and reproducing device 20. Also, numeral 36 is a built-in microphone, and numeral 37 is a built-in microphone.
is a headphone jack, and 41 is a built-in speaker.

The functions of the respective switches in the embodiment shown in FIGS. 2 and 3 will be briefly described below.

(1) Recording mode 8--This mode represents the case where recording is performed sequentially from the first address of the audio data storage element. In this case, by externally attaching the memory pack, it becomes possible to expand the storage capacity of the storage element within the main body.

Further, the marker indicator lights 28 are lit sequentially from number 0 in proportion to the recording time to indicate recording.

(2) Skip/record mode This mode represents the case where an arbitrary partial area of the audio data storage element is selected and recording is performed from the beginning address of this partial area. In this case as well, by using a memory pack, it is possible to expand the storage capacity of the audio data storage element within the main body. It is also possible to skip a partial area of the audio data storage element of the memory pack.

The marker indicator lights 28 light up one by one in a short time starting from number 0, stop at the skip OFF position, and when recording starts from this position, recording to the relevant partial area ends as in the recording mode described above, and the next The marker indicator lamps 28 are lit one by one each time the partial area is moved.

(3) Repeat/record mode This mode is similar to the skip/record mode, but the recording position is selected from the end address of the audio data storage element. The fact that the storage capacity can be expanded using a memory pack is the same as in the recording mode and skip/record mode.Furthermore, it is also possible to repeat a partial area of the audio data storage element in the memory pack. It is.

The marker indicator lights 28 are lit up one by one at high speed, starting from the marker indicator lights 28 with the larger number and moving towards the smaller number, as an indicator of the desired location. When recording is started by turning off the repeat operation, the operation of the marker indicator light 28 is the same as in the recording mode.

(4) Reproduction mode This mode represents the case where the audio data is reproduced sequentially from the first address of the storage element. The ability to expand the playback capacity using a memory pack corresponds to the recording mode.

The marker indicator lights 28 are sequentially lit starting from number 0 in proportion to the playback time, as in the recording mode.

(5) Skip/Reproduction Mode This mode represents the case where reproduction is performed from the beginning address of an arbitrary partial area of the audio data storage element. In this case as well, the storage capacity of the audio data storage element can be expanded by externally attaching a memory pack. A skip mode within a memory pack is also possible. - The marker indicator lights 28 are sequentially lit one by one starting from number 0 in a short period of time, similarly to the skip recording mode described above. On the stage where the skip is stopped and the playback is performed, the display is sequentially illuminated in proportion to the playback time corresponding to the partial area of the audio data storage element, as in the playback mode.

(6) Repeat/playback mode This mode is similar to the skip/playback mode, except that the playback position is set from an address toward the end of the audio data storage element. By using a memory pack, it is possible to expand the playback capacity corresponding to the recording mode, and repeat operations within the memory pack are also possible.

11- The operation of the marker indicator lamps 28 is the same as in the above-mentioned repeat recording, in which the indicator lamps are turned on in sequence in a short period of time, and the repeat switch 25 is turned on.
The solid-state recording/playback device 20 stops when the playback switch 22 is turned off and starts playback operation, and the operation of the marker indicator light 28 at this time is the same as the operation during playback.

(7) Cue/Reproduction Mode This mode is a mode in which the audio data recorded in the partial area next to the partial area currently being reproduced is read out by operating the cue switch 23. Even in this mode, the use of a memory pack makes it possible to locate the beginning of audio data whose capacity has been expanded.

The operation of the marker indicator light 28 is the same as in the reproduction mode described above.

(8) Copy mode This mode represents the case where audio data recorded in the audio data storage element within the main body is copied to an external memory pack.

Recording is performed in the memory pack sequentially from the beginning of the audio data storage element of the memory pack. Marker table 12 - The operation of the indicator light 28 is the same as in the recording mode.

Next, a specific circuit configuration for realizing the various operation modes described above will be explained.

FIG. 4 is a block diagram showing the circuit configuration of an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration example of the voice detection circuit 61 in the block diagram of FIG. 4, and FIG. 6 is a waveform diagram showing an example of waveforms of each part of the circuit of FIG.

4 to 6, reference numeral 51 indicates the main body of the solid-state recording and reproducing apparatus 20 of this embodiment, and reference numeral 52 indicates a memory pack. The main body 51 and the memory pack 52 are connected by a plug 54.
It is electrically connected via 55. Further, the plug 53 of the main body 51 is provided with an input/output terminal, and can be connected to a microphone 56, a speaker 57, etc., and is electrically connected to the circuit within the main body.

Reference numerals 58 and 59 are amplifiers, which amplify the input signal from the input terminal and output the signal to the speaker 57 via the output terminal.
Amplify the reproduction signal that drives the etc. This amplifier 58
．． Five of them form an analog amplifier 60 in pairs.

For example, the input signal, which is the output signal of the microphone 56, is
The signal is amplified by the amplifier 58 through the plug 53 and input to a low-pass filter (hereinafter abbreviated as "LP F") 62 and a voice detection circuit 61.

This audio detection circuit 61 interrupts the recording operation to the audio data storage element 81.103 when the level of the input signal is below a preset level during recording, and prevents the audio data storage element 81. This is a circuit for preventing wastage of the 103 and for quickly listening to necessary signals during reproduction.

Details of this circuit will be described later in FIG.

The output signal of this audio detection circuit 61 is transmitted to a peripheral input/output controller (hereinafter referred to as "PIO").
76 (hereinafter abbreviated as ``), and the central control circuit (hereinafter ``
The output signal of the LPF 62 is one of the seven control signals (abbreviated as ``CP tJ'').
The output signal encoded by the delta modulation circuit 63 is converted into parallel signals of 8 bits each by the serial/parallel conversion circuit 64.

The output signal of this serial/parallel conversion circuit 61 is inputted to an input/output switching circuit 65 and then sent to an address/data/control bus 75.
is output to. The signal from the address/data control bus 75 is input to the parallel/serial conversion circuit 67 via the input/output switching circuit 65, where it is converted bit by bit into a temporally continuous bit-serial output signal. and is input to the delta demodulation circuit 68.

The output signal of this delta demodulation circuit 68 is L P F2O
is terminated with a variable resistor 70 via a slope detector (
(hereinafter abbreviated as 113Dll) 72.

The output signal of this 8072 is a voltage controlled oscillator circuit (hereinafter referred to as “
V C0
73J: A pulse signal with a period proportional to the slope of the demodulated signal is output, and this pulse signal and a signal obtained by dividing this pulse signal by 8 by the frequency dividing circuit 74 are sent to the address/data/control bus 75 and the delta modulation circuit. 63, delta demodulation circuit 68, 15- It is supplied to the serial-to-parallel converter circuit 64, the parallel-to-serial converter circuit 67, the input/output switching circuit 65, etc., and is used as a control pulse signal.

The demodulated output via the variable resistor 70 is input to a muting circuit 71, the voltage level of which is attenuated as required, and output to the speaker 57 via an amplifier 59 and a plug 53.

Reference numeral 81 is a storage element for audio data, for example 256
It consists of 12 bit RAMs. The entire storage area of this audio data storage element 81 is divided into a plurality of partial areas, and from now on, the address data of the starting address of each partial area and the chip number of the storage element in which the partial area exists are combined into a pair of data. In addition, an emergency backup battery 82 is connected to the audio data storage element 81, so that even if the power is cut off, the internal audio data will be volatile. Further, the audio data storage element 81 is connected to an address/data/control bus 75, and exchanges signals with the C16-PU 79, input/output switching circuit 65, and the like.

Reference numeral 83 is a control memory element for controlling addresses for writing and reading audio data into the voice data memory element 81.

This control memory element 83 records the address pointer data of the audio data memory element 81 at the time of starting recording.
12 RAMs for storing address pointer data at the end of recording, 12 RAMs for storing address pointer data at the end of playback, save RAM 87, and the beginning of each partial area of the preset audio data storage element 81. ROM8 that stores the address pointer data of the address
8 is provided. The input/output terminals of each of the RAMs 1 to 2 84 to 87 and the ROM 88 are connected to the CPU 79 via an address data control bus 75, a PI076, and an address data control bus 78. Note that RΔM of the control memory element 83 - - 84 - 87
is connected to the backup battery 82 to prevent stored data from volatilizing in an emergency.

P■o76 has a register and communicates with CPU79 and address.
Data control bus 78 and interrupt signal fD
77 exchange signals with each other, and also accept output signals from operation buttons 80 such as the recording copy switch 21, playback switch 22, cue switch 23, etc. shown in FIGS. 2 and 3.

Furthermore, when the memory pack 52 is connected to the main body 51 via the connectors 54 and 55, the signal line 95 is electrically connected to the signal line 96 that is grounded within the memory pack 52, and the memory pack 52 is connected. This is a signal line for generating various command signals associated with this, and for lighting the indicator light 29 to indicate that recording or playback operation to the memory pack 52 shown in FIGS. 2 and 3 is in progress. The address/data/control bus 75 includes, via a drive circuit 89, a marker indicator light 28 that displays each partial area of the audio data storage element 81, an indicator light 29 that indicates that the memory pack 52 is connected, and the like. The CPU 79 sends necessary drive signals.

Similarly, the conversion signal bypass circuit 75 is a comparison circuit (hereinafter referred to as "C") that compares a preset reference value and address pointer data of a partial area of the audio data storage element 81.
The multivibrator 9 is triggered by the output signal from the C0M91 and the C0M91.
2 and the main body 5 through a drive circuit 93 that changes the output signal of this multivibrator 92 into an appropriate tT drive signal.
Memory element 81 for audio data in 1 Memory pack 5
The CPLJ79
This remaining amount indicator light 94 is driven by a control signal from the controller.

The address/data/control bus 75 is connected to the connector 54
．． 55 to the address/data/control bus 101 in the memory pack 52, and supplies each of the control signals to the sound 19-voice data storage element 103 and the control storage element 97 in the memory pack 52.

Inside the control storage element 97, there is a RAM 98 for storing address pointer data at the time of starting recording to the audio data storage element 103 in the memory pack 52, and
RΔM 99 for storing address pointer data at the end of recording in the audio data storage element 103 in the memory pack 52 and the audio data storage element 103 at the end of the playback operation from the audio data storage element 103 in the memory pack 52 The RAM 100 stores address pointer data.

Note that each RA of the control storage element 97 in the memory pack 52
M■~■98~100 and audio data storage element 10
A backup battery 102 is connected to the RAM in the main body 51 in the same way as each RAM in the main body 51, to prevent stored data from volatilizing when the power is turned off.

By connecting the memory pack 52 described above to the main body 51 via the connectors 54 and 55, the audio data storage element 103 in the memory pack 52 is transferred to the audio data storage element 81 in the book 20. They will be connected in cascade.

Next, a circuit example of the audio detection circuit 61 in the circuit diagram of FIG.
This will be explained using the circuit diagram shown in the figure.

The output signal of amplifier 58 in FIG. 4 is input to input terminal 1 in FIG.
12 to one input terminal of the C0M111. In the input terminal of this C0M111 usage, a variable resistor 114 is grounded to the terminal 113 to which a positive voltage is loaded.
The sliding point of this variable resistor 114 is connected via a capacitor 115.

A reference input voltage is set in advance by the variable resistor 114 and capacitor 115. The output of the C0M111 is connected to the input terminal of the monostable multivibrator 116, and the output terminal 11 of the monostable multivibrator 116 is connected to the input terminal of the monostable multivibrator 116.
9 is connected to PI076 in FIG. 4 above. Furthermore, the logic level of the monostable multivibrator 116 is “1”.
A capacitor 117 and a resistor 118 for adjusting the time are externally attached to the stable multi-vibration break 116.

FIG. 6 is a waveform diagram showing the operation of the sound detection circuit of FIG. 5. Before explaining the overall operation of the solid-state recording and reproducing apparatus 20 of FIG. This will be explained using the waveform diagram shown in FIG.

When an audio signal as shown in FIG. 6(a) is input to the input terminal 112, the variable resistor 114 and the capacitor 115
When the level of the audio signal is higher than the reference voltage level (S in Figure 6) set in , the output of C0M111 becomes logic level "1". Therefore, the output waveform of C0M111 is as shown in Figure 6 (B). As shown in FIG.
When the level is low, a pulse waveform at logic level "O11" is output.

The monostable multivibrator 116 is triggered by the pulse waveform shown in FIG. 6(b), and the time (
During T) in FIG. 6(c), even if the trigger pulse of the COMI 11 reaches a logic level of 0°', the output level of the monostable multi-bi break 116 continues to be at a logic level of ``1''. , as shown in FIG. 6(c), during the first three pulses in FIG. 6(b) where trigger pulses are frequently issued, the monostable multivibrator 116
The output of continues to be at logic level ``1'', and the next (
After the fourth pulse (b) falls, the level of the audio input signal applied to the input terminal 112 is lower than the reference setting voltage level S for a time T set by the capacitor 117 and resistor 118. , the output level of the monostable multivibrator 116 falls to the logic level #OII and remains at the logic level "0" until the next trigger pulse is input.

In this way, the output signal of the monostable multivibrator 116 of this audio detection circuit becomes the 23-rL OII level when the audio input signal is lower than the reference voltage level for a certain period of time, so the recording is performed at this "0" level. The recording is stopped while the level of the audio input signal is less than the reference level by not generating an interrupt signal for the audio data storage element 81.1.
03 can be prevented from being wasted.

Furthermore, since the output signal of the monostable multivibrator 116 itself can be used as an interrupt signal, it is also possible to obtain an automatic recording start function using this audio detection circuit.

Next, the operation of the embodiment shown in FIG. 4 will be explained using the flowcharts shown in FIGS. 7 to 12. In addition, Fig. 7 shows C
8 is a flowchart showing the interrupt operation of the PU 79, FIG. 8 is a skip and repeat operation, FIG. 9 is a recording operation, FIG. 10 is a playback operation, and FIG. 11 is a flowchart showing a recording/playback operation when a memory pack is inserted.

First, by turning on the power switch 27 (step (22) in FIG. 8), the CPU 79 controls the control memory element 8.
Initialize each part according to the program written in the ROM 88 of 3 (step (23))
. That is, the PTO 76 for accepting interrupts, the RAMs 84 to 86 for temporarily recording the address pointer data of the audio data storage element 81, the audio data storage element 81, the data of the serial/parallel conversion circuit 64, etc. are initialized. do.

After the initialization is completed, the solid recording and reproducing bag f&20 enters the stop mode (step (24,)), and the recording switch 21,
Interrupts can be caused by operating switches such as the playback switch 22, skip switch 24, repeat switch 25, stop switch 26, etc., and by a 1-byte signal obtained by dividing the output clock signal of the VCO 73 by 8 by the frequency dividing circuit 74.

The flowchart of FIG. 8 shows the flow when a skip operation or a repeat operation is performed, but for convenience of explanation, the recording operation will be explained first using the flowchart of FIG. 9.

(1) Recording operation When the recording switch 21 is turned on for recording (step (/117) in FIG. 9), the interrupt register reads the interrupt information and issues an interrupt to the CPU 79. CPU
79 executes the interrupt according to the interrupt operation flowchart shown in FIG. 7, and determines which operation command it is.

That is, in the flowchart of FIG.
9 reads the data of the interrupt register of the PTO 76 after being initialized and waits for an interrupt (step (1)
)).

Next, step (2)) to determine whether there is a memory pack.
If there is a memory pack, the operation that accompanies the connection of the memory pack, for example, when the storage capacity of the audio data storage element 81 in the main body is full and the end marker comes out, the audio data in the memory pack 52 is memory element 103 for
The memory pack 52 of RAM ■~■84~86 in the storage element 83 for control and the switching of the storage element to
A series of operations such as switching to the RAMs 1 to 98 to 100 in the memory pack 52 and lighting the indicator light 29 indicating that the memory pack 52 has been inserted are performed (step (3)).

Next, in step (4) to determine the presence or absence of a 1-byte interrupt signal, a 1-byte interrupt signal generated upon operation of the recording switch 21 or playback switch 22 is detected, and the necessary operations are performed for each. For example, when recording,
The audio data converted into 8-bit parallel data using a 1-byte signal by the serial/parallel conversion circuit 64 is sent to the CPU.
Step (11)') 1. :(7)CP
The audio data is recorded from U79 to the audio data storage element 81 (step (12)).

Then, the address data of the audio data storage element 81 is incremented and the recording operation is continued (step (15)), but when the end marker appears or the stop switch 26 is operated, the recording operation is stopped. Perform operations such as clearing the address counter, stopping 1-byte signal interrupts, and writing address pointer data to RΔM85 at the end of recording (step (16)).
.

Also, during playback, the audio data is read out from the audio data storage element 81 to the CPU 79 (step (13)), and then the audio data is transferred from the CPU '79 to the parallel-to-serial conversion circuit 67 ( Step (1
4)) Regenerate the audio signal.

Thereafter, in order to read the next audio data, the address data of the audio data storage element 81 is incremented (step (15)), and at the end of playback, the same stopping process as at the end of recording is performed (step (16)).

In addition, if such a 1-byte signal for recording and playback is not generated, it is determined whether there is a repeat signal (step <5>), and if there is a repeat signal, the control memory corresponding to the repeat operation is A series of processes such as counting down the ROM 88 in the element 83 and sequentially lighting up the marker indicator lamps 28 in the opposite direction are performed (step (17)). Thereafter, the process proceeds to determination of playback after repeat (step (7)), recording (step (8)), etc.

If it is not a repeat operation, it is determined whether it is a skip operation or not (step (6)); if it is a skip operation, the address of the ROM 88 in the control storage element 83, for example, associated with the skip operation is Processes such as brightening the pointer data and sequentially lighting up the marker indicator lights 28 indicating partial areas in the audio data storage element 81 are performed (step ('78)), and the playback continues (step ('78)).
7)) or recording (step (8)).

Next, if it is not a skip operation, or if the processing necessary for a repeat operation or a skip operation has been completed, it is determined whether or not it is a reproduction operation (step (7)).

If it is a playback operation, operations such as accepting an interrupt of a 1-byte signal necessary for the playback operation, starting operation of the VCO 73, and canceling the muting state of the micoating circuit 71 are performed (step (19)), and the next copy is performed. The process proceeds to a determination as to whether the operation is a stop operation (step (9)) or a stop operation (step (10)).

Next, it is determined whether the recording operation is to be performed (step (8)
). In the case of a recording operation, operations such as accepting an interrupt of a 1-byte signal necessary for the recording operation, starting the operation of the VC○73, and activating the muting operation of the muting circuit 71 are performed (step (20)). ), the process proceeds to the next copy operation (step (9)).

After performing the above-mentioned recording or reproduction, or after performing the accompanying processing necessary for recording or reproduction, it is determined whether the operation is a copy operation to the memory back (step (9)). If it is a copy operation, a step (21) of performing operations necessary to transfer the audio data from the audio data storage element 81 in the main body to the audio data storage element 103 in the memory back 52; After the transfer operation is completed, the process moves to a determination as to whether or not it is the next stop operation (step (10)).

The presence or absence of a 1-byte signal (step (4)), the presence or absence of repeat operation (step (5)), the presence or absence of a skip operation (step (6)), and the presence or absence of a playback operation (step (7))
)), whether or not it is a recording operation (step (8)), and whether it is a copy operation or not (step (9)), and finally, it is determined whether or not it is a stop operation (step (8)).
10)), in the case of this stopping operation, the processing necessary for the above-mentioned stopping is performed (step (16)). If it is not a stop operation, the interrupt register is read after initialization again (step (1)) to prepare for the next operation.

The CPU 79 performs the above-described judgment operation, but when the recording switch 21 is turned on, the CPU 79
9 is interrupted by a 1-byte signal, so the 12th
The process moves to a loop with the 1-byte signal in step (4) in the figure, and the CPU starts controlling the recording operation.

Returning to the flowchart of FIG. 9, details of the recording operation of the CPU 79 will be explained.

When the recording operation is determined in step (47), the marker indicator lamp 28 corresponding to the address pointer data written in the RAM 84 in the control storage element 83 lights up (step (48)).

This is the section 31- which indicates the section immediately before the section of the audio data storage element 81 where this recording operation is started 171.

Next, it is determined whether or not there is data in the RAM 85 in the control storage element 83 (step (49)). This judgment is made to determine whether or not a recording operation has been performed before starting this recording operation, and the address pointer data at the end of the previous recording has been recorded in the RAM 85.

And the address pointer data at the end of the previous recording is RA
If the address pointer data is recorded in the ROM 85, the next address pointer data after the address pointer data at the end of the previous recording is read from the ROM 88 (step 50).
, proceed to the next step (51).

If there is no data in the RAM 85, the process also proceeds to step (51), and it is determined whether address pointer data is held in the ROM 88 (step (51)). If address pointer data is held in the ROM 88, the address pointer data held in the ROM 88 is preset in the address calendar 32-ta in the CPU 79 (step (53)). Also, R.O.
If no address pointer data is held in M81'', the address pointer data next to the final address pointer data at the end of the previous recording read in step (50) is preset in the address counter of the CPU 79.

That is, when the skip operation or repeat operation described in 19 is performed by this series of operations, recording is performed from the first address of the partial area next to the partial area selected by the skip operation or repeat operation, and the skip operation or repeat operation is performed. If no operation is performed, even if there is still a recording address in the divided area in the audio data storage element 81 at the end of the previous recording, the next recording operation will always be performed in the next divided area. The recording is made from the first number.

After specifying the recording address in the audio data storage element 81 in this state, the CPU 79 closes the converted signal bypass circuit 66 of the delta modulation circuit 63 and the delta demodulation circuit 68 (Stenb (54)), and also prevents howling. Therefore, the muting circuit 71 is turned on (step (55)).

Further, the operation of the variable clock VCO 73 is started (step (56)), and at the same time, the input/output switching circuit 65 is switched to the modulation side (step (57)).

In this way, the preparation system for recording has been completed, so when an audio signal is applied from the microphone 56 to the solid-state recording and reproducing device in this state, this audio signal is amplified by the amplifier 58 via the tangent line 53. It is applied to LPF62. LPF
After being band-limited to the required frequency band at 62, this audio signal is applied to a delta modulation circuit 63 and encoded into a digital signal.

A part of the audio signal encoded in this way is immediately passed through the conversion signal bypass circuit 66 to the delta demodulation circuit 6.
8 (step (58)), and is demodulated by LPF 6 again (step (58)).
After the band is limited by 9, the slope value of the voltage waveform of J: is detected in 5D72 (step (59)), and according to the magnitude of this slope value, the VCO 73
The oscillation frequency of 3 is changed (step (60))
.

The oscillation pulse of this VCO 73 is used as a clock pulse in the delta modulation circuit 63 and delta demodulation circuit 68 described above.

That is, this delta modulation and demodulation coarsens the clock frequency according to the slope of the waveform to be modulated and demodulated. This is because when modulation and demodulation is performed using clock pulses of a uniform frequency, the modulation and demodulation accuracy decreases where the slope of the waveform to be modulated and demodulated is steep, and on the other hand, it has extra accuracy where the slope is gentle. This is done to maintain sufficient accuracy by increasing the n-clock frequency where the slope is steep, and to lower the clock pulse frequency where the slope is gentle to avoid unnecessary precision. By performing delta modulation and demodulation using a clock pulse frequency proportional to the slope value of the waveform to be modulated and demodulated in this manner, delta modulation and demodulation can be performed with sufficient accuracy depending on the aspect of the waveform to be modulated and demodulated.

35- The oscillation output of the VCO 73 is supplied to the above-mentioned delta modulation circuit 63 and delta demodulation circuit 68, and is also supplied to the frequency division circuit 74.
After being frequency-divided by 8 and converted into a 1-byte signal (step (61)), it is supplied to the CPU 79 etc. via the serial/parallel conversion circuit 64, parallel/serial conversion circuit 67, and address/data/control bus 75, and the audio signal is converted into a 1-byte signal. It is used as a timing pulse for writing or reading signal data into the audio data storage element 81 or the like. In this state, the CPU 79 accepts the aforementioned 1-byte signal interrupt (step (4)
), (62)).

Next, the value of the address counter of the CPU 79 and the value of the ROM 88
It is determined whether the data match (step (63)). CPU79 address counter value and RO
If the data in M88 do not match, the value of the address counter of the CPU 79 is incremented by one address, and the address data in the audio data memory 81 is changed (step (64)). This operation is repeated at 36- until the address counter of the CPU 79 and the data of the ROM 88 match (steps (63) and (64)).

That is, since address pointer data indicating the starting address of each partial area of the audio data storage element 81 is recorded in the ROM 88, when starting recording, each part of the audio data storage element 81 must be Recording is started from the first address of the partial area.

When the leading address of each partial area in the audio data storage element 81 is read out in this manner, an address pointer data number is set corresponding to this partial area (step (65)). At the same time, this set address pointer data is written to RAM 84 (step (6)
6)).

That is, address pointer data at the time of starting recording is recorded in the RAM 84.

At the same time, the marker indicator light 28 corresponding to this address pointer data lights up (step (67)). In this state, the ROM 8th address counter is incremented in preparation for the next recording operation.

(Step (68)).

When the recording address in the audio data storage element 81 is determined in this way, the serial digital signal, which is the output signal of the delta modulation circuit 63, is converted into parallel data (bit parallel data) (step (69)), and the audio data storage element 81 or, if the memory pack 52 is used, the audio data storage element 10 in the memory pack 52.
3, the audio signal is stored in the form of bit parallel data (step 70)).

Next, when writing of 8-bit bit-parallel audio data using a 1-byte signal is completed, the address counter of the CPU 79 is incremented, and the audio data storage element 8 is incremented.
Preparation is made for writing a bit parallel signal to the next address within 1 (step (71)).

In this state, it is determined whether or not there is an end marker indicating that the storage capacity in the audio data storage element 81 is exhausted (step (74)). If the end marker does not appear, it is determined whether or not the stop switch has been operated. (Step (75
)). If the end marker does not appear and the stop switch is not operated (step (75)),
Returning again to step (65), the recording operation is continued after confirming the address of the address pointer data.

In this case, if the address pointer data number set in the previous recording operation and the address pointer data number for the next recording are the same, the RAM in step (66)
(2) Address pointer data is not written to 84.

When recording is to be continued to the next divided area of the audio data storage element 81, step (65
) is incremented, and this incremented address pointer data is written to RΔM 84 in step (66).

In this way, audio data is sequentially recorded into the audio data storage element 81 or the audio data storage element 103.

Next, when the storage capacity of the audio data storage element 81 increases and the end marker appears (step (74)),
This end marker is written into the RAM 84 (step (78)), the interruption of the 1-byte signal is stopped (step (79)), and the presence or absence of a memory pack is determined (step (80)).

If there is a memory pack, recording into the memory pack is performed according to the flowchart of the recording operation to the memory pack shown in FIG. 10, which will be described later. If there is no memory pack, the recording operation must be ended now, so the address counter is cleared (step (81)), and the solid-state recording/playback device enters stop mode and stops its operation (step (81)). 82)).

If you want to stop the storage before the end marker appears, that is, while there is still some storage capacity left in the audio data storage element 81, operate the stop switch 26 (step (75)) to interrupt the 1-byte signal. is stopped (step (76)), and address pointer data at this time is written into RAM 85 (step (77)). That is, the address pointer data at the end of recording is written into R40-AM 85. Thereafter, the address counter is cleared (step (81)) and the stop mode is entered (step (82)), as in the case without the memory pack described above.

Note that the recording time of the partial area is approximately 10 seconds in this embodiment, and the marker indicator lights 28 are sequentially turned on every 10 seconds to display the recorded area.

That is, the 1-byte signal is counted by the CPU 79,
When the preset number of 1-byte signals generated in 10 seconds is reached, the marker indicator lights 28 are turned on one by one. The marker indicator light 28 is converted into a decimal number and driven by a drive circuit 89 connected to the address/data/control bus 75.

(2) Skip recording operation If the user desires to record from an arbitrary Nth partial area, by turning on the stop switch 24,
PU79 accepts the interrupt (steps (6), (25)
)), the operation mode is determined and the process moves to a skip operation (step (18)).

In this case, the CPU 79 sequentially reads data for comparison with the number of 1-byte signals generated within a preset time (10 seconds in this embodiment) from the ROM 88 of the control storage element 83 (step (26)). Based on this data, only one corresponding marker indicator light 28 is sequentially blinked (step (27)).

In this case, in order to ensure accurate operation by the user, the marker indicator light 28 is set to blink at a rate of one marker every 0.4 seconds in this embodiment.

When the marker indicator light 28 lights up to the point where the user desires to record, step (28) is performed to stop the skip operation.
)), the incrementing operation of the address counter of the ROM 88 is stopped, and the read data is held in this state (step (29)).

To record in this state, perform the recording operation described above and set the recording switch 21 to 0NL (step (47)).
Hereinafter, the recording operation will be performed according to the flowchart shown in FIG.

In this case as well, it is determined in step (51) whether address pointer data is held in the ROM 88, and if address pointer data is held,
That is, when a partial area of the audio data storage element 81 is selected to perform a skip operation and start a recording operation, the address pointer data of the ROM 88 is transferred to the CPU 79.
Step (53) to preset the address counter of
), since recording is started from this address, recording is performed from the beginning address of the partial area of the audio data storage element 81 selected by performing the skip operation. The subsequent recording operation is the same as in normal recording mode.

(3) Repeat recording operation In this case, when the user wants to record the audio signal from the end of the divided area of the audio data storage element 81 first, the partial area can be recorded by operating the repeat recording operation 25 for convenience. This function provides a function to quickly select the position of a desired partial area by reading out from the larger address at high speed.

That is, by turning on the repeat recording operation 25 (steps (5), (3/I)), the CPU 79 starts repeat processing (step (143-7)). In this case, if a memory pack 52 is connected, in order to start the repeat operation from that memory pack 52, the presence or absence of the memory pack 52 is first determined (step (35)); The memory pack indicator light 29 will light up in step (40).
), the control memory element 83 in the main body 51 is connected to the memory pack 5
2 (step (41))
), step (42)) of sequentially reading address pointer data from the ROM 88 in the control storage element 83. However, in this case, the address pointer data is read out sequentially by counting backwards from the larger to the smaller.

Next, in response to reading of the address pointer data in the ROM 88, the marker indicator lights 28 blink sequentially from the larger number to the smaller number. The read speed in this case is the same as the read speed in the skip operation (step (43)).

In this way, the partial areas of the audio data storage element 103 in the memory pack 52 are sequentially read out, and it is determined whether the reading in the memory pack 52 is completed based on the presence or absence of the end marker. )
), if reading from the memory pack 52 is not completed, the same operation is repeated until reading from the memory pack 52 is completed.

When the end marker is detected and it is determined that reading of the memory pack 52 is completed (step (44)), the control memory element 97 of the memory pack 52 is transferred to the control memory element 83 in the main body 51. Switch (step (/1.5)). Simultaneously with this switching operation, the memory pack indicator light 29 goes out (steps (4, 6)).

Subsequently, the ROM 88 of the control memory element 83 in the main body 51
The address pointer data is sequentially read from the address pointer data from the larger number (step (36)), and in accordance with this reading operation, the marker indicator lamps 28 blink sequentially from the larger number (step (37)).

If the repeat operation is continued in this way, the above operation is repeated and the repeat switch 25 is turned OFF.
If it has been F (step (38)), at this point R
Stop subtracting the OM88 at1no pointer data,
The read address pointer data is held (step 393 and subsequent steps).The recording operation from this stage is the same as in the case of skip recording, and is performed according to the flowchart in FIG.

(4) Repeating recording and stopping operations In this case,
This is a case where each of the above-mentioned recording operations is performed multiple times within the capacity of the data storage element.

That is, when recording a plurality of pieces of information after a certain period of time has elapsed or selecting and recording a plurality of divided areas, this is done through a stop operation, but if the recording operation is performed again after the stop operation, the CPU 79 Stop operation (step (
10) and (75)), step (76)) to stop the 1-byte signal interrupt, and step (77) to record the address pointer data at this time in RAM 85.
)), clear the address counter step (81)
>, enters stop mode (steps (16), (82)
)). Then, by operating the recording switch 21 again (steps (8), (47)), the marker indicator light 28 corresponding to the address pointer data indicating the start address of the partial area written in the RAM 086 at the time when recording was started last time is activated. It is turned on (step (48)) to display the segmented area of the audio data storage element 81 in which audio data has already been recorded.

Then, write the address pointer data at the end of the previous recording to R.
Step (49)) to read from the AM85, step (50)) to increment this data, and send this incremented address pointer data to the CPU.
Step (5) to preset the address counter of 79.
2)), the value of the address counter is continued to be incremented until the address pointer data preletted in this address Karakun matches the starting address of each partial area of the audio data memory 81 stored in the ROM 88 (step ( 63), (64)), Previous 47- Even if there is sufficient capacity in the partial area at the end of recording, recording is performed from the next partial area at the end of this recording. Note that when recording is performed again in a previously recorded partial area, the previously recorded audio data is updated and newly recorded audio data is stored.

(5) Reproduction Operation When the reproduction switch 22 is turned on for reproduction (steps (a), (83)), the P1076 reads the interrupt information and issues an interrupt to the CPU 79 via the interrupt signal line 77.

When this interrupt signal is generated, the CPU 79 determines whether or not there is held data in the RAM 86 of the control storage element 83 (step (,84)). If there is held data in the RAM 86, this held data is read out and incremented by 1 byte (step (85)).

In other words, the fact that there is retained data in the RAM 86 indicates that a previous playback operation was performed, and this R
Since the data held in the AM 86 is the address pointer data at the end of the previous playback, by incrementing the held data by 1 byte, the playback operation starts from the address following the previous playback operation in the audio data storage element 81. This is to do this.

Next, if there is no held data in the RAM 086, and if there is held data, this held data is incremented by 1 byte, and then it is determined whether or not there is held data in the ROM 88 (step (86)). This determination is whether a skip operation or a repeat operation has been performed.

If there is data held in the ROM 88, a skip or repeat operation has been performed, so this data is transferred to the CP.
The address counter of U79 is preset and playback is prepared from the partial area of the audio data storage element 81 selected by a skip operation or a repeat operation (step (
88)). If there is no retained data, the skip operation or repeat operation has not been performed, so the CPU 79 is preset with the data of step (85), which is incremented by 1 byte from the address pointer data at the end of the previous playback operation, and the data is continued from the previous playback operation. Prepare to play (
step (87)). In this state, the marker indicator lamp 28 is temporarily turned off (step (89)) in preparation for displaying the partial area during the subsequent reproduction operation.

Next, the CPU 79 opens the converted signal bypass circuit 66 of the delta modulation/demodulation section (step (90)) and turns off the muting circuit 71 for howling prevention (step (91)). In addition, variable clock VC
To start the operation of O73 (Step (92)), since no control voltage is generated at the frequency control input terminal of this VCO73 at the time of starting reproduction, this VC073 starts oscillating at its free running frequency (Step (93)) )).

At the same time, the input/output switching circuit 65 is switched to the demodulation side (step (94)).

Next, the output pulse of the VCO 73 is frequency-divided by 8 by the frequency dividing circuit 74 to generate a 1-byte signal (step (95)
)). When a 1-byte signal is generated in this way, the CPU 7
9 accepts the interrupt by this 1-byte signal (step (96)), and determines whether the address counter of the CPU 79 and the data of the RAM 84 are the same value (step (97)). If the address data of the CPU 79 and the address pointer data of the RAM 84 do not match, the address counter of the CPU 79 is incremented (step (98)) and continues to be incremented until they match (steps (97), (9)).
8)).

That is, by this operation, the partial area at the start of recording of the audio data storage element 81 of the recording stream is read out.

In this way, when the address counter data of the CPU 79 and the address pointer data of the RAM 84 match,
The matched value is stored in the audio data storage element 8 of the CPU 79.
Set address counter 1 (step (99))
. At the same time, the marker display \T28 of the partial area corresponding to this number is turned on (step (100)), and then part of the address pointer data 51 of the ROM 88 is incremented in preparation for the next readout (step (101)). Step (1) of reading data from the partial area of the audio data storage element 81 in which the audio data has been recorded as described above.
02>), the bit-parallel audio data based on the read 1-byte signal is converted into a temporally continuous bit-serial pulse signal by the parallel-to-serial conversion circuit 67 via the input/output switching circuit 65 (step (103)). . After that, delta demodulation is performed in the delta demodulation circuit 68 (step (1)
04)). The demodulated signal demodulated by this delta demodulation circuit 68 passes through an LPF 69, adjusts the volume with a variable resistor 70, turns on a muting circuit 71, amplifies it with five amplifiers, and outputs it as an audio output signal. and speaker 5
7 (step (105)).

On the other hand, a part of the output signal of the LPF 69 is 5D7
2, the slope of the amplitude is detected, and an output voltage is generated depending on the magnitude of this slope. The frequency of the output clock pulse of the VCO 73 is controlled by the VCO 73 according to the magnitude of the output voltage of the VCO 5072 (step (106)).

That is, by reading and reproducing the signal using a clock frequency that corresponds to the magnitude of the slope of the voltage amplitude of the demodulated signal, it is possible to reproduce the audio signal on the same time axis as when it was recorded.

After 1 byte of audio signal is played in this way, the address counter of the CPU 79 is incremented,
Prepare to play the next 1 byte of audio signal (step (
107)). In this state, it is determined whether RΔM 84 matches a preset constant value (step (1)
08)). When the value of this RAM■84 matches the set value, the remaining capacity indicator light 33 or 34 displays the remaining capacity.
lights up (step (109)).

In other words, in the case of this embodiment, if the time remaining at the end of the storage capacity of the storage element 81 for audio data to be recorded is 20 seconds or 10 seconds, a warning is given regarding the remaining capacity of the storage element 81 for audio data. The remaining amount indicator light 33 or 34 lights up.

On the other hand, in a step (110)) to detect the presence or absence of an end marker in parallel, if the end marker has not yet appeared,
That is, if there is still room in the storage capacity of the audio data storage element 81, it is detected whether or not the stop switch 26 is operated next (steps (10) and (111)).
). If the stop switch has not been operated, it is subsequently determined whether or not the cue switch 23 has been operated (step (112)).

In this way, if the end marker does not appear and neither the stop switch 26 nor the cue switch 23 is operated, the address pointer data of the address counter of the CPU 79, that is, the audio data incremented in step (107). It is determined whether the next reproduction address in the storage element 81 matches the data recorded in the RAM 85 (step (113)).

In other words, it is determined whether or not the audio signal recorded by this operation still remains.

If it is determined in this way that the address pointer data of the address counter of the CPU 79 and the data in the RAM 85 do not match, this indicates that there is still recorded audio data, so the steps continue. (Returning to step 102>, the next audio data is read from the audio data storage element 81 and reproduced.

In addition, the address pointer data of the CPU 79 and the RAM■8
If the data match the data of 5, it indicates that recording in the partial area in the audio data storage element 81 has already been completed, but the next audio data storage element 8
In order to reproduce the recording in the partial area within 1, the next address pointer data is read from RAM 84 (step (114)). The read address pointer data is then preset in the address counter of the CPU 79 (step (115)).

Then, the audio data stored in the partial area of the audio data storage element 810 corresponding to the newly preset address pointer data is played back, and for this purpose, the process returns to step (102) 55- and the address counter is preset. In step (100), the address pointer data is displayed as marker indicator light 2.
At the same time, the audio data in the partial area of the audio data storage element 81 corresponding to this address pointer data is read out (step (102)).

In this way, the recorded data is sequentially played back, and when the storage capacity of the audio data storage element 81 approaches its end, the remaining indicator lights 33 and 34 light up as described above, and
When the storage capacity in the audio data storage element 81 is completely filled, the end marker becomes visible, this end marker is detected in step (110), and the interrupt operation of the 1-byte signal to the CPU 79 is stopped (step (110)). 116)).

Next, step (117) to determine the presence or absence of a memory pack.
), if there is no memory pack, the address counter of the CPtJ79 is cleared (step (118)), and the stop mode is entered (step (119)). If there is a memory pack, it will be explained later.

In addition, if the playback operation is to be stopped even though the storage capacity in the audio data storage element 81 is still 56-, by operating the stop switch 26 (steps (10), (111)), When the interruption of the 1-byte signal to the CPU 79 is stopped (step (120)), the address pointer data at this time is written into the RAM 86 (step <121)).

That is, address pointer data at the end of reproduction is recorded in the RAM 86.

After writing the address pointer data into the RAM 86 in this manner, the solid-state recording and reproducing device 2Ω- enters the stop mode (step (119)).

Note that the reproduction/cueing operation in step (112) will be described later.

In this way, the reproduction operation according to this embodiment is performed by using the address pointer data of the audio data storage element 81 and the RAM 8 of the control storage element 83 while the CPU 79 is reading the audio data.
Constantly compare the address pointer data recorded in 5.
When both data become the same, the one closest to the data from among the address pointer data stored in RΔM 84,
A partial area of the audio data storage element 81 is selected, and the audio data is read out and reproduced.

In other words, the unrecorded portions are skipped and only the recorded portions are sequentially played back.

(6) Skip/playback operation In this case, the user desires to playback from a certain partial area in the audio data storage element 81 or the audio data storage element 103, and selects and plays the partial area. . In this case, when the skip switch 24 is turned on, C
, the PU79 determines the skip operation mode (step (6)) and executes the skip processing program (
Step (18)).

That is, according to the skip flowchart in FIG.
When the skip switch 24 is operated (step (
25)) The CPU 79 uses the ROM 8 in the control storage element 83.
Step (26)) in which the address pointer data is sequentially read from 8 (step (26)), and the indicator lamps 28 in the partial areas corresponding to the read address pointer data are sequentially turned on one by one (step (27)).

Skip switch 2 is the same as the operation during skip recording below.
4 is turned off or not. Step (28)>
If the end marker is not turned off, step (30)) determines whether there is an end marker. If the end marker does not appear, continue reading the address pointer data (step (26)). If the end marker appears, proceed to step (26)). It is determined whether there is a memory pack (step (31)), and if there is no memory pack, it is meaningless to continue skipping any further, so the solid-state recording/reproducing device enters the stop mode (step (24)).

In addition, when the memory pack 52 is connected, the control memory element 83 in the main body 51 is switched to the control memory element 97 in the memory pack 52 (step (32)), and the memory pack is being skipped. Step 3: Turn on the two memory pack indicator lights to indicate that the
3)) Continue reading the address pointer data (step (26)). Note that the memory pack indicator light 29 indicates the RAM 9 in the control memory 83 in the memory pack 52.
The light is turned off when the FND marker written in 8 is read or when the solid-state recording/reproducing device enters the stop mode (step (24)).

In this way, when the selected partial area is reached during the skip operation, the skip switch 24 is turned OFF t::-
tr (step (28)). When the skip switch 24 is turned off, the address pointer data in the ROM 88 at this point is incremented, stopped, and held in this state (steps (2)).

In the case where reproduction is to be performed, when the reproduction switch 22 is turned on, the CPU 79 determines that it is in the reproduction mode (step (7)) and executes the reproduction program. (Step (19)).

That is, when the playback switch 22 is turned on (step (83)), it is determined whether or not a playback operation has been performed before this playback operation based on whether or not there is data in the RAM 86 (step (8/1)). ), if it is determined that the previous playback was performed, the address pointer data of this RΔM 86 is read out and incremented by 1 byte (step (85)), and if the previous playback operation has not been performed, the data is stored in the ROM 88. Step (86)) to determine whether there is retained data; in this case, the step (86) described above is performed;
29), the address pointer data during skip playback is R.
Since it is held in OM88, step (88
), this data is preset in the address counter of the CPtJ79, and a reproduction operation similar to the reproduction operation described above is performed from the partial area where this skip operation was stopped. Note that by performing this skip operation, the marker indicator light 28 that was lit during playback is turned off.

(7) Repeat/playback operation In this case, by turning on the repeat switch 25 during playback, the recording address J: of the audio data storage element 81. Address pointer data is sequentially scanned at high speed to select a necessary playback position.

By turning on the repeat switch 25, the CPU 7
Step 9 determines whether the mode is repeat mode (step (5)) and executes the repeat processing program (step (17)).

That is, by turning on the repeat switch 25 (step (34)), it is determined whether there is a memory pack or not (step (35)). Start repeat operation.

That is, the memory pack display *r29 indicating that there is a memory pack lights up (step (4, 0)), and accordingly, the control memory element 83 in the main body 51 is moved to the memory pack 5.
Switching to the control memory element 97 in 2 (step (/11)
)), the step of reading address pointer data from the ROM 88 in the control storage element 83 in order from the larger gfI@ to the smaller number (/l2)), and sequentially blinking the marker indicator lights 28 corresponding to this address pointer data (step (4,3)).

In this way, the address pointer data is sequentially read, and the presence or absence of the end marker in the memory pack 52 is determined (step (44)).The above reading operation is continued until the end marker does not appear, and when the end marker appears, switches the control memory element 97 in the memory pack 52 to the control memory element 83 in the main body 51 (step (/15))
, turn off the two indicator lights indicating that there is a memory pack (step (46)), and store the address pointer data corresponding to the audio data storage element 81 in the main body in the ROM 88.
step (36)) to sequentially read out the numbers from the largest to the smallest; step (37)) to make the marker indicator lights 28 blink sequentially in response to this readout operation; and turn off the repeat switch 25. It is determined whether or not (step (38)). The above operation continues while the OFF operation is not performed, and when the OFF operation is performed, step 6
At one point in time, the address data in the ROM 88 is incremented, reading is stopped, and this data is held (step (39)).

When the next playback operation is performed in this state, it is determined that the CPIJ 79 is in the playback mode, as in the skip playback mode described above (step (7)), and the playback processing program is executed (step (19)).

That is, when the playback switch 22 is turned on (step (83)), the data in the ROM 88 is preset to the address counter of the CPU 79 (step <88)), and the portion in the audio data storage element 81 corresponding to this address pointer data is Start the playback operation from the area.

Note that in this repeat operation program, the recording and playback operation is stopped in the memory pack 52 at the same time as recording and playback, and recording and playback cannot be performed from an appropriate partial area of the audio data storage element 103 in this memory pack 52. This is a program such as this, but the memory pack 52 originally uses the audio data storage element 103, which has a smaller storage capacity than the audio data storage element 81 of the main body 64-51, and uses the audio data storage inside the main body. It is used for an auxiliary purpose to compensate for the lack of storage capacity of the element 81, and the storage capacity of the audio data storage element 103 is not that large, so the audio data in the memory pack 52 is stored in the memory pack 52 by repeat operation. This is because it was considered unnecessary to select a partial area in which the recording/playback operation of the storage element 103 is to be started.

However, the audio data storage element 1 in the memory pack 52
It is also easy to add a repeat recording/playback mode within this memory pack 52 by using a large storage capacity storage element in 03. Note that the marker indicator light 28, which was turned on due to the reproduction operation before the repeat operation, is turned off by the repeat operation.

(8) Cue/playback operation This is a case where the audio data currently being played is skipped and the audio data recorded in the next partial area is played back.

This is carried out by turning on the cue switch 23 during playback.

That is, when the cue switch 23 is turned on, the CPU
79 is running the playback program (step (1)
9)) During this playback program, turn on the cue switch.
is detected (step (112)), and the RAM ■
85, the one closest to the address pointer data of the audio data storage element 81 currently being played back is read out (step (122)).
). Then, address pointer data closest to and higher than the read address pointer data is read from the RAM 84 (114).

Next, this read address pointer data is CPt
Preset the step to the address counter of J79 (
115)), the audio data is read from the address in the audio data storage element 81 corresponding to this address pointer data and reproduction is continued (step (102)).

Through this series of operations, the cue switch 23 is turned on.
When the partial area is played back, the partial area being played back is skipped and the next partial area is played back from the first address.

Note that the head-off switch 23 is of a type that, even if it is turned on once, the next time the head-off operation is performed by turning on the head-off switch 23 again as soon as you release your finger.

(9) Repetition of playback/stop operation When the stop switch 26 is turned on during data playback (step (111)), the address pointer data of the audio data storage element 81 that is currently being read out is RA.
The solid-state recording and reproducing device 20 enters the stop mode (step (119)), but when it is set to the possible reproducing mode (step (83)), it returns to the position where the previous reproduction ended. Step (84,
)), reproduction is started from the address obtained by incrementing the address pointer data of this data by 1 byte (step (85)).

That is, when repeating the playback/stop operation, playback is started following the address 67-- at which the previous playback ended.

(10) Operation of the memory pack The audio data storage element 81 and various data storage RΔM 84-86 and the same type of audio data storage element 103 and RAM 98-100 are stored in the operation body 51 of the memory pack. Memory pack 5 packaged for easy carrying
2 is provided on the outside of the main body, and the main body and the memory pack 52 provided on the outside are electrically connected by connectors 54 and 55 to extend recording and playback time and to extend the recording/playback time and to extend the storage element 8 for audio data inside the main body.
Used when editing or copying audio data recorded in 1.

Note that the audio data storage element 1 in this memory pack 52
03 and RAMs 98 to 100 are provided with a backup memory 102 within the memory pack memory 52 to prevent stored data from being volatilized when the main body is disconnected from the power supply.

Egg White, which has RA = 68-M98 to 100 with the same function as the main body 51 in the memory pack 52, is a memory for audio data when the memory pack 52 is used in a main body different from the main body 51. This is to avoid any inconvenience in reading the recording address of the element 103.

Note that when this memory pack 52 is connected to the connection 54, the signal line 95 inside the main body 51 is grounded via the plug 54.55 and the signal line 96 inside the memory pack 52, and the CPU 79 determines that the memory pack is present. Step (2))
Various programs associated with the existence of the memory pack are executed (step (3)).

The contents of various programs associated with the existence of this memory pack include, for example, an operation that switches the control storage element inside the main body to the control storage element inside the memory pack when reading the end manica stored in the control storage element inside the main body. (steps (32), (123), etc.), the operation of reading out the address pointer data for the memory pack in the address pointer data storage ROM 88 following the address pointer data for the main body, the lighting of the memory pack operation indicator 29 (steps (33), ( 124) etc.).

By providing a memory pack 52, which will be described later], in the case of the bee operation, the copy switch 21 is operated, and the audio data recorded in the audio data storage element 81 in the main body is transferred via the data save RAM 87. memory pack 52
[Sequentially recording from the first address to the audio data storage element 103]] bee operation becomes possible.

Furthermore, when the end marker of the audio data storage element 81 housed inside the main body 51 is detected, the marker indicator light 28 turns on at the same time as the memory pack indicator light 29 (steps (33), (124), etc.). The marker indicator light 28 will display each partial area of the audio data storage element 103 in the memory pack 52.

Next, the operation when using the memory back 52 will be explained.

(a) Recording mode When the recording switch 21 is turned on, the CPU 79 determines the presence or absence of the memory pack 52 (step (2)).As described above, the determination of the presence or absence of the memory pack 52 can be made by connecting the memory pack 52. By installing the signal line 95, it is determined that the memory pack 52 is inserted.

When it is determined that the memory pack 52 is inserted, the CPU 79 switches the control memory element 83 in the main body 51 to the control memory element 97 in the memory pack 52 (step (123)), and turns on the memory pack indicator light. Turn on 29 (
step (124)). Following this operation, the CPU 79
accepts a 1-byte signal interrupt (step (62)
)), memory pack 52 as in normal recording operation after JS.
Recording is performed in the audio data storage element 103 inside.

After recording the bit-parallel signal read out using the 1-byte signal, the address counter in the CPU 79 is incremented (step 71).
), the presence or absence of an end marker in the memory pack 52 is determined (step (125)). If the end marker does not appear and the stop switch 26 has not been operated yet (step (126)>, the CPU 79 reads the next 1 pie 1 signal (step (62)), then the memory pack continues. Recording to the audio data storage element 103 in 52 continues.

While recording continues in this manner, whether the end marker in the memory pack 52 is detected (step (1)
25)) When the stop switch 26 is operated, step (126)) the interruption of the 1-byte signal to the CPU 79 is stopped (step (127)), and the address counter is cleared. Device,? -・0 becomes stop mode (step (1
29)).

In this way, recording into the memory pack 52 is completed.

(b) Skip/recording operation This is an addition of the above-mentioned operation within the memory pack to the skip/recording operation within the main body. The explanation will be omitted.

=72- (c) Repeat/recording operation This is similar to the skip/record operation in (h).

(d) Repeating the recording/stop operation This is the addition of the memory pack operation in the flowchart in Figure 11 above to the record/stop operation of the main unit, and the other operations are the same as the repetition of the record/stop operation of the main unit. Since there is, I will omit the explanation.

(e) Reproduction operation The above-mentioned memory pack operation is added to the reproduction operation of the main body.

(f) Skip/reproduction operation This is the addition of the memory pack operation shown in FIG. 11 to the skip/reproduction operation of the main body.

(0) Repeat/playback operation The operation of the memory pack shown in FIG. 11 described above is added to the repeat/playback operation of the main body.

(h) Cue/playback operation This is the cue/playback operation of the main body plus the above-described memory pack operation of FIG. 11.

(i) Repetition of playback/stop operation This is the addition of the memory pack operation in the flowchart of FIG. 11 to the repetition of playback/stop operation of the main body.

(11) - 1 pin operation This copy operation is performed on the audio data storage element 8 in the main body 51.
This is an operation of transferring and transcribing a specified part or all of the audio data stored in the audio data stored in the audio data storage device 103 in the memory pack 52. This operation will be explained according to the flowchart in FIG.

First, the main unit is played back to find the audio data to be played in the memory pack 52. After selecting the desired copy location, set to -H stop mode and press copy switch 21.
Turn on. By turning on this copy switch 21, C
The P U 79 determines that it is in the copy mode (step (9)) and executes the copy program described in detail below (step (21)).

That is, when the copy switch 21 is turned on (step (13)
0)), the presence or absence of the memory pack 52 is first determined in step (131)). If the memory pack 52 is not inserted, the bee operation is impossible, so the main body 51 enters the stop mode (step (131)). 132)). If the memory pack 52 is inserted, the copy indicator light 30 will light up to indicate that the copy operation is in progress (step 133).
, the CPU 79 sets the start address pointer data of the audio data storage element 103 in the memory pack 52 (
step (134)).

Next, the data of RΔM 86 in the main body 51 is read out, and the address pointer data corresponding to the partial area in the audio data storage element 81 located before this is read out from the RAM 84 (step (135)). RAM■8i
The at 1 pointer data of R in the memory pack 52
A step (1
37). This audio data is then written into the audio data storage element 103 in the memory parallel 75 (step (138)). Next, the address counter of the CPLI 79 is incremented (step (139)).

That is, by the above operation, the audio data storage element 81
When the copy switch 21 is set to ONL, the data is sequentially copied starting from the first data recorded in the partial area.

This copy operation is performed when the stop switch 26 is turned on (step (140)), the end marker is read from the RAM 84 (step (141)), or the address pointer data at the end of recording is read from the RAM 85. If the address pointer data is issued (step (142)), the address pointer data at this time is written to the RAM 99 in the memory pack 52 (step (143)), and the copy indicator light 30 is turned off (step (14'l)). ), the main body 51 enters the stop mode (step (145)).

In order to play a plurality of audio data among the audio data recorded in the audio data storage element 81 in the main body 51, turn on the copy switch 21 each time (step 146), and store the memory pack. RAM in 52■
Read the address pointer data recorded in 99,
From this, the address pointer data corresponding to the partial area of the storage area in the audio data storage element 103 in the bamboo grass is set to R.
Step (14, 7>) of reading from the OM 88, and setting the address in the audio data storage element 103 corresponding to the read address pointer data (step (148)). Then, the read address pointer data is written to the RAM 98 in the memory pack 52 (step (149>). Then, the set address of the audio data storage element 103 is stored in the audio data storage element 8.
Transfer data and copy from step 1 (step (1)
38)). The following copy operation is the same as the previous copy operation.

In other words, the audio data storage element 1 having a larger address than the data read from the RAM 99 in the memory pack 52
The address pointer data of the partial area in 03 is stored in ROM8.
8, a segmented area in the audio data storage element 103 corresponding to the data is selected and transferred.

Although not shown in the flowchart of FIG. 12, the copy indicator light 30 is also turned on during the re-hemp copying operation.

Through the above operations, the solid-state recording and playback device 2 of this embodiment is
0, the audio data stored in the audio data storage element 81 in the main body 51 can be transferred and transcribed to the audio data storage element 103 in the memory pack 52, but the transfer speed in this case is CP (J79 Since the signal processing speed is determined by the instantaneous signal processing speed of
Extremely high-speed copying is possible.

Next, the operation of the indicator light of the solid-state recording and reproducing apparatus of this embodiment will be summarized and explained.

(1) Marker indicator light This marker indicator light is composed of a total of 18 IEDs that display time for a total of 180 seconds in units of 10 seconds, and has a delta modulation/demodulation circuit 63 necessary to obtain satisfactory audio quality.
．． The number obtained by converting a frequency 10 times the clock frequency of 68 into bytes becomes the storage capacity of the partial area of the audio data storage element 81.103 necessary to store 10 seconds of audio data. Therefore, since the number of address data is the same, address data is set in advance every 10 seconds, and when the address data during actual operation and the set address data are compared, and the values become the same, 10 seconds have passed.

In this embodiment, in order to reduce the number of audio data storage elements 81, 103, a variable clock system is used for the delta modulation/demodulation circuits 63, 68, in which the clock frequency is proportional to the magnitude of the slope of the audio signal. Strictly speaking, errors occur due to differences in information, but since the average value is used as the preset address data value, the errors are averaged out for 10 seconds and do not cause any practical problems.

In addition, a time base composed of a crystal oscillator or the like is set in the setting data, and a pulse is generated from the time base every 10 seconds, thereby changing the address data of the data storage element to RΔM 84.98. Recording can improve accuracy.

(2) Remaining capacity indicator light In the solid-state recording and reproducing apparatus of the present invention, since the audio recording medium cannot be visually seen like a magnetic tape, it is necessary to accurately display the remaining capacity.

In this embodiment, in addition to the marker indicator light 28 described above, the last one
When reaching 0 seconds and the last 20 seconds, the remaining capacity indicator lights 34 and 33 are flashed to alert the user. The timing of lighting the LED is such that a multivibrator circuit is triggered by the above-mentioned lighting signal of the LFD that displays the remaining amount time, and the circuit performs a blinking display.

As another method, it is also possible to use a simple means such as dividing the necessary parts of the marker indicator lamps into different colors.

(3) Recording/playback/play/cue/stop/memory pack operation/skip/repeat/lobby indicator light Lights up when operating in the relevant mode. The light is turned on by the lighting data from the CPU 79 while the light is operating in the corresponding mode. Note that the skip/repeat mode is related to the recording or playback mode, so it does not light up independently.

(4) All of the above-mentioned indicator lights are connected to each part via drive circuits 89 and 93.

[Effects of the Invention] As explained above, in the solid-state recording and reproducing device according to the present invention, a solid-state memory element is used as the storage means, and the memory pack is connectable to the main body via the connecting means, and the memory pack is connected to the main body. Since the operation of the memory pack is displayed and checked when connected to the memory pack, there is no quality deterioration such as fluctuations in audio signals or distortion noise caused by mechanical drive mechanisms, and there is no wear on storage media such as magnetic tapes and disks. It is possible to obtain the usual effects of using a solid-state memory element as a storage medium, which is free from quality deterioration such as scratches and scratches, is highly reliable, and is maintenance-free. At the same time, it is possible to determine the operation of a memory pack when using a memory pack. can be performed reliably and is extremely easy to use.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall structure of the present invention, Figs. 2 and 3 are perspective views of an embodiment of the invention, and Fig. 4 is a block diagram showing the circuit structure of an embodiment of the invention. , Figure 5 is the fourth
FIG. 6 is a waveform diagram of the circuit shown in FIG. 5, and FIGS. 7 to 12 are flowcharts showing the operation of an embodiment of the present invention. 61......Audio detection circuit 63
・・・・・・・・・・・・・・・Delta modulation circuit 64・
......Serial-to-parallel conversion circuit 65...
・・・・・・・・・・・・Input/output switching circuit 66...
・・・・・・・・・Conversion signal bypass circuit 67・
・・・・・・・・・・・・Parallel-serial conversion circuit 68...
・・・・・・・・・・・・Delta demodulation circuit 71...
...... Muting circuit 72...
・・・・・・・・・・・・・Slope detector 73・
・・・・・・・・・・・・・・・VCO゛74・・・・
......... Frequency divider circuit 76...
・・・・・・PTO79・・・・・・・・・・・・・・・
・・CPU 80 ・・・・・・・・・・・ Operation button 81.103 ・Storage element for audio data 82.102
...Backup battery 83.97...Control memory element 84-87.98-100...RAM8
8・・・・・・・・・・・・ROM89.93・
...Drive circuit 90.94...Indicator light 91...C0M92...
・・・・・・・・・・・・March Vibrator Patent Attorney Suyama Sa-2 Ni-814- V Mouth

Claims (1)

[Claims] an encoding means for encoding an audio signal; a first storage means for storing the audio signal encoded by the encoding means; and a first storage means for storing the encoded audio signal stored in the first storage means. a connecting means for electrically connecting a memory pack having a decoding means for decoding and a second storage means configured independently of the encoding means, the first storage means and the decoding means; a memory pack detecting means for detecting that the memory pack is connected via the connecting means and generating an output signal; and a first memory pack detecting means for indicating that the memory pack is connected by the output signal of the memory pack detecting means. storage means, and storage in or reproduction from the partial area corresponding to each partial area obtained by dividing the entire storage area of the second storage means in the memory pack into a plurality of parts. A solid-state recording and reproducing device, characterized in that it is equipped with a second display means for displaying that the solid-state recording and reproducing device is playing.