JPS6012591A - Solid recording/reproducing apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state recording and reproducing device for recording and reproducing audio signals in a solid-state storage element.

[Technical background of the invention and its problems] Conventionally, recording and reproducing devices use magnetic tapes, disks, etc. as storage media, and detect changes in the amplitude of audio signals from changes in the strength of the magnetic field or the amplitude of sound grooves. Tape recorders and record discs are known that record temporal changes in correspondence with the running direction of the tape or disc.

However, in such conventional recording and reproducing devices that have moving parts, the performance of the magnetic head, magnetic tape, needle, etc. has an adverse effect on the dynamic range and distortion of the signal, and the running speed of the magnetic tape or disk that drives it System performance had a negative impact on signal frequency characteristics, wow and flutter, noise, etc. In addition, the lifespan of storage media such as magnetic tapes and disks is finite, and it is important to know the exact location of the recorded signal on the recording medium, so it is necessary to immediately obtain the necessary signal during playback. There was a drawback that cueing operations were not easy.

In addition, in order to eliminate the drawbacks of conventional recording and reproducing devices having movable parts, solid state recording and reproducing devices using solid state memory elements as storage media have been published in patent publications, etc. All of these merely disclosed the possibility of evil theory, and did not take into consideration the ease of use as a concrete device.

Furthermore, regardless of whether or not it has a movable part, the recording/playback device can expand the storage capacity of the storage medium inside the main body by using a storage medium packaged in the storage medium built into the main body. was unknown.

[Object of the invention] The present invention has been made in response to such conventional circumstances,
It is an object of the present invention to provide a solid-state recording and reproducing device that is free from wow and flutter, level fluctuations, etc., and can expand the storage capacity of the storage medium in the main body by connecting a storage medium formed in a package.

[Summary of the invention] FIG. 1 is an overall configuration diagram showing the configuration of the present invention.

In the figure, the output of an encoding means 2 for encoding an audio signal input to an input terminal 1 is stored in a first storage means 3 for storing the audio signal encoded by this encoding means 2. The encoded audio signal stored in the first storage means 3 is decoded by the decoding means 4 and output to the output terminal 5. Furthermore, by connecting the memory pack 7 having a second storage means independent of the first storage means to the connection means 6, the audio signal can be continuously stored in the first storage means and the second storage means. Can be stored or played back.

[Embodiment of the Invention] The details of the present invention will be described below with reference to an embodiment shown in the drawings.

2 and 3 are perspective views showing the appearance of one embodiment of the solid-state recording and reproducing device according to the present invention, and FIG. FIG. 3 is a perspective view showing a state in which the inside is visible after being shifted.

In FIGS. 2 and 3, reference numeral 39 denotes a storage element (hereinafter referred to as a control device for storing control data) that stores encoded audio signals and is built in the main body of the solid-state recording and reproducing device fi20 and is made of, for example, RAM. This is called the "sound data storage element" to distinguish it from the storage element. The storage area of the audio data storage element 39 is divided into a plurality of partial areas, and the starting address of each partial area is stored in advance in the control storage element.

Reference numeral 28 denotes an indicator light corresponding to each of the three audio data storage elements or each partial area of the audio data storage element in the memory pack (described later) (hereinafter referred to as a "marker indicator lamp" to be distinguished from the black type indicator lamps described later). ). This marker indicator light 28 lights up corresponding to a partial area read out in accordance with recording or playback to each partial area of the audio data storage element or a skip or repeat operation described later, and is turned on in response to recording or playback to the partial area. Displays playback, skip, and repeat operations.

Reference numerals 33 and 34 indicate indicator lights indicating that the storage capacity of the three audio data storage elements is nearing its end. In this embodiment, the indicator light 33 has a storage capacity of 20
In this embodiment, the indicator light 34 is turned on 10 seconds before the storage capacity is reached.

4- Also, in this embodiment, for example, RAM or 0M
It has an insertion slot 35 into which a packaged memory pack having an audio data storage element such as O8 is inserted, and the memory pack inserted through the memory pack insertion slot 35 is connected to the connection terminal 40 and connected to the main body. electrically connected. The indicator light 29 is an indicator light that indicates that the memory pack is inserted into the main body and that recording to or reproduction from the memory pack is in progress.

Reference numerals @21 to 27 are switches for performing various operations of the solid-state recording and reproducing device 20, and reference numeral 21 indicates the recording operation to the audio data storage element 39 in the main body, and the operation by inserting the memory pack into the main body. The audio data storage element 3 in
This is a recording/copy switch for performing a recording operation on the memory pack following the recording operation on the audio data storage element 39, or when transferring audio data stored in the audio data storage element 39 to the memory pack and performing a copy operation. , this recording/
When the copy switch 21 is operated, the indicator light 30 lights up.

Reference numeral 22 is a playback switch for playing back the recording signal recorded in the audio data storage element 39, and when the playback switch 22 is operated, the indicator light 31 lights up.

Reference numeral 23 is a cue switch for cueing operation, and when this cue switch 23 is operated, the partial area being played back in the audio data storage element 39 is skipped and the recorded audio signal is transferred to the next partial area. Reproduce.

Reference numeral 24 is a skip switch corresponding to fast forwarding in a conventional tape recorder, and when this skip switch is operated, the marker indicator light 28 changes to, for example, 0. It blinks sequentially every 1 second, and the leading address of each partial area of the audio data storage element 39 is read out one after another. Then, with this skip switch 24 turned OFF, recording or reproduction is possible from the first address of the partial area next to the current partial area.

Reference numeral 25 is a repeat switch corresponding to the rewind switch of a conventional tape recorder, and by operating this repeat switch 25, the skip switch 24 is activated.
In the opposite direction, that is, when the audio data storage element 39 or memory pack is connected, the marker indicator light 28 lights up for 0.4 seconds from the R Hiiragi address of the audio data storage element in the memory pack. The sound data storage element 39 or the partial area of the audio data storage element in the memory pack is sequentially read out from the rear address. When the repeat switch 25 is turned OFF, scanning of the partial area of the audio data storage element 39 or the audio data storage element in the memory pack is completed, and recording starts from the partial area next to the partial area at the time of stop. Or playback becomes possible.

Reference numeral 26 is a stop switch that instructs to stop each operation, and when this switch is operated, the indicator light 32 lights up.

Reference numeral 27 is a power switch of the solid-state recording and reproducing apparatus 20. Also, numeral 36 is a built-in microphone,
Reference numeral 37 is a headphone jack, and reference numeral 41 is a built-in speaker.

The functions of the respective switches in the embodiment shown in FIGS. 2 and 3 will be briefly described below.

(1) Recording mode This mode represents the case where recording is performed sequentially from the first address of the audio data storage element. In this case, by externally attaching the memory pack, it becomes possible to expand the storage capacity of the storage element within the main body.

Further, the marker indicator lights 28 are lit sequentially from number 0 in proportion to the recording time to indicate recording.

(2) Skip/record mode This mode represents the case where an arbitrary partial area of the audio data storage element is selected and recording is performed from the beginning address of this partial area. In this case as well, by using a memory pack, it is possible to expand the storage capacity of the audio data storage element within the main body. It is also possible to skip a partial area of the audio data storage element of the memory pack.

8- Marker indicator lights 28 light up one by one in a short time from number 0, stop at the skip OFF position, and start recording from this position, recording to the corresponding partial area ends as in the recording mode. Each time the process moves to the next partial area, the marker indicator lights 28 are lit up one by one.

(3) Repeat/record mode This mode is similar to the skip/record mode, but the recording position is selected from the end address of the audio data storage element. The fact that the storage capacity can be expanded using a memory pack is the same as in the recording mode and skip/record mode.Furthermore, it is also possible to repeat a partial area of the audio data storage element in the memory pack. It is.

The marker indicator lights 28 are lit up one by one at high speed, starting from the marker indicator lights 28 with the larger number and moving towards the smaller number, as an indicator of the desired location. When recording is started by turning off the repeat operation, the operation of the marker indicator light 28 is the same as in the recording mode.

(4) Reproduction mode This mode represents the case where the audio data is reproduced sequentially from the first address of the storage element. The ability to expand the playback capacity using a memory pack corresponds to the recording mode.

The marker indicator lights 28 are sequentially lit starting from number 0 in proportion to the playback time, as in the recording mode.

(5) Skip/Reproduction Mode This mode represents the case where reproduction is performed from the beginning address of an arbitrary partial area of the audio data storage element. In this case as well, the storage capacity of the audio data storage element can be expanded by externally attaching a memory pack. A skip mode within a memory pack is also possible.

The marker indicator lights 28 are sequentially lit one by one starting from number 0 in a short period of time, similarly to the skip recording mode described above. When the skip is stopped and the playback is performed, similarly to the playback mode described above, the partial areas of the audio data storage element are sequentially illuminated in proportion to the playback time.

(6) Repeat/playback mode This mode is similar to the skip/playback mode, except that the playback position is set from an address toward the end of the audio data storage element. By using a memory pack, it is possible to expand the playback capacity corresponding to the recording mode, and repeat operations within the memory pack are also possible.

The operation of the marker indicator lights 28 is similar to the above-mentioned repeat recording, by sequentially lighting up the indicator lights in a short period of time, and pressing the repeat switch 28.
The solid-state recording and reproducing device 20 starts the reproducing operation by operating the reproducing switch 22 after stopping with both OFF and OFF, and the operation of the marker indicator lamp 28 at this time is the same as the operation during reproducing.

(7) Cue/Reproduction Mode This mode is a mode in which the audio data recorded in the partial area next to the partial area currently being reproduced is read out by operating the cue switch 23. Even in this mode, the use of a memory pack makes it possible to locate the beginning of audio data whose capacity has been expanded.

The operation of the marker indicator light 28 is the same as in the reproduction mode described above.

11- (8) Copy mode This mode represents the case where audio data recorded in the audio data storage element within the main body is copied to an external memory pack.

Recording is performed in the memory pack sequentially from the beginning of the audio data storage element of the memory pack. The operation of the marker indicator light 28 is the same as in the recording mode.

Next, a specific circuit configuration for realizing the various operation modes described above will be explained.

FIG. 4 is a block diagram showing the circuit configuration of an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration example of the voice detection circuit 61 in the block diagram of FIG. 4, and FIG. 6 is a waveform diagram showing an example of waveforms of each part of the circuit of FIG.

In FIGS. 4 to 6, reference numeral 51 indicates the main body of the solid-state recording and reproducing apparatus of this embodiment, and reference numeral 52 indicates a memory pack. The main body 51 and memory pack 52 are connected to a connector 54.5
It is electrically connected via 5. Further, the plug 53 of the main body 51 is provided with an input/output terminal, and the microphone 5
6, Subi 12-power 57, etc. can be connected, and it is electrically connected to the circuit inside the main body.

Reference numerals 58 and 59 are amplifiers, which amplify the input signal from the input terminal and output the signal to the speaker 57 via the output terminal.
Amplify the reproduction signal that drives the etc. This amplifier 58
．． 59 form a pair to form an analog amplifier 60.

For example, the input signal, which is the output signal of the microphone 56, is
It is amplified by the amplifier 58 via the plug 53, and then passed through a low-pass filter (hereinafter abbreviated as "L P F ") 62.
and is input to the voice detection circuit 61.

This audio detection circuit 61 interrupts the recording operation to the audio data storage element 81.103 when the level of the input signal is below a preset level during recording, and prevents the audio data storage element 81. This circuit is designed to prevent the wastage of the 103 and also to quickly listen to necessary signals during playback.

Details of this circuit will be described later in FIG.

The output signal of this audio detection circuit 61 is transmitted to a peripheral input/output controller (hereinafter referred to as "p").
The output signal of the LPF 62 is input to the delta modulation circuit 63, and becomes one of the control signals of the central control circuit (hereinafter abbreviated as ``c p u'') 79. The output signal encoded by the delta modulation circuit 63 is converted into parallel signals of 8 bits each by the serial/parallel conversion circuit 64.

The output signal of this serial/parallel conversion circuit 64 is inputted to an input/output switching circuit 65 and then sent to an address/data/control bus 75.
is output to. The signal from the address/data control bus 75 is input to the parallel/serial conversion circuit 67 via the input/output switching circuit 65, where it is converted bit by bit into a temporally continuous bit-serial output signal. , are input to the delta demodulation circuit 68.

The output signal of this delta demodulation circuit 68 is L P F2O
is terminated with a variable resistor 70 via a slope detector (
(hereinafter abbreviated as "SD") 72.

The output signal of this 5D72 is a voltage controlled oscillator circuit (hereinafter "''
(abbreviated as “vco”) 73, and the VCO
73 outputs a pulse signal with a period proportional to the slope of the demodulated signal, and this pulse signal and a signal obtained by dividing this pulse signal by 8 by a frequency dividing circuit 74 are divided into the address data and
The signal is supplied to the control bus 75, the delta modulation circuit 63, the delta demodulation circuit 68, the serial/parallel conversion circuit 64, the parallel/serial conversion circuit 67, the input/output switching circuit 65, etc., and is used as a control pulse signal.

The demodulated output via the variable resistor 70 is input to a muting circuit 71, the voltage level of which is attenuated as required, and output to the speaker 57 via an amplifier 59 and a plug 53.

The symbol @81 is a storage element for audio data, for example 256
It consists of 12 bit RAMs. The entire storage area of this audio data storage element 81 is divided into a plurality of partial areas, and from now on, the address data of the starting address of each partial area and the chip number of the storage element in which the partial area exists are combined into a pair of data. This will be referred to as "address pointer data"=15-. Further, a backup battery 82 for emergency use is connected to the audio data storage element 81.
To prevent internal audio data from being volatile even when the power is cut off. Furthermore, a storage element 81 for audio data
is connected to the address/data/control bus 75, and exchanges signals with the CPU 79, input/output switching circuit 65, and the like.

Reference numeral 83 is a control storage element for controlling addresses for writing and reading audio data to and from the audio data storage element 81.

In this control memory element 83, an RA is used to record address pointer data of the audio data memory element 81 at the time of starting recording.
12 RAMs for storing address pointer data at the end of recording, 12 RAMs for storing address pointer data at the end of playback, save RAM 87, and the beginning of each partial area of the preset audio data storage element 81. ROM8 that stores the address pointer data of the address
8 is provided. The input/output terminals of each of the RAMs 1 to 2 84 to 16-87 and the ROM 88 are connected to the CPU 79 via an address/data control bus 75, a PI 076, and an address/data control bus 78. Note that the RAM ■ to ■8 of the control memory element 83
4 to 87 are connected to the backup battery 82 to prevent stored data from volatilizing in an emergency.

The PI076 has a register and has an address and address with the CPU79.
Data control bus 78 and interrupt signal line 7
7 to mutually exchange signals, and the second
It receives output signals from operation buttons 80 such as the recording copy switch 21, playback switch 22, cue switch 23, etc. shown in FIGS.

Furthermore, when the memory pack 52 is connected to the main body 51 via the connections 54 and 55, the signal line 95 is electrically connected to the signal line 96 that is grounded within the memory pack 52, and the memory pack 52 is connected. This is a signal line for generating various command signals associated with this, and for lighting the indicator light 29 to indicate that recording or playback operation to the memory pack 52 shown in FIGS. 2 and 3 is in progress. The address/data/control bus 75 is connected via a drive circuit 89 to a marker indicator light 28 that indicates each partial area of the audio data storage element 81 and an indicator light 29 that indicates that the memory pack 52 is connected. etc., and sends necessary drive signals from the CPU 79.

Similarly, the conversion signal bypass circuit 75 is a comparison circuit (hereinafter referred to as "CO
M”) 91 and the output signal from this C0M91, the multivibrator 9 triggered from 1 to
2 and the main body 51 via a drive circuit 93 that changes the output signal of this multivibrator 92 into an appropriate drive signal.
storage element 81 for audio data and memory pack 52 in
It is connected to the remaining capacity indicator light 9/I (corresponding to indicator lights 33 and 34 in FIGS. 2 and 3) that displays the remaining storage capacity of the audio data storage element 103 in the CPU 79. This remaining amount indicator light 94 is driven by the control signal.

The address/data/control bus 75 is connected to the connector 54
．． 55 to the address/data/control bus 101 in the memory pack 52, and supplies each of the control signals to the audio data storage element 103 and the control storage element 97 in the memory pack 52.

Inside the control storage element 97, there is a RAM 98 for storing address pointer data at the time of starting recording to the audio data storage element 103 in the memory pack 52, and
A RAM 99 for storing address pointer data at the end of recording to the storage element 103 for audio data in the memory pack 52 and a storage element 103 for audio data at the end of the playback operation from the storage element 103 for audio data in the memory pack 52. The RAM 100 stores address pointer data.

Note that each RA of the control storage element 97 in the memory pack 52
Each RA in the main body 51 is stored in the RAM in the memory element 103 for M■ to ■98 to 100 and audio data 19-.
A backup battery 102 is connected in the same way as for M, and prevents stored data from volatilizing when the power is turned off.

By connecting the memory pack 52 described above to the main body 51 via the connectors 54 and 55, the audio data storage element 103 in the memory pack 52 is connected to the audio data storage element 81 in the main body in a so-called cascade connection. It will be done.

Next, a circuit example of the audio detection circuit 61 in the circuit diagram of FIG.
This will be explained using the circuit diagram shown in the figure.

The output signal of amplifier 58 in FIG. 4 is input to input terminal 1 in FIG.
12 to one input terminal of the C0M111. In the input terminal of this C0M111 usage, a variable resistor 114 is grounded to the terminal 113 to which a positive voltage is loaded.
The sliding point of this variable resistor 114 is connected via a capacitor 115.

A reference input voltage is set in advance by the variable resistor 114 and capacitor 115. The output of the COM20-111 is connected to the input terminal of the monostable multivibrator 116, and the monostable multivibrator 116
The output terminal 119 of is connected to the PIO 76 shown in FIG. Also, a capacitor 1 for adjusting the logic level "1" time of the monostable multi-by-break 116
7 and resistor 118 connect the monostable multivibrator 1
It is externally attached to 16.

FIG. 6 is a waveform diagram showing the operation of the sound detection circuit shown in FIG. This will be explained using the waveform diagram shown in FIG.

When an audio signal as shown in FIG. 6(a) is input to the input terminal 112, the variable resistor 114 and the capacitor 115
When the level of the audio signal is higher than the reference voltage level (S in FIG. 6) set in , the output of C0M111 becomes logic level 111 II. Therefore, C0M111
As shown in Fig. 6 (b), the output waveform of is at logic level HI II as long as the audio signal is between a level higher than the reference setting voltage, and becomes logic level ll when it is at a low level.
A pulse waveform at "O" is output.

The monostable multivibrator 116 is triggered by the pulse waveform shown in FIG. 6(b), and the time (
During T) in FIG. 6(c), even if the trigger pulse of the C0M111 reaches the logic level NOII, the output level of the monostable multivibrator 116 remains at the logic level 1.
111! Therefore, as shown in Fig. 6 (c), during the first three pulses in Fig. 6 (b) where trigger pulses are frequently issued, the hollow chamber multi-vibration break 1
The output of No. 16 continues to be at the logic level "1", and after the next (b) fourth pulse falls, the output of No. Since the level of the applied audio input signal continues to be lower than the reference setting voltage level S, the output level of the monostable multi-bi break 116 falls to logic level "0" and the next trigger pulse is input. The logic level continues to be "'0" until it is reached.

This is how this audio detection circuit works! 11 The output signal of the stable multi-by-break 116 becomes the II OII level when the audio input signal is lower than the reference voltage level for a certain period of time, so this "O" ON loop prevents the generation of an interrupt signal for recording. By doing so, it is possible to stop recording while the level of the audio input signal is lower than the reference level, and to prevent the audio data storage element 81.103 from being wasted.

Furthermore, since the output signal of the monostable multivibrator 116 itself can be used as an interrupt signal, it is also possible to obtain an automatic recording start function using this audio detection circuit.

Next, the operation of the embodiment shown in FIG. 4 will be explained using the flowcharts shown in FIGS. 7 to 12. In addition, Fig. 7 shows C
8 is a flowchart showing the interrupt operation of the PU 79, FIG. 8 is a skip and repeat operation, FIG. 9 is a recording operation, FIG. 10 is a playback operation, and FIG. 11 is a flowchart showing a recording/playback operation when a memory pack is inserted.

First, by turning on the power switch 27 (step (22) in FIG. 8), the CPU 79 controls the control memory element 8.
Each part is initialized according to the program written in the ROM 88 of No. 3 (step (23)). slj That is, PI076 for accepting interrupts, RAM for temporarily recording address pointer data of the audio data storage element 81 ~
(2) Initialize the data in 84 to 86, the audio data storage element 81, the series/parallel variable circuit 64, etc. After initialization is completed, the solid-state recording/playback device enters stop mode (step (2)
4)) Interrupts caused by operating switches such as the recording switch 21, playback switch 22, skip switch 24, repeat switch 25, stop switch 26, etc., and 1 byte obtained by dividing the output clock signal of the VCO 73 by 8 using the frequency dividing circuit 74. Waits for an interrupt to occur at the signal J:.

The flowchart of FIG. 8 shows the flow when a skip operation or a repeat operation is performed, but for convenience of explanation, the recording operation will be explained first using the flowchart of FIG. 9.

(1) Recording operation When the recording switch 21 is turned on for recording (step (47) in FIG. 9), the interrupt register reads the interrupt information and issues an interrupt to the CPU 79. CPU79
executes the interrupt according to the interrupt operation flowchart shown in FIG. 7, and determines which operation command it is.

That is, in the flowchart of FIG.
After 79 is initialized, it reads the data of the interrupt register of PI076 and waits for an interrupt (step (
1)).

Next, step (2)) to determine whether there is a memory pack.
If there is a memory pack, the operation that accompanies the connection of the memory pack, for example, when the storage capacity of the audio data storage element 81 in the main body is full and the end marker comes out, the audio data in the memory pack 52 is memory element 103 for
The memory pack 52 of RΔM■ to ■84 to 86 in the control memory element 83 that accompanies the switching of the memory element to
A series of operations such as switching to RAMs 1 to 98 to 100 in the memory pack 52 and lighting the indicator light 29 indicating that the memory pack 52 has been inserted are performed (step (3)).

Next, in step (4, )), the presence or absence of a 1-byte interrupt signal is determined, and the recording switch 21 or the playback switch 22
Detects the 1-byte interrupt signal generated by the operation, and performs the necessary operation for each. For example, when recording,
The audio data converted into 8-bit bit-parallel data in 1-byte bits by the serial-parallel conversion circuit 64 is sent to the CPU 7.
The audio data is sent via the 9-head address data control bus 75 (step (11)), and the audio data is recorded from the CPU 79 to the audio data storage element 81 (step (12)).

Thereafter, the address data in the audio data storage element 81 is incremented to continue the recording operation (step (15)), but when the end marker appears or the stop switch 26 is operated, the recording operation is stopped. Perform operations such as clearing the counter, stopping 1-byte signal interrupts, and writing address pointer data to the RAM 85 when recording ends (step (16)).
.

Also, during playback, the audio data storage element 81
The CPU 79 then transfers the audio data to the parallel-to-serial conversion circuit 67 (step (14)) and reproduces the audio signal.

Thereafter, in order to read the next audio data, the address data of the audio data storage element 81 is incremented (step (15)), and at the end of playback, the same stopping process as at the end of recording is performed (step (16)).

In addition, if such a 1-byte signal for recording and playback is not generated, it is determined whether there is a repeat signal (step (5)), and if there is a repeat signal, the control memory corresponding to the repeat operation is A series of processes such as counting down the ROM 88 in the element 83 and sequentially lighting up the marker indicator lamps 28 in the opposite direction are performed (step (17)). Thereafter, the process proceeds to determination of playback after repeat (step (7)), recording (step (8)), etc.

If it is not a repeat operation, it is determined whether it is a skip operation or not (step <6)). If it is a skip operation, the address pointer data of the ROM 88 in the control storage element 83, for example, associated with the skip operation is Steps of performing processes such as addition and sequential lighting of marker indicator lights 28 indicating partial areas in the audio data storage element 81 (
18) 1. Next, proceed to a discrimination operation such as playback (step (7)) or recording (step <8)).

Next, if it is not a skip operation, or if the processing necessary for a repeat operation or a skip operation has been completed, it is determined whether or not it is a reproduction operation (step (7)).

If it is a playback operation, operations such as accepting an interrupt of a 1-byte signal necessary for the playback 03 operation, starting the operation of the VCO 73, and canceling the muting state of the muting circuit 71 are performed 28- (step (19)). Next copy operation (step (
9)) Proceed to judge whether it is a stop operation (step (10)), etc.

Next, it is determined whether the recording operation is to be performed (step <8>).
). In the case of a recording operation, operations such as accepting an interrupt of a 1-byte signal necessary for the recording operation, starting the operation of the V6O13, and activating the muting operation of the muting circuit 71 are performed (step (20)). The process proceeds to a determination as to whether or not it is the next copy operation (step (9)).

After performing the process necessary for recording or playback, it is determined whether the operation is a copy operation to the memory pack (step (9)). If the operation is a copy operation, then In step (21>), operations necessary to transfer the audio data from the audio data storage element 81 in the main body to the audio data storage element 103 in the memory pack 52 are performed (step (21>), and after the transcription operation is completed, , the process moves to a determination as to whether or not it is the next stop operation (step (10)).

The presence or absence of a 1-byte signal (step (4)), the presence or absence of repeat operation (step (5)), the presence or absence of a skip operation (step (6)), and the presence or absence of a playback operation (step (7))
), whether it is a recording operation or not, step (8)), and whether it is a copy operation or not, step (9)).
Finally, it is determined whether or not it is a stop operation (step (1)
0)), in the case of this stopping operation, the process necessary for the above-mentioned stopping is performed (step (16)). If it is not a stop operation, the interrupt register is read after reinitialization and step (1)) is performed to prepare for the next operation.

The CPU 79 performs the above-described judgment operation, but when the recording switch 21 is turned on, the CPU 79
9 is interrupted by a 1-byte signal, so the 12th
The process moves to a loop with the 1-byte signal in step (4) in the figure, and the CPLI starts controlling the recording operation.

Returning to the flowchart of FIG. 9, details of the recording operation of the CPU 79 will be explained.

When the recording operation is determined in step (47), the marker indicator lamp 28 corresponding to the address pointer data written in the RAM 84 in the control storage element 83 lights up (step (/18)).

This is the audio data storage element 8 that starts this recording operation.
This shows the divided area immediately before the divided area No. 1.

Next, it is determined whether or not there is data in the RAM 85 in the control storage element 83 (step (/l9)). This judgment is made to determine whether or not a recording operation has been performed before starting this recording operation, and the address pointer data before the end of the previous recording has been recorded in the RAM 85.

And the address pointer data at the end of the previous recording is RA
If the address pointer data is recorded in the ROM 85, the next address pointer data after the address pointer data at the end of the previous recording is read out from the ROM 88 (step (50)').
, proceed to the next step (51).

If there is no data in the RAM 85, the process proceeds to step (51) in the same way as in 31, and it is determined whether address pointer data is held in the ROM 88 (step (51)). If address pointer data is held in this ROM88, this ROM88
Preset the address pointer data held in the address counter in the CPU 79 (step (53)
). If no address pointer data is held in the ROM 88, the CPU 79 presets the address pointer data next to the last address pointer data at the end of the previous recording read in step (50).

That is, when a skip operation or repeat operation, which will be described later, is performed by this series of operations, recording is performed from the first address of the partial area next to the partial area selected by the skip or repeat operation, and the skip operation or repeat operation is performed. If this is not done, even if there is still a recording address in the divided area in the audio data storage element 81 at the end of the previous recording, the next recording 32- operation will always be performed in the next divided area. This allows recording to start from the first address.

After specifying the recording address in the audio data storage element 81 in this state, the CPU 79 closes the converted signal bypass circuit 66 of the delta modulation circuit 63 and the delta demodulation circuit 68 (step (54)), and also prevents howling. Therefore, the muting circuit 71 is turned on (step (55)).

Further, the operation of the variable clock VCO 73 is started (step (56)), and at the same time, the input/output switching circuit 65 is switched to the modulation side (step (57)).

In this way, the preparation system for recording has been completed, and in this state, when an audio signal is applied from the microphone 56 to the reed of the solid-state recording and reproducing device, this audio signal is amplified by the amplifier 58 via the tangential line 53. It is applied to LPF62. LPF
After being band-limited to the required frequency band at 62, this audio signal is applied to a delta modulation circuit 63 and encoded into a digital signal.

A part of the audio signal encoded in this way is immediately passed through the conversion signal bypass circuit 66 to the delta demodulation circuit 6.
8 (step (58)), and is demodulated by LPF 6 again (step (58)).
After the band is limited by 9, the slope value of the voltage waveform is detected by 5D72 (step (59)), and depending on the magnitude of this slope value, the VCO 73
The oscillation frequency of is changed (step (60)).

The oscillation pulse of this VCO 73 is used as a clock pulse for the delta modulation circuit 63 and delta demodulation circuit 68'c described above.

That is, this delta modulation and demodulation coarsens the clock frequency according to the slope of the waveform to be modulated and demodulated. This is because when modulation and demodulation is performed using clock pulses of a uniform frequency, the modulation and demodulation accuracy decreases where the slope of the waveform to be modulated and demodulated is steep, and on the other hand, it has extra accuracy where the slope is gentle. This is done to maintain sufficient accuracy by increasing the clock frequency where the slope is steep, and to lower the clock pulse frequency where the slope is gentle to avoid unnecessary accuracy. By performing delta modulation and demodulation using a clock pulse frequency proportional to the slope value of the waveform to be modulated and demodulated in this manner, delta modulation and demodulation can be performed with sufficient accuracy depending on the aspect of the waveform to be modulated and demodulated.

The oscillation output of the VCO 73 is supplied to the above-mentioned delta modulation circuit 63 and delta demodulation circuit 68, and is also supplied to the frequency division circuit 74.
After being frequency-divided by 8 and converted into a 1-byte signal (step (61)), it is supplied to the CPU 79 etc. via the serial/parallel conversion circuit 64, parallel/serial conversion circuit 67, and address/data/control bus 75, and the audio signal is converted into a 1-byte signal. This is used as a timing pulse for writing or reading signal data into the audio data storage element 81 or the like. In this state, the CPtJ79 accepts the aforementioned 1-byte signal interrupt (step (4)
), (62)).

Next, the value of the address counter of the CPU 79 and the value of the ROM 88
It is determined whether the data match (step (63)). If the value of the address 35-counter of the CPU 79 does not match the data of the ROM 88, the value of the address counter of the CPU 79 is incremented by one address, and the address data in the audio data memory 81 is changed (step (64)). . This operation is then repeated until the address counter of the CPU 79 and the data of the ROM 88 match (steps <63) and (64).
,)>.

That is, since address pointer data indicating the starting address of each partial area of the audio data storage element 81 is recorded in the ROM 88, when starting recording, each part of the audio data storage element 81 must be Recording is started from the first address of the partial area.

When the leading address of each partial area in the audio data storage element 81 is read out in this manner, an address pointer data number is set corresponding to this partial area (step (65)). At the same time, this set address pointer data is written to RAM 84 (step (6)
6)).

In other words, the RΔM 84 contains the A36- Address pointer data will be recorded.

At the same time, the marker indicator light 28 corresponding to this address pointer data lights up (step (67)). In this state, the address counter in the ROM 88 is incremented in preparation for the next 8-tone operation.

(Step (68)).

When the recording address in the audio data storage element 81 is determined in this way, the bit-serial digital signal that is the output signal of the delta modulation circuit 63 is transferred to the serial-parallel conversion circuit 63.
4, it is converted into parallel data of 8 bits each (bit parallel data) (step (69)), and is stored in the audio data storage element 81 or, if the memory pack 52 is used, the audio data storage element 103 in the memory pack 52.
Then, the audio signal is stored in the form of bit parallel data (step 70).

Next, when writing of 8-bit bit-parallel audio data using a 1-byte signal is completed, the address counter of the CPU 79 is incremented, and the audio data storage element 8 is incremented.
Preparation is made for writing a bit parallel signal to the next address within 1 (step (71)).

In this state, it is determined whether or not there is an end marker indicating that the storage capacity in the audio data storage element 81 is exhausted (step (74)). If the end marker does not appear, it is determined whether or not the stop switch has been operated. (Step (75
)). If the end marker does not appear and the stop switch is not operated (step (75)), the process returns to step (65) and continues the recording operation after confirming the address of the address pointer data.

In this case, if the address pointer data number set in the previous recording operation and the address pointer data number for the next recording are the same, the RAM in step (66)
(2) Address pointer data is not written to 84.

Then, when recording is to be continued into the next divided area of the audio data storage element 81, step (65
) is incremented, and this incremented address pointer data is written to RAM 84 in step (66).

In this way, audio data is sequentially recorded into the audio data storage element 81 or the audio data storage element 103.

Next, when the storage capacity of the audio data storage element 81 is full and an end marker appears (step (74)), this end marker is written to the RAM 84 (step (78)).
), the 1-byte signal interrupt is stopped (step (7)
9)), it is determined whether there is a memory pack (step (80)).

If there is a memory pack, recording into the memory pack is performed according to the flowchart of the recording operation to the memory pack shown in FIG. 10, which will be described later. If there is no memory pack, the recording operation must be ended now, so the address counter is cleared (step (81)), and the solid-state recording and playback device 20 enters the stop mode and stops its operation (step (81)). 82)).

Note that if you want to stop the storage before the end marker appears, that is, if there is still storage capacity left in the storage element 81 for voice data, operate the stop switch 26 (step (75)) to save 1 byte. The signal interrupt is stopped (step (76)), and the address pointer data at this time is written to RAM 85 (step (77)).
. That is, the address pointer data at the end of recording is written into the RAM 85. Thereafter, the address counter is cleared (step (81)) and the stop mode is entered (step (82)), as in the case without the memory pack described above.

Note that the recording time of the partial area is approximately 10 seconds in this embodiment, and the marker indicator lights 28 are sequentially turned on every 10 seconds to display the recorded area.

That is, the 1-byte signals are counted by the CP and LJ 79, and when the preset number of 1-byte signals generated in 10 seconds is reached, the marker indicator lamps 28 are turned on one by one.

The marker indicator light 28 is converted into a decimal number and driven by a drive circuit 89 connected to the address/data/control bus 75.

4O- (2> Skip recording operation If the user wishes to record from an arbitrary Nth partial area, by turning on the skip switch 24, the C
PU79 accepts the interrupt (steps (6), (25)
)), determines the operation mode and moves to skip operation (
Step (18)).

In this case, the CPU 79 sequentially reads data for comparison with the number of 1-byte signals generated within a preset time (10 seconds in this embodiment) from the ROM 88 of the control storage element 83 (step (26)). Based on this data, only one corresponding marker indicator light 28 is sequentially blinked (step (27)).

In this case, in order to ensure accurate operation by the user, the marker indicator light 28 is set to blink at a rate of one marker every 0.4 seconds in this embodiment.

When the marker indicator light 28 lights up to the point where the user desires to record, step (28) is performed to stop the skip operation.
)), the incrementing operation of the address counter of the ROM 88 is stopped and the read data is held in this state (
Step (29)).

If you want to record in a closed state, perform the recording operation described above and set the recording switch 21 to 0NL (step (47)).
Hereinafter, the recording operation will be performed according to the chart shown in FIG.

In this case as well, it is determined in step (51) whether address pointer data is held in the ROM 88, and if address pointer data is held,
That is, when a partial area of the audio data storage element 81 is selected to perform the skip operation and start the recording operation, the address pointer data of the ROM 88 is preset in the address counter of the CPU 79 (step (53)).
Since recording is started from this address, recording is performed from the leading address of the partial area of the audio data storage element 81 selected by performing the skip operation. The subsequent recording operation is the same as in normal recording mode.

(3) Repeat recording operation In this case, when the user wants to record the audio signal from the smallest divided area of the audio data storage element 81 first, the partial area can be changed to an address by operating the repeat switch 25 for convenience. This function has a function of quickly selecting the position of a desired partial area by reading out from the larger one at high speed.

That is, by turning on the repeat switch 25 (steps (5), (34)), the CPU 79 immediately starts the repeat process (step (17)). In this case, if the memory pack 52 is connected, in order to start the repeat operation from the memory pack 52, first it is determined whether the memory pack 52 is present or not (step 35).
), if there is a memory pack 52, the memory pack indicator 29 lights up (step (/10)), and the control memory element 83 in the main body 51 is switched to the control memory element 97 in the memory pack 52 (step (/10)). /l 1 ) ”), the address pointer data is sequentially read from the ROM 88 in the control storage element 83 (step (42)). However, in this case, the address pointer data is read out sequentially from the largest to the smallest. To go.

Next, in response to reading of the address pointer data 43-1 in the ROM 88, the marker indicator lights 28 blink sequentially from the largest number to the smallest number. The read speed in this case is the same as the read speed in the skip operation (step (43)).

In this way, the partial areas of the audio data storage element 103 in the memory pack 52 are sequentially read out, and whether or not the reading in the memory pack 52 is completed is determined based on the presence or absence of the end marker.Step (/I/I) ), if reading from the memory pack 52 is not completed, the same operation is repeated until reading from the memory pack 52 is completed.

When the end marker is detected and it is determined that the reading of the memory pack 52 is completed (step (4, 4,)), the control memory element 97 of the memory pack 52 is transferred to the control memory in the main body 51. Switch to element 83 (
Step ('/l-5)). Simultaneously with this switching operation, the memory pack indicator light 29 goes out (step (46)
) ).

Subsequently, the ROM 88 of the control memory element 83 in the main body 51
Step (36)) reads out address pointer data sequentially from the highest number (step (36)). Accompanying this reading operation, the marker indicator lamps 28 blink sequentially from the highest number (step (37)).

If the repeat operation is continued in this way, the above operation is repeated and the repeat switch 25 is turned OFF.
If it has been F (step (38)), at this point R
The subtraction of the address pointer data of the OM88 is stopped and the read address pointer data is held (step (39)).The recording operation from this stage onwards is the same as in the case of skip recording, and is performed according to the flowchart in FIG. It will be done.

(4) Repeating recording and stopping operations In this case,
This is a case where each of the above-mentioned recording operations is performed multiple times within the capacity of the data storage element.

That is, when recording a plurality of pieces of information after a certain period of time has elapsed or selecting and recording a plurality of divided areas, this is done through the stop operation, but if the recording sound operation was performed before the stop operation, the CPU 79 is a stop operation (step (
10) and (75)), step (76)) to stop the 1-byte signal interrupt, and step (77) to record the address pointer data at this time in RAM 85.
)), clear the address counter step (81)
), enters stop mode (steps (16), (82
)). Then, by operating the recording switch 21 again (steps (8), (47)), a marker indicator light corresponding to the address pointer data written in the RAM 84 and indicating the starting address of the partial area at the time when recording was started last time. 28 is turned on (step (/18)), and the divided area of the audio data storage element 81 in which audio data has already been recorded is displayed.

Then, write the address pointer data at the end of the previous recording to R.
Step (49)) to read from the AM 85, step (50)) to increment this data, and send this incremented address pointer data to the CPU 7.
Step (52) to preset the address counter of 9.
)), the address counter continues to be incremented by 1 until the address pointer data preset in this address Karakun matches the starting address of each partial area of the audio data memory 81 stored in the ROM 88 (step ( 63), (64)) Even if there is sufficient capacity in the partial area at the end of the previous recording, recording is performed from the next partial area at the end of this recording. Note that when recording is performed again in a previously recorded partial area, the previously recorded audio data is updated and newly recorded audio data is stored.

(5) Reproduction operation When the reproduction switch 22 is turned on for reproduction (steps (a), (83)), the P 1076 reads the interrupt information and interrupts the CPU 79 with the interrupt signal wA77.

When this interrupt signal is generated, the CPU 79 determines whether or not there is held data in the RAM 86 of the control storage element 83 (step (84)). If there is held data in the RAM 86, this held data is read out and incremented by 1 byte (step (85)).

In other words, the fact that there is retained data in the RAM 86 indicates that a previous playback operation was performed, and this R
Since the data held in the AM 86 is the address pointer data at the end of the previous playback, by incrementing the data by 1 byte, the data stored in the audio data storage element 8 is
This is because the reproduction operation is performed from the address following the previous reproduction operation of 1.

Next, if there is no held data in the RAM 86, or if there is held data, this held data is incremented by 1 byte, and then it is determined whether or not there is held data in the ROM 88 (step (86)). This determination is whether a skip operation or a repeat operation has been performed.

If there is data held in the ROM 88, a skip or repeat operation has been performed, so this data is transferred to the CP.
By presetting the address counter of U79 and performing a skip or repeat operation>48--Prepare for reproduction from the selected partial area of the audio data storage element 81 (step (88)). If there is no retained data, the skip operation or repeat operation has not been performed, so the CPU 79 is preset with the data of step (85), which is incremented by 1 byte from the address pointer data at the end of the previous playback operation, and the data is continued from the previous playback operation. (step (87)). In this state, turn off the marker indicator 28 by 10 steps (89
)), in preparation for displaying the partial area during the subsequent playback operation.

Next, the CPU 79 opens the converted signal bypass circuit 66 of the delta modulation/demodulation section (step (90)) and turns off the muting circuit 71 for howling prevention (step (91)). In addition, variable clock VC
In order to start the operation of O73 (step (92)), since no control voltage is generated at the frequency control input terminal of this VCO 73 at the time of starting reproduction, this VCO 73 starts oscillating at its free running frequency (step (93)). )).

At the same time, the input/output switching circuit 65 is switched to the demodulation side (step (94)).

Next, the output pulse of the V'CO 73 is frequency-divided by 8 by the frequency dividing circuit 74 to generate a 1-byte signal (step (
95)). When a 1-byte signal is generated in this way, CP
U79 accepts the interrupt by this 1-byte signal (step (96)), and determines whether the address counter of CPLJ79 and the data of RAM 84 are the same value (step (97)). and CPU7
If the address data of 9 and the address pointer data of RAM 84 do not match, the address counter of the CPU 79 is incremented (step (98)) and continues to be incremented until they match (step (97)).
, (98)).

That is, by this operation, the partial area of the audio data storage element 81 of the recording pile at the time when recording started is read out.

In this way, when the address counter data of the CPU 79 and the address pointer data of the RΔM 84 match,
The matched value is stored in the audio data storage element 8 of the CPU 79.
Set address counter 1 (step (99))
. At the same time, the marker indicator light 28 of the partial area corresponding to this number is turned on (step (100)), and the address pointer data in the ROM 88 is subsequently incremented by 1 in preparation for the next reading (step (101)). A step of reading data from a partial area of the audio data storage element 81 in which audio data is recorded (
102)) The bit-parallel audio data based on the read 1-byte signal is converted into a temporally continuous bit-serial pulse signal by the parallel-to-serial conversion circuit 67 via the input/output switching circuit 65 (step (103)). . After that, delta demodulation is performed in the delta demodulation circuit 68 (step (
104)). The demodulated signal demodulated by this delta demodulation circuit 68 passes through an LPF 69, adjusts the volume with a variable resistor 70, and then passes through a muting circuit 71 to an amplifier 5.
9 and output as an audio output signal 51-, which is reproduced by the speaker 57 (step (105)).

On the other hand, a part of the output signal of the LPF69 is 5D72,
The slope of the amplitude is detected, and an output voltage is generated depending on the magnitude of this slope. Then, the frequency of the output clock pulse of the VCO 73 is controlled by the VCO 73 according to the magnitude of the output voltage of the 5072 (step (106)).
.

That is, by reading and reproducing the signal using a clock frequency that corresponds to the magnitude of the slope of the voltage amplitude of the demodulated signal, it is possible to reproduce the audio signal on the same time axis as when it was recorded.

After 1 byte of audio signal is played in this way, the address counter of the CPU 79 is incremented,
Preparation is made for reproduction of the next 1 byte of audio signal' (step (107)). In this state, it is determined whether the RAM 84 matches a certain preset value (step (
108)). When the value of this RAM 84 matches the set value, the remaining capacity indicator 33 or 3
452- lights up (step (109)).

That is, in the case of this embodiment, if the remaining time at the end of the storage capacity of the storage element 81 for audio data to be recorded is 20 seconds or 10 seconds, a warning is given of the remaining capacity of the storage element 81 for audio data. The remaining amount indicator light 33 or 34 lights up.

On the other hand, in a step (110)) to detect the presence or absence of an end marker in parallel, if the end marker has not yet appeared,
That is, if there is still room in the storage capacity of the audio data storage element 81, it is detected whether or not the stop switch 26 is operated next (steps (10) and (111)).
). If the stop switch has not been operated, it is subsequently determined whether or not the cue switch 23 has been operated (step (112)).

In this way, if the end marker is not recorded and neither the stop switch 26 nor the cue switch 23 is operated, the address pointer data of the address counter of the CPU 79, that is, the audio data incremented in step (107). It is determined whether the next reproduction address in the storage element 81 matches the data recorded in the RAM 85 (step (113)).

In other words, it is determined whether or not the audio signal recorded by this operation still remains.

If it is determined in this way that the address pointer data of the address counter of the CPU 79 and the data in the RAM 85 do not match, this indicates that there is still recorded audio data, so the steps continue. Returning to (102), the next audio data is read from the audio data storage element 81 and reproduced.

Note that the address pointer data of CPU79 and RAM08
If the data matches the data of 6, it indicates that recording in the partial area in the audio data storage element 81 has already been completed, but the next audio data storage element 8
In order to reproduce the recording in the 5 partial areas within 1, the next address pointer data is read from the RAM 84 (step (114)). The read address pointer data is then preset in the address counter of the CPU 79 (step (115)).

Then, the audio data stored in the partial area of the audio data storage element 81 corresponding to the newly preset address pointer data is played back, and for this purpose, the process returns to step (102) and the address pointer data preset in the address counter is reproduced. Step address pointer data (
100), the audio data in the partial area of the audio data storage element 81 corresponding to this address pointer data is read out (step (100)).
102)).

In this way, the recorded data is sequentially played back, and when the storage capacity of the audio data storage element 81 approaches its end, the remaining indicator lights 33 and 34 light up as described above, and
When the storage capacity in the audio data storage element 81 is completely filled, an end marker appears, this end marker is detected in step (110), and the interrupt operation of the 1-byte signal to the CPU 79 is stopped (step (116) )).

55- Next step (117) to determine the presence or absence of a memory pack.
), if there is no memory pack, the address counter of the CPU 79 is cleared (step (118)), and a stop mode is entered (step (119)). If there is a memory pack, it will be explained later.

If you wish to stop the playback operation even though the storage capacity R in the audio data storage element 81 still remains, operate the skip switch 26 (step (10).
), (1'11)), the interrupt of the 1-byte signal to the CPU 79 is stopped (step (120)), and the address pointer data at this time is written to the RAM 86 (step (121)).

That is, address pointer data at the end of reproduction is recorded in the RAM 086.

After writing the address pointer data to the RAM 86 in this manner, the solid-state recording/reproducing device 2, Q- enters the stop mode (step (119)).

Note that the reproduction/cueing operation in step (112) will be described later.

-56= In this way, the playback operation according to the present embodiment is performed by using the address pointer data of the audio data storage element 81 while the CPtJ79 is reading the audio data and the RAM0 of the control storage element 83.
The address pointer data recorded in 86 is constantly compared, and when both data become the same, the address pointer data stored in RAM 84 that is closest to and at the highest level is read out. A partial area of the audio data storage element 81 is selected, and the audio data is read out and reproduced.

In other words, the unrecorded portions are skipped and only the recorded portions are sequentially played back.

(6) Skip/playback operation In this case, the user desires to playback from a certain partial area in the audio data storage element 81 or the audio data storage element 103, and selects and plays the partial area. . In this case, when the skip switch 24 is turned on and off,
The CPU 79 determines the skip operation mode (step (6)), and executes the skip processing program (step (18)).

That is, according to the skip 70-yard in Figure 8,
When the skip switch 24 is operated, step (
25)') CPtJ79 is the RO in the control memory element 83
The address pointer data is sequentially read from the M88 (step (26)), and the indicator lamps 28 in the partial areas corresponding to the read address pointer data are sequentially turned on one by one (step (27>)).

Skip switch 2 is the same as the operation during skip recording below.
Step (28))
If the end marker is not turned off, step (30)) determines whether there is an end marker. If the end marker does not appear, continue reading the address pointer data (step (26)). If the end marker appears, the next step is to read the address pointer data. The presence or absence of the memory pack is determined (step (31)), and if there is no memory pack, it is meaningless to continue skipping any further, so the solid-state recording and reproducing device 20 enters the stop mode (step (24,)).

In addition, when the memory pack 52 is connected, the control memory element 83 in the main body 51 is switched to the control memory element 97 in the memory pack 52 (step (32)), and the memory pack is being skipped. Step (33) to turn on the memory pack indicator light 29 to indicate that
)) Continue reading the address pointer data (step (26)). Note that the memory pack indicator light 29 indicates the reading of the END marker written in the RAM 98 in the control memory 83 in the memory pack 52. , or when the solid-state recording and reproducing device 20 enters the stop mode (step (24)), the light is turned off.

In this way, when the selected partial area is reached during the skip operation, the skip switch 24 is turned off (step (28)). When the skip switch 24 is turned OFF, the address pointer data in the ROM 88 at this point is incremented and stopped, and is held in this state (
Step (29)).

59- When performing the following reproduction, when the reproduction switch 22 is turned on, the CPU 79 determines that it is in the reproduction mode, step <7)), and executes the reproduction program. (Step (19)).

That is, when the playback switch 22 is turned on (step (83)), it is determined whether or not a playback operation has been performed before this playback operation based on whether or not there is data in the RAM 86 (step (84)). If it is determined that the previous playback was performed, read the address pointer data of 86 for this RA and increment it by 1 byte.
85)), and if no previous playback operation has been performed, it is determined whether or not there is data held in the ROM 88 (step 86)), in which case the step (2) described above is performed.
), the address pointer data during skip playback is RO
Since it is held in M88, step (88)
, preset this data in the address counter of CPLI79, and then proceed to playback 0 in the same way as the playback operation described above.
One operation is performed from the partial area where this skip operation is stopped. Note that by performing the 60-line skip operation, the marker indicator light 28 that was lit during playback is turned off.

(7) Repeat 1-/Playback operation In this case, by turning on the repeat switch 25 during playback, the speed is faster than the recording address at the rear of the audio data storage element 81.103, which corresponds to the rewinding operation of a normal tape recorder. The address pointer data is sequentially scanned to select a necessary playback position.

By turning on the repeat switch 25, CPtJ
79 determines whether the mode is repeat mode (step (5)) and executes a repeat processing program (step (17)).

That is, by turning on the repeat switch 25 (step (34)), it is determined whether there is a memory pack or not (step (35)). Start repeat operation.

That is, the memory back indicator 29 indicating that there is a memory pack lights up (step (/l0)), and the control memory element 83 in the main body 51 is moved to the memory pack 52.
(Step (41))
, step (42)) of reading address pointer data from the ROM 88 in the control storage element 83 in order from the largest number to the smallest number; sequentially blinking the marker indicator lights 28 corresponding to this address pointer data (step (42));
43)).

In this way, the address pointer data is sequentially read and the presence or absence of the end marker in the memory pack 52 is determined (step (44,)).The above reading operation is continued until the end marker appears. In this case, the control memory element 97 in the memory pack 52 is transferred to the main body 51.
(Step (45))
, turn off the indicator light 29 indicating that there is a memory pack (step (46)), and store the address pointer data corresponding to the audio data storage element 81 in the main body in the ROM 88.
A step (36)) in which the numbers are sequentially read from the largest to the smallest number (36)), a step (37)) in which the marker indicator light 28 is sequentially blinked in response to this readout operation, and a FF operation of the repeat switch 25 is performed. It is determined whether or not (step (38)). The above operation continues as long as the OFF operation is not performed, and when the OFF operation is performed, the address data in the ROM 88 is incremented at that point.
Stop reading and keep this data (step (
39)).

When the next playback operation is performed in this state, the CPU 79 determines that the playback mode is in the skip playback mode described above (step (7)) and executes the playback processing program (step (19)).

That is, when the playback switch 22 is turned on (step (83)), the data in the ROM 88 is preset to the address counter of the CPU 79 (step (88)), and the portion in the audio data storage element 81 corresponding to this address pointer data is Start the playback operation from the area.

63- In addition, in this repeat operation program, the recording and playback operation is stopped in the memory pack 52 at the same time as recording and playback, and recording and playback is performed from an appropriate partial area of the audio data storage element 103 in this memory pack 52. Although this is a program that cannot be used, the memory pack 52 originally uses the audio data storage element 103, which has a smaller storage capacity than the audio data storage element 81 of the main body 51.
It is used for supplementary purposes to compensate for the lack of storage capacity of the audio data storage element 81 in the main body, and the storage capacity of the audio data storage element 103 is not that large, so it is a memory by repeat operation. This is because it was considered unnecessary to select a partial area in which to turn on the recording/playback operation of the audio data storage element 103 in the pack 52.

However, the audio data storage element 1 in the memory pack 52
It is also easy to add a repeat recording/playback mode within this memory pack 52 by using a large storage capacity storage element in the memory pack 52. Note that the indicator light 28 of the marker table 64, which was lit due to the reproduction operation before the repeat operation, is turned off by the repeat operation.

(8) Cue/playback operation This is a case where the audio data currently being played is skipped and the audio data recorded in the next partial area is played back.

This is carried out by turning on the cue switch 23 during playback.

That is, when the cue switch 23 is turned on, the CPU
79 is running the playback program (step (1)
9)) During this playback program, turn on the cue switch.
is detected (step (112)), and the RAM ■
Among the address pointer data recorded in 85, the address pointer data closest to the address pointer data of the storage element 81 for audio data currently being reproduced is read out (step (122)).
). Then, the address pointer data closest to and higher than the read address pointer data is read from the RAM 84 (step (114)).

Next, this read address pointer data is sent to the CPU.
79 address counter in a preset step (1
15)), the audio data is read from the address in the audio data storage element 81 corresponding to this address pointer data and reproduction is continued (step (102)).

Through this series of operations, the cue switch 23 is turned on.
When the partial area is played back, the partial area being played back is skipped and the next partial area is played back from the first address.

The water heading switch 23 is a type of switch in which, even if it is turned on once, it turns OFF as soon as the finger is released, and the next heading operation is performed by turning on the heading switch 23 again.

(9) Repeating play/stop operations Turn on the stop switch 26 during data playback.

In this case (step (111)), the address pointer data of the audio data storage element 81 from which audio data is being read is written into the RAM 86, and the solid-state recording and reproducing device enters the stop mode (step (119)). ), when the playback mode is set again (step (83)), it is determined whether there is data at the position where playback ended last time.
84)), playback starts from the address where the address pointer data of this data is incremented by 1 byte (
step (85)).

That is, when repeating the playback/stopping operation, playback is started following the address at which playback ended last time.

(10) Operation of the memory pack The audio data storage element 81 and various data storage RAMs 84-86 and the same type of audio data storage element 103 and RAMs 98-100 are stored in the operation body 51 of the memory pack. Memory pack 5 packaged for easy carrying
2 is provided on the outside of the main body, and the main body and the memory pack 52 provided on the outside are electrically connected by a connector 54.5°5,
It is used to extend the recording and playback time and to edit and copy audio data recorded in the internal audio data storage element 81.

Note that the audio data memory in the memory pack 52, the memory element 103, and the RAMs 98 to 100 are provided with a memory to prevent the stored data from volatilizing when the main unit is disconnected from the power supply. A backup memory 102 is provided within the memory pack memory 52 for backup purposes.

The memory pack 52 includes RAM 98~ with the same function as the main body 51.
The reason why 100 is provided is to avoid any inconvenience in reading the recording address of the audio data storage element 103 when the memory pack 52 in which audio data is already stored is used in a main body other than the main body 51.

Note that when this memory pack 52 is connected to the connector 54, the signal line 95 inside the main body 51 is grounded via the connector 54.55 and the signal line 96 inside the memory pack 52, and the CPU 79 determines that the memory pack is present. Step (2))
Various programs associated with the existence of the memory pack are executed (step (3)).

The contents of each program associated with the existence of this memory pack are stored, for example, in a control memory element inside the main body. (steps (32), (123), etc.), operation to read the address pointer data for the memory pack in the address pointer data storage ROM 88 following the address pointer data for the main body, the memory pack operation indicator light 29
(step (33), <124), etc.).

By providing the memory pack 52, in the case of a copy operation to be described later, the copy switch 21 is operated, and the audio data recorded in the audio data storage element 81 in the main body is transferred to the memory via the data save RAM 87. pack 52
It becomes possible to perform a copy operation in which data is sequentially recorded in the audio data storage element 103 in the audio data storage element 103 starting from the first address.

Furthermore, when the end marker of the audio data storage element 81 housed inside the main body 51 is detected, the marker 1 indicator light 28 lights up at the same time as the memory pack indicator light 29 (steps (33), (124,), etc.). Each marker indicator light 28 will display each partial area of the audio data storage element 103 in the memory pack 52.

Next, the operation when using the memory back 52 will be explained.

(a) Recording mode When the recording switch 21 is turned on, the CPIJ 79 determines the presence or absence of the memory pack 52 (step (2)). As described above, the presence or absence of the memory pack 52 is determined by connecting the memory pack 52 and installing the N line 95, thereby determining that the memory pack 52 is inserted.

When it is determined that the memory pack 52 is inserted, the CPU 79 switches the control memory element 83 in the main body 51 to the control memory element 97 in the memory pack 52 (step (123)), and turns on the memory pack indicator light. Turn on 29 (
Step (124>). Following this operation, the CPU 79
accepts a 1-byte signal interrupt (step (62)
)) Thereafter, recording is performed in the audio data storage element 103 in the memory pack 52 in the same manner as in a normal recording operation.

After recording the bit-parallel signal read out by the 1-byte signal in this way, the address counter in the CPLI 79 is incremented by steps (71
)), the presence or absence of an end marker in the memory pack 52 is determined (step (125)). If the end marker does not appear and the stop switch 26 is not operated (step (126)), the CPU 79 reads the next 1-byte signal (step (62)), and continues to read the audio data in the memory pack 52. memory element 103 for
Continue recording.

While recording continues in this manner, whether the end marker in the memory pack 52 is detected (step (1)
25)) When the stop switch 26 is operated, step (126)) the interruption of the 1-byte signal to the CPU 79 is stopped (step (127)), the address counter is cleared (step (128)), and solid-state recording playback is started. The device 2Ω- enters the stop mode (step (129)'
).

In this way, recording into the memory pack 52 is performed 71- finish.

(b) Skip/recording operation This is the skip/recording operation in addition to the above) operation in the empty memory pack, and the other operations are the same as the skip/recording operation described above. The explanation will be omitted.

(0) Repeat/recording operation This is similar to the skip/record operation in (b).

(d) Repeating the recording/stop operation The operation of the memory pack in the flowchart of FIG. 11 described above is added to the recording/stop operation of the main body,
The other operations are the same as the repeating recording/stop operations of the main unit, so their explanation will be omitted.

(e) Reproduction operation The above-mentioned memory pack operation is added to the reproduction operation of the main body.

(f) Skip/reproduction operation This is the addition of the memory pack operation shown in FIG. 11 to the skip/reproduction operation of the main body.

72-(g) Repeat/playback operation This is the repeat/playback operation of the main unit plus the operation of the memory pack shown in FIG. 11 described above.

(h) Cue/playback operation This is the cue/playback operation of the main body plus the above-described memory pack operation of FIG. 11.

(i) Repetition of playback/stop operation This is the addition of the memory pack operation in the flowchart of FIG. 11 to the repetition of playback/stop operation of the main body.

(11) Copying operation This copying operation is performed on the audio data storage element 8 in the main body 51.
This is an operation of transferring and transcribing a specified part or all of the audio data stored in the audio data stored in the audio data storage device 103 in the memory pack 52. This operation will be explained with reference to chart 70 in FIG.

First, the main unit is played back to find the audio data to be copied to the memory pack 52. After selecting the desired copy location, set to -H stop mode and press copy switch 21.
Turn on. By turning on this copy switch 21, C
The PU 79 determines that it is in the copy mode (step (9)), and executes the copy program described in detail below (step (21)).

That is, when the copy switch 21 is turned on (step (13)
0)), the presence or absence of the memory pack 52 is first determined (step (131)). If the memory pack 52 is not inserted, the copy operation is impossible, so the main body 51 enters the stop L mode (step (131)). 132)). If the memory pack 52 is inserted, the copy indicator light 30, which indicates that the copy operation is in progress, lights up (step 133).
), the CPU 79 sets the start address pointer data of the audio data storage element 103 in the memory pack 52 (step (13/I)).

Next, the data in the RAM 86 in the main body 51 is read out, and the address pointer data corresponding to the previous partial area in the audio data storage element 81 is read out from the RAM 84 (step (135)). This RAM■84
The address pointer data of RA in the memory pack 52
M■98 (step 136)) and reads the audio data in the audio data storage element 81 at the address corresponding to this address pointer data (step (1)
37). Then, this audio data is written to the audio data storage element 103 in the memory pack 52 (step (1)
38)). Next, the address counter of the CPU 79 is incremented (step (139)).

That is, by the above operation, the audio data storage element 81
A portion of the data to be copied is selected, and the data is sequentially copied starting from the first data recorded in the partial area where the copy switch 21 is turned on.

This copy operation is performed when the stop switch 26 is turned on (step (140)), the end marker is read from the RAM 84 (step (141)), or the address pointer data at the end of recording is read from the RAM 85. If it is issued (step (142)), the current address 75-pointer data is stored in RAM 99 in the memory pack 52 (step (143)), and the copy indicator 30 is turned off (step (142)). 14,4'')), the main body 51 enters the stop mode (step (145)).

In order to play a plurality of audio data among the audio data recorded in the audio data storage element 81 in the main body 51, the copy switch 21 is turned on each time (step (146)'), and the memory pack 52 The address pointer data recorded in the RAM 99 is read out, and the address pointer data corresponding to the partial area of the storage area in the audio data storage element 103 located after this is read out from the ROM 8.
8 (step (147)), and set the address in the audio data storage element 103 corresponding to the read address pointer data (step (148)).
)). Then, the read address pointer data is written into the RAM 98 in the memory pack 52 (step (149)). Then, the data is transferred from the audio data storage element 81 to the set row address =7 of the audio data storage element 103 and copied (step (138)). The following copy operation is the same as the previous copy operation.

In other words, the audio data storage element 1 having a larger address than the data read from the RAM 99 in the memory pack 52
The address pointer data of the partial area in 03 is stored in ROM8.
8, a segmented area in the audio data storage element 103 corresponding to the data is selected and transferred.

Although not shown in the flowchart of FIG. 12, the copy indicator light 30 is also turned on during the second copy operation.

Through the operations described above, the solid-state recording and reproducing device of this embodiment transfers and transfers the audio data stored in the audio data storage element 81 in the main body 51 to the audio data storage element 103 in the memory pack 52. However, the transfer speed in this case is determined by the signal processing speed of the CPU 79, so
Compared to a tape recorder that uses normal magnetic tape, it enables extremely high-speed copying.

Next, the operation of the indicator light of the solid-state recording and reproducing apparatus according to this embodiment will be summarized.

(1) Marker indicator light This marker indicator light is composed of a total of 18 LEDs that display a time of 180 seconds in units of 10 seconds, and has a delta modulation/demodulation circuit 63 necessary to obtain satisfactory audio quality.
．． The configuration is such that the number obtained by converting a frequency 10 times the clock frequency of 68 into bytes becomes the storage capacity of the partial area of the audio data storage element 81.103 necessary to store 10 seconds of audio data. Therefore, since the number of address data is the same, address data is set in advance every 10 seconds, and when the address data during actual operation and the set address data are compared, and the values become the same, 10 seconds have passed.

In this embodiment, in order to reduce the number of audio data storage elements 81.103, a variable clock system is used for the delta modulation/demodulation circuits 63.68, in which the clock frequency differs in proportion to the magnitude of the slope of the audio signal. Errors occur due to differences in information, but by using an average value for the address data value set in advance, the errors are averaged out for 10 seconds and do not cause any practical problems.

In addition, if a time base composed of a crystal oscillator or the like is set in the setting data, a pulse is generated from the time base every 10 seconds, and the address data of the data storage element is thereby recorded in the RAM 84.98. Accuracy can be improved.

(2) Remaining capacity indicator light In the solid-state recording and reproducing apparatus of the present invention, since the audio recording medium cannot be visually seen like a magnetic tailer, an accurate remaining capacity indicator is required.

In this embodiment, in addition to the marker indicator light 28 described above, the last one
When reaching 0 seconds and the last 20 seconds, the remaining capacity indicator lights 34 and 33 are flashed to alert the user. The timing of the lighting of the LED is
The multi-vibrator circuit is triggered by the above-mentioned lighting signal of the LED for displaying the remaining amount time, and the circuit performs a blinking display.

79- As another method, convenient means may be used, such as dividing the necessary portions of the marker indicator lights into different colors.

(3) Recording/playback/play/cue/stop/memory pack operation/skip/repeat/copy indicator light Lights up when the corresponding mode is being operated, and any indicator LED
Also, while the CPU'U79 is operating in the relevant mode, the CPU
It lights up according to the lighting data from 79. Please skip/
Repeat mode is related to recording or playback mode, so it does not light up by itself.

(4) All the indicator lights mentioned above are connected to each part via drive circuits 89 and 93.

[Effects of the Invention] As explained above, in the solid-state recording and reproducing device according to the present invention, a solid-state storage element is used as a storage means, and a memory pack that is packaged separately from this storage means is connected to the storage means. Since the audio signal is stored or reproduced using a solid-state storage element as a storage medium, there is no quality deterioration such as fluctuations in the audio signal or distortion noise caused by the 80-mechanical drive mechanism that occurs when a solid-state storage element is used as a storage medium, and it is There is no quality deterioration such as abrasion or scratches on storage media such as disks, and common effects such as high reliability and maintenance-free operation are obtained, and at the same time, the storage capacity of the solid-state storage element built into the main body is relatively small. Even in such cases, by connecting a memory pack, the storage capacity can be expanded, and long-term storage and playback can be performed.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the overall structure of the present invention, Figs. 2 and 3 are perspective views of an embodiment of the invention, and Fig. 4 is a block diagram showing the circuit structure of an embodiment of the invention. , Figure 5 is the fourth
FIG. 6 is a waveform diagram of the circuit of FIG. 5, and FIGS. 7 to 12 are 70-wire diagrams showing the operation of an embodiment of the present invention. . 61......Audio detection circuit 63
・・・・・・・・・・・・・・・Delta modulation circuit 64・
......Serial-to-parallel conversion circuit 65...
・・・・・・・・・・・・Input/output switching circuit 66...
・・・・・・・・・Conversion signal bypass circuit 67・
・・・・・・・・・・・・Parallel-serial conversion circuit 68...
・・・・・・・・・・・・Delta demodulation circuit 71...
...... Muting circuit 72...
・・・・・・・・・・・・・Slope detector 73・
・・・・・・・・・・・・・・・VCO74・・・・・・
...... Frequency divider circuit 76 ......
・・・・・・PIO79・・・・・・・・・・・・・・・
CPU80・・・・・・・・・・・・Operation button 81
．． 103...Storage element for audio data 82.102...
・Backup battery 83.97...Control memory element 84-87.98-100...RAM88.
・・・・・・・・・・・・ROM89.93...
...Drive circuit 90.94...Indicator light 91...C0M92...
・・・・・・・・・Multi Vibrator Bi1 Figure 83-

Claims (1)

[Claims] an encoding means for encoding an audio signal; a first storage means for storing the audio signal encoded by the encoding means; and a first storage means for storing the encoded audio signal stored in the first storage means. A connection means for electrically connecting a memory pack having a decoding means for decoding and a second storage means independent of the first storage means, and connecting the memory pack to the connection means. A solid-state recording and reproducing device characterized in that an audio signal can be successively stored or reproduced in the first storage means and the second storage means.