JPS6012596A - Solid recording/reproducing apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a solid-state recording and reproducing device for recording and reproducing audio signals in a solid-state storage element.

[Technical background of the invention and its problems] Conventionally, recording and reproducing devices use magnetic tapes, disks, etc. as storage media to detect changes in the amplitude of audio signals by changes in the strength of the magnetic field or changes in the amplitude of the sound W+7. Tape recorders and record disks are known that convert changes in size and store temporal changes in association with the running direction of the tape or disk.

However, in such conventional recording/playback devices with moving parts, the performance of the magnetic head, magnetic tape, needle, etc. has an adverse effect on the dynamic range and distortion rate of the signal, and the performance of the running system that drives the magnetic tape or disk has an adverse effect on the dynamic range and distortion rate of the signal. performance had a negative impact on signal frequency characteristics, wow and flutter, noise, etc. In addition, the lifespan of magnetic tapes and disks as storage media is finite, and furthermore, it is difficult to determine the exact position of the recorded signal on the storage medium. The disadvantage was that it was not easy.

Furthermore, in order to overcome the drawbacks of conventional recording and reproducing devices that use moving parts, solid state recording and reproducing devices that use solid-state storage elements as storage media have been published in patent publications and the like. All of these merely disclosed theoretical possibilities, and did not take into account the ease of use as a concrete device. For example, in conventional recording and playback devices, a stop switch that stops the operation of the recording and playback device for a long period of time and a pause switch that stops the operation temporarily are usually provided separately, making it difficult to operate the device in a hurry. At times, it was often difficult to decide which switch to operate, and no improvements in this regard had been made public regarding solid-state recording and playback devices.

[Object of the invention] The present invention has been made in response to such conventional circumstances,
To provide a solid-state recording and reproducing device that is free from wow black, level fluctuation, etc., has a stop switch that also serves as a pause function, and has good operability.

[Summary of the invention] FIG. 1 is an overall configuration diagram showing the configuration of the present invention.

In the figure, the output of an encoding means 2 for encoding an audio signal input to an input terminal 1 is stored in a first storage means 3 for storing the audio signal encoded by this encoding means 2. The encoded audio signal stored in the first storage means 3 is decoded by the decoding means 4 and outputted to the output terminal 5. The operation of reading out and reproducing the audio signal stored in the first storage means 3 is stopped by the operation of the stop means 6, and when the reproduction is stopped by the stop means 6, the operation of reading and reproducing the audio signal stored in the first storage means 3 is stopped. The address is stored in the second storage means 7. By operating the reproduction start means 8, the reproduction operation is started again from the address next to the address stored in the second storage means 7.

[Embodiment of the Invention] The details of the present invention will be described below with reference to an embodiment shown in the drawings.

2 and 3 are perspective views showing the external appearance of an embodiment of the solid-state recording and reproducing device according to the present invention, and FIG. FIG. 3 is a perspective view showing a state in which it has been shifted so that its interior can be seen.

In FIGS. 2 and 3, reference numeral 39 denotes a storage element (hereinafter referred to as a control device for storing control data) that stores encoded audio signals and is built in the main body of the solid-state recording and reproducing device and is made of, for example, RAM. The storage area of the audio data storage element 39 is divided into a plurality of partial areas, and the first address of each partial area is the control storage. It is stored in advance in the element.

Reference numeral 28 denotes an indicator light corresponding to each partial area of the audio data storage element 39 or the audio data storage element in the memory pack (described later) (hereinafter referred to as a "marker indicator light" to distinguish it from other types of indicator lights described later). ). This marker indicator light 28 lights up corresponding to a partial area read out in accordance with recording or playback to each partial area of the audio data storage element or a skip or repeat operation described later, and is turned on in response to recording or playback to the partial area. Displays playback, skip, and repeat operations.

4- Numerals 33 and 34 are indicator lights that indicate that the storage capacity of the audio data storage element 39 is nearing its end. In this embodiment, the indicator light 33 has a storage capacity of 20
In this embodiment, the indicator light 34 is turned on 10 seconds before the storage capacity is reached.

Further, in this embodiment, for example, RAM or CM
It has an insertion slot 35 for inserting a memory pack formed into a package having an audio data storage element such as O'S,
The memory pack inserted through the memory pack insertion port 35 is connected to the connection terminal 40 and electrically connected to the main body. The indicator light 29 is an indicator light that indicates that the memory pack is inserted into the main body and that recording to or reproduction from the memory pack is in progress.

Reference numerals 21 to 27 indicate switches for performing various operations of the solid-state recording and reproducing device 20, and reference numeral 21 indicates a recording operation to the audio data storage element 39 in the main body, and a recording operation by inserting the memory pack into the main body. The audio data storage element 3 of
This is a recording/copy switch for performing a recording operation on the memory pack following the recording operation on the audio data storage element 39, or when transferring audio data stored in the audio data storage element 39 to the memory pack and performing a copy operation. , this recording/
When the copy switch 21 is operated, the indicator light 30 lights up.

Reference numeral 22 is a playback switch for playing back the recording signal recorded in the audio data storage element 39, and when the playback switch 22 is operated, the indicator light 31 lights up.

Reference numeral 23 is a cue switch for cueing operation, and when this cue switch 23 is operated, the partial area being played back in the audio data storage element 39 is skipped and the recorded audio signal is transferred to the next partial area. Reproduce.

Reference numeral 24 is a skip switch corresponding to fast forwarding in a conventional tape recorder. When this skip switch is operated, the marker indicator light 28 blinks sequentially, for example, every 0.1 seconds, and each of the audio data storage elements 39 is The first addresses of the partial areas are read one after another. Then, with this skip switch 24 turned OFF, recording or reproduction is possible from the first address of the partial area next to the current partial area.

Reference numeral 25 is a repeat switch corresponding to the rewind switch of a conventional tape recorder, and by operating this repeat switch 25, the skip switch 24 is activated.
In the opposite direction, that is, when the audio data storage element 39 or the memory pack is connected, the marker indicator light 28 changes from the last address of the audio data storage element in the memory pack, for example, every 0.4 seconds. , and the partial areas of the audio data storage element 39 or the audio data storage element in the memory pack are sequentially read out from the rear address. When this repeat switch 25 is turned OFF, scanning of the partial area of the audio data storage element 39 or the audio data storage element in the memory pack is completed, and the next part of the area at the time of stop is scanned. Recording or playback is possible from this area.

Reference numeral 26 is a stop switch that instructs to stop each operation, and when this switch is operated, the indicator light 32 lights up.

Reference numeral 27 is a power switch of the solid-state recording and reproducing device 20. Also, numeral 36 is a built-in microphone, and numeral 37 is a built-in microphone.
is a headphone jack, and 41 is a built-in speaker.

The functions of the respective switches in the embodiment shown in FIGS. 2 and 3 will be briefly described below.

(1) Recording mode This mode represents the case where recording is performed sequentially from the first address of the audio data storage element. In this case, by externally attaching the memory pack, it becomes possible to expand the storage capacity of the storage element within the main body.

Further, the marker indicator lights 28 are lit sequentially from number 0 in proportion to the recording time to indicate recording.

(2) Skip/record mode This mode represents the case where an arbitrary 8-minute area of the audio data storage element is selected and recording is performed from the first address of this partial area. In this case as well, by using a memory pack, it is possible to expand the storage capacity of the audio data storage element within the main body. It is also possible to skip a partial area of the audio data storage element of the memory pack.

The marker indicator lights 28 light up one by one in a short time starting from number 0, stop at the skip OFF position, and when recording starts from this position, recording to the relevant partial area ends as in the recording mode described above, and the next The marker indicator lamps 28 are lit one by one each time the partial area is moved.

(3) Repeat/record mode This mode is similar to the skip/record mode, but the recording position is selected from the end address of the audio data storage element. The fact that the storage capacity can be expanded using a memory pack is the same as in the recording mode and skip/record mode.Furthermore, it is also possible to repeat a partial area of the audio data storage element in the memory pack. It is.

The marker indicator lights 28 are lit up one by one at high speed, starting from the marker indicator lights 28 with the larger number and moving towards the smaller number, as an indicator of the desired location. When recording is started by turning off the repeat operation, the operation of the marker indicator light 28 is the same as in the recording mode.

(4) Reproduction mode This mode represents the case where the audio data is reproduced sequentially from the first address of the storage element. The ability to expand the playback capacity using a memory pack corresponds to the recording mode.

The marker indicator lights 28 are sequentially lit starting from number 0 in proportion to the playback time, as in the recording mode.

(5) Skip/Reproduction Mode This mode represents the case where reproduction is performed from the beginning address of an arbitrary partial area of the audio data storage element. In this case as well, by attaching a memory pack externally, it is possible to expand the storage capacity of the audio data storage element. Skip mode is also possible within the memory pack.

The marker indicator lights 28 are sequentially lit one by one starting from number 0 in a short period of time, similarly to the skip recording mode described above. When the skip is stopped and the playback is performed, similarly to the playback mode described above, the partial areas of the audio data storage element are sequentially illuminated in proportion to the playback time.

(6) Repeat/playback mode This mode is similar to the skip/playback mode, except that the playback position is set from an address toward the end of the audio data storage element. By using a memory pack, it is possible to expand the playback capacity corresponding to the recording mode, and repeat operations within the memory pack are also possible.

Marker display * The operation of T28 is the same as the above-mentioned repeat recording, by sequentially lighting up the indicator lights in a short time and repeating switch 2.
5 OFF, the solid-state recording and reproducing device or the reproducing operation is started by operating the reproducing switch 22, and the operation of the marker indicator lamp 28 at this time is the same as the operation during reproducing.

(7) Cue/Reproduction Mode This mode is a mode in which the audio data recorded in the partial area next to the partial area currently being played back is read out by operating the cue switch 23. Even in this mode, the use of a memory pack makes it possible to locate the beginning of audio data whose capacity has been expanded.

The operation of the marker indicator light 28 is the same as in the reproduction mode described above.

(8)] Bee Mode This mode represents the case where audio data recorded in the audio data storage element within the main body is copied to an external memory pack.

Recording is performed in the memory pack sequentially from the beginning of the audio data storage element of the memory pack. The operation of the marker indicator light 28 is the same as in the recording mode.

Next, a specific circuit configuration for realizing the various operation modes described above will be explained.

FIG. 4 is a block diagram showing the circuit configuration of an embodiment of the present invention.

FIG. 5 is a circuit diagram showing a specific configuration example of the voice detection circuit 61 in the block diagram of FIG. 4, and FIG. 6 is a waveform diagram showing an example of waveforms of each part of the circuit of FIG.

12- In Figures 4 to M6, the reference numeral 51 indicates the main body of the solid-state recording and reproducing device U20 of the Mokumitsuki example, and the reference numeral 52
indicates a memory pack. The main body 51 and the memory pack 52 are electrically connected via connectors 54 and 55. In addition, the input/output terminal is marked EH on the plug 53 of the main body 51,
A microphone 56, a speaker 57, etc. can be connected and electrically connected to the circuit inside the main body.

Reference numerals 58 and 59 are amplifiers, which amplify the input signal from the input terminal and output the signal to the speaker 57 via the output terminal.
jt! of the reproduction signal that drives etc. Perform 1 width. The amplifiers 58 and 59 form a pair to form an analog amplifier 60. For example, the input signal, which is the output signal of the microphone 56, is amplified by the amplifier 58 via the plug 53, and then passed through a low-pass filter (hereinafter abbreviated as "LPF").
62 and the voice detection circuit 61.

This audio detection circuit 61 interrupts the recording operation to the audio data storage element 81.103 when the level of the input signal is below a preset level during recording, and prevents the audio data storage element 81. This is a circuit for preventing wastage of the 103 and for quickly listening to necessary signals during reproduction.

Details of this circuit will be described later in FIG.

The output signal of this audio detection circuit 61 is transmitted to a peripheral input/output controller (hereinafter referred to as "P").
The output signal of the LPF 62 is input to the delta modulation circuit 63, and becomes one of the control signals of the central control circuit (hereinafter abbreviated as "c p u") 79. The output signal encoded by the delta modulation circuit 63 is converted into parallel signals of 8 bits each by the serial/parallel conversion circuit 64.

The output signal of this serial/parallel conversion circuit 64 is inputted to an input/output switching circuit 65 and then sent to an address/data/control bus 75.
is output to. The signal from the address/data control bus 75 is input to the parallel/serial conversion circuit 67 via the input/output switching circuit 65, where it is converted bit by bit into a temporally continuous bit-serial output signal. , are input to the delta demodulation circuit 68.

The output signal of this delta demodulation circuit 68 is terminated at a variable resistor 70 via an LPF 69, and at the same time is input to a slope detector (hereinafter abbreviated as "SD") 72 that detects the slope of this output signal. .

The output signal of this 5D72 is a voltage controlled oscillator circuit (hereinafter referred to as “
(abbreviated as “vco”) 73, VCO 7
3 outputs a pulse signal with a period proportional to the slope of the demodulated signal, and this pulse signal and a signal obtained by dividing this pulse signal by 8 by the frequency dividing circuit 74 are sent to the address/data control bus 75 and the delta modulation circuit 63. , delta demodulation circuit 68, serial/parallel conversion circuit 64, parallel/serial conversion circuit 6
7. It is supplied to the input/output switching circuit 65, etc., and is used as a control pulse signal.

The demodulated output via the variable resistor 70 is input to a muting circuit 71, the voltage level of which is attenuated as required, and output to the speaker 57 via an amplifier 59 and a plug 53.

Reference numeral 81 denotes a storage element for audio data, which is composed of 12 RAMs each having, for example, 15 to 256 bits. The entire storage area of this audio data storage element 81 is divided into a plurality of partial areas, and from now on, the address data of the starting address of each partial area and the chip number of the storage element in which the partial area exists are combined into a pair of data. This will be referred to as "address pointer data." Also, the voice data storage element 81 is equipped with a backup battery 82 for emergency use.
This prevents internal audio data from being volatile even if the power is cut off. Further, the audio data storage element 81 is connected to an address/data/control bus 75, and exchanges signals with the CPU 79, input/output switching circuit 65, and the like.

Reference numeral 83 is a control storage element for controlling addresses for writing and reading audio data to and from the audio data storage element 81.

In this control memory element 83, an RA is used to record address pointer data of the audio data memory element 81 at the time of starting recording.
12 M, address 16 at the end of recording, RΔM 85 to store pointer data, RAM 86 to store address pointer data at the end of playback,
A save RAM 87 and a ROM 88 for storing address pointer data of the starting address of each partial area of the audio data storage element 81 set in advance are provided. The input/output terminals of each of the RAMs ■ to ■84 to 87 and ROM8B are the address/data/control bus 75, the PIO
76 and is connected to CPtJ 79 via an address, data, and control bus 78. Note that the RAMs (1) to (4) 84 to 87 of the control memory element 83 are connected to the backup battery 82 to prevent stored data from volatilizing in an emergency.

The PI076 has a register, and exchanges signals with the CPtJ79 through an address/data/control bus 78 and an interrupt signal line 77, and also operates the recording copy switch 21, playback switch 22, and playback switch 22 shown in FIGS. 2 and 3. The output signal from the operation button 80 such as the cue switch 23 is accepted.

Furthermore, when the memory pack 52 is connected to the main body 51 via the connectors 54 and 55, the signal line 95 is electrically connected to the signal line 96 that is grounded within the memory pack 52, and the memory pack 52 is connected. This is a signal line for generating various command signals associated with this, and for lighting the indicator light 29 to indicate that recording or playback operation to the memory pack 52 shown in FIGS. 2 and 3 is in progress. The address/data/control bus 75 includes, via a drive circuit 89, a marker indicator light 28 that displays each partial area of the audio data storage element 81, an indicator light 29 that indicates that the memory pack 52 is connected, and the like. The CPU 79 sends necessary drive signals.

Similarly, the conversion signal bypass circuit 75 is a comparison circuit (hereinafter referred to as "
COM") 91 and the output signal from this C0M91, the audio inside the main body 51 is transmitted through a multivibrator 92 triggered by the output signal and a drive circuit 93 that changes the output signal of this multivibrator 92 into an appropriate drive signal. A remaining capacity indicator light 94 (corresponding to indicator lights 33 and 34 in FIGS. 2 and 3) displays the remaining capacity of the data storage element 81 and the audio data storage element 10j in the memory pack 52. ), and this remaining amount indicator light 94 is driven by a control signal from the CPU 79.

The address/data/control bus 75 is connected to the connector 54
．． 55 to the address/data/control bus 101 in the memory pack 52, and transmits each fli control signal to the audio data storage element 1 in the memory pack 52.
03 and the control memory element 97.

Inside the control storage element 97, there is a RAM 98 for storing address pointer data at the time of starting recording to the audio data storage element 103 in the memory pack 52, and
RAM 99 and memory pack 5219 for storing address pointer data at the end of recording to the audio data storage element 103 in the audio data storage element 103 in the audio data storage element 103 at the end of the playback operation. 103 and a RAM 100 for storing address pointer data.

Note that each RA of the control storage element 97 in the memory pack 52
M■~■98~100 and audio data storage element 10
A backup battery 102 is connected to the RAM in the main body 51 in the same way as each RAM in the main body 51, to prevent stored data from volatilizing when the power is turned off.

By connecting the memory pack 52 described above to the main body 51 via the connectors 54 and 55, the audio data storage element 103 in the memory pack 52 is connected to the audio data storage element 81 in the main body in a so-called cascade connection. It will be done.

Next, a circuit example of the audio detection circuit 61 in the circuit diagram of FIG.
This will be explained using the circuit diagram shown in the figure.

The output signal of amplifier 58 in FIG. 4 is input to input terminal 1 in FIG.
12 to one input terminal of the C0M111. A variable resistor 114 is grounded to the other input terminal 20- of this COMI 11 at a terminal 113 to which a positive voltage is loaded, and the sliding point of this variable resistor 114 is connected via a capacitor 115. .

A reference input voltage is set in advance by the variable resistor 114 and capacitor 115. The output of the C0M111 is connected to the input terminal of the monostable multivibrator 116, and the output terminal j of this monostable multivibrator 116
19 is connected to the PI076 shown in FIG. 4 above. Also, monostable mal.

A capacitor 117 and a resistor 118 are externally connected to the monostable multivibrator 116 for adjusting the time of the logic level "I II" of the multivibrator 116.

FIG. 6 is a waveform diagram showing the operation of the sound detection circuit shown in FIG. This will be explained using the waveform diagram in FIG.

When an audio signal as shown in FIG. 6(a) is input to the input terminal 112, the variable resistor 11/11 capacitor 11
When the level of the audio signal is higher than the reference voltage level (S in FIG. 6) set in step 5, the output of C0M111 becomes logic level "'1". Therefore, the output waveform of C0M111 is as shown in FIG. As shown in (b), the logical level "
1'', and when the level is low, a pulse waveform at logic level ``0'' is output.

The monostable multi-bi break 116 is triggered by the pulse waveform shown in FIG. 6(b), and the time (
During T) in FIG. 6(c), even if the trigger pulse of the C0M111 reaches the logic level 110 II, the output level of the monostable multivibrator 116 continues to be at the logic level "1". As shown in Figure 6 (C), during the first three pulses in Figure 6 (B) where trigger pulses are frequently issued, the monostable multivibrator 11
The output of 6 continues to be at logic level ``1'' and the next (
After the fourth pulse (b) falls, the level of the audio input signal applied to the input terminal 112 is lower than the reference setting voltage level S for the time set by the capacitor 117 and resistor 118. In order to continue, the output level of the monostable multivibrator 116 falls to the logic level 'O' and remains at the logic level '0' until the next trigger pulse is input.

In this way, the output signal of the monostable multivibrator 116 of this audio detection circuit becomes the 110 I+ level when the audio input signal is lower than the reference voltage level for a certain period of time, so this "O" level is used for recording. By not generating the interrupt signal, it is possible to stop recording while the level of the audio input signal is lower than the reference level, and to prevent the audio data storage element 81.103 from being wasted.

Furthermore, since it is possible to use the output signal of this monostable multivibrator 116 itself as an interrupt signal 23-, it is also possible to obtain an automatic recording start function using this voice detection circuit.

Next, the operation of the embodiment shown in FIG. 4 will be explained using the flowcharts shown in FIGS. 7 to 12. In addition, Fig. 7 shows C
8 is a flowchart showing the interrupt operation of the PU 79, FIG. 8 is a skip and repeat operation, FIG. 9 is a recording operation, FIG. 10 is a playback operation, and FIG. 11 is a flowchart showing a recording/playback operation when a memory pack is inserted.

First, by turning on the power switch 27 (the eighth
Step (22) in the figure>, the CPU 79 initializes each part according to the program written in the ROM 88 of the control storage element 83 (step (23)). That is, the PI076 for accepting interrupts, and the RAM for temporarily recording address pointer data of the audio data storage element 81.
(2) Initialize the data in 84 to 86, the audio data storage element 81, the serial/parallel conversion circuit 64, etc. After the initialization is completed, the solid-state recording and playback device 20 enters the stop mode (step (
24)”), recording switch 21, playback switch 24- switch 22, skip switch 24, repeat switch 2
5. Interrupts caused by the operation of switches such as the stop switch 26 and interrupts caused by a 1-byte signal obtained by dividing the output clock signal of the VCO 73 by 8 by the frequency dividing circuit 74 are provided.

The flowchart of FIG. 8 shows the flow when a skip operation or a repeat operation is performed, but for convenience of explanation, the recording operation will be explained first using the flowchart of FIG. 9.

(1) Recording Operation When the recording switch 21 is turned on for recording (step (47) in FIG. 9), the interrupt register reads the interrupt information and issues an interrupt to the CPU 79. CPU7
9 executes the interrupt according to the interrupt operation flowchart of FIG. 7, and determines which operation command it is.

That is, in the flowchart of FIG.
After being initialized, the PI 79 reads the data in the interrupt register of the PI 076 and waits for an interrupt (step (1)).

Next, step (2)) to determine whether there is a memory pack.
If there is a memory pack, the operation that accompanies the connection of the memory pack, for example, when the storage speed of the audio data storage element 81 in the main body is completed and the end marker appears, the operation of the memory pack 52 is performed. Audio data storage element 103
The memory pack 52 of RAM ■~■84~86 in the storage element 83 for control and the switching of the storage element to
A series of operations such as switching to the RAMs 1 to 98 to 100 in the memory pack 52 and lighting the indicator light 29 indicating that the memory pack 52 has been inserted are performed (step (3)).

Next, in step (4)) to determine the presence or absence of a 1-byte interrupt signal, a 1-byte interrupt signal generated by the operation of the recording switch 21 or the playback switch 22 is detected,
Perform the necessary operations for each. For example, when recording, the CPU 79 converts audio data into 8-bit parallel data using a 1-byte signal in the serial/parallel conversion circuit 64.
The audio data is sent via the head address data control path 75 (step (11)), and the audio data is recorded from the CPU 79 to the audio data storage element 81 (step (12)).

After that, the address data of the audio data recording element 81 is incremented [, and the recording operation is continued (step (15)), but the recording operation is stopped due to the appearance of the end marker or the operation of the stop switch 26. That is, operations such as clearing the address counter, stopping interrupts of 1-byte signals, and writing address pointer data to the RAM 85 at the end of recording are performed (step (16)).
).

Also, once again, the CP is stored in the audio data storage element 81.
The U79 heavy parallel audio data is read (step (13)), and then the audio data is transferred from the CPU 79 to the parallel-to-serial conversion circuit 67 (step (14)) to reproduce the audio signal.

Thereafter, in order to read the next audio data, the address data of the audio data storage element 81 is incremented (step (15)), and at the end of playback, the same stop processing as at the end of recording is performed (step (16)). )).

In addition, if such a 1-byte signal for recording and playback is not generated, it is determined whether there is a repeat signal (step (5)), and if there is a repeat signal, the control memory corresponding to the repeat operation is A series of processes such as counting down the ROM 88 in the element 83 and sequentially lighting up the marker indicator lamps 28 in the opposite direction are performed (step (17)). Thereafter, the process proceeds to determination of playback after repeat (step (7)), recording (step (8)), etc.

If it is not a repeat operation, it is determined whether or not it is a skip operation (step (6)), and if it is a skip operation, the address pointer data of the ROM 88 in the control storage element 83, for example, associated with the skip operation is Steps of performing processes such as addition and sequential lighting of marker indicator lights 28 indicating partial areas in the audio data storage element 81 (
18)), then proceed to a discrimination operation such as playback (step (7)) or recording (step (8)).

Next, if it is not a skip operation, or if the processing necessary for a repeat operation or a skip operation has been completed, it is determined whether or not it is a playback operation (step (
7)). If it is a playback operation, 1 necessary for the playback operation.
Byte signal interrupt acceptance and VCO73 operation start,
An operation such as canceling the muting state of the muting circuit 71 is performed (step (19)), and the next copy operation is stopped (step (9)) and then the operation is stopped (step (10)).
Proceed to the next judgment.

Next, it is determined whether the recording operation is to be performed (step (8)
). In the case of a recording operation, operations such as accepting an interrupt of a 1-byte signal necessary for the recording operation, starting the operation of the VCO 73, and activating the muting operation of the muting circuit 71 are performed (step (20)). The process proceeds to a determination as to whether or not it is the next copy operation (step (9)).

After performing the above-mentioned recording or reproduction, or after performing the accompanying processing necessary for recording or reproduction, it is determined whether the operation is a copy operation to a memory pack (step (9)). If it is a copy operation, the operation necessary to transfer the audio data from the audio data storage element 81 in the main body to the audio data storage element 103 in the memory pack 52 is performed (step (21)); After the transfer operation is completed, the process moves to a determination as to whether or not it is the next stop operation (step (10)).

The presence or absence of the above 1-byte signal (step (4)), the presence or absence of repeat operation (step (5)), and the presence or absence of skip operation (
Step (6)), Playback operation step (7)
), whether it is a recording operation (step (8)), and whether it is a copy operation (step (9)),
Finally, it is determined whether or not it is a stop operation (step (1)
0)), in the case of this stopping operation, the processing necessary for the above-mentioned stopping is performed (step (16)). If it is not a stop operation, the interrupt register is read after reinitialization and step (1)) is performed to prepare for the next operation.

The CPU 79 performs the above-described judgment operation, but when the recording switch 21 is turned on, the CPU 79
9 is interrupted by a 1-byte signal, so the 12th
The process moves to a loop with the 1-byte signal in step (4) in the figure, and the CPU starts controlling the recording operation.

Returning to the flowchart of FIG. 9, details of this recording operation within the CPU 79 will be explained.

When the recording operation is determined in step (47), the marker indicator lamp 28 corresponding to the address pointer data written in the RAM 84 in the control memory 83 lights up (step (48)).

This is the recording element 8 for audio data that starts this recording operation.
This shows the divided area immediately before the divided area No. 1.

Next, it is determined whether or not there is data in RΔM 85 in the control memory element 83 (step (49)). This judgment is made to determine whether or not a recording operation has been performed before starting this recording operation, and the address pointer data at the end of the previous recording has been recorded in the RAM 85.

If the address pointer data 31- at the end of the previous recording is recorded in the RAM 85, a step (50
)), proceed to the next step (51).

If there is no data in the RAM 85, the process also proceeds to step (51), and it is determined whether address pointer data is held in the ROM 88 (step (51)). If address pointer data is held in the ROM 88, the address pointer data held in the ROM 88 is preset in the address counter in the CPU 79 (step (53)). If no address pointer data is held in the ROM 88, the CPU 79 presets the address pointer data next to the last address pointer data at the end of the previous recording read in step (50).

That is, if a skip operation or a repeat operation, which will be described later, is performed as a result of this series of operations, recording is performed from the beginning address of the partial area next to the partial area selected by the skip or repeat operation, and the skip operation or repeat operation is performed. If the repeat operation is not performed 4r, even if there is still a recording address in the divided area in the audio data storage element 81 at the end of the previous recording, the next recording operation will always be performed in the next divided area. This allows recording to start from the first address of the area.

After specifying the recording address in the audio data storage element 81 in this state, the CPU 79 closes the converted signal bypass circuit 66 of the delta modulation circuit 63 and the delta demodulation circuit 68 (step (54)) to prevent howling. Therefore, the muting circuit 71 is turned on (step (55)).

Also, the operation of the variable clock VCO 73 is started (step (56)), and at the same time, the input/output switching circuit 65
is switched to the modulation side (step (57)).

Now that the preparation system for recording has been completed, in this state, when an audio signal is applied from the microphone 56 to the solid-state recording and reproducing device, this audio signal is amplified by the amplifier 58 via the tangent line 53. is applied to the LPF 62. LP
After being band-limited to a required frequency band by F62, this audio signal is applied to a delta modulation circuit 63 and encoded into a digital signal.

A part of the audio signal encoded in this way is immediately passed through the conversion signal bypass circuit 66 to the delta demodulation circuit 6.
8 (step (58)), and is demodulated by LPF 6 again (step (58)).
After the band is limited by 9, the slope value of the voltage waveform is detected by 5072 (step (59)), and depending on the magnitude of this slope value, the VCO 73
The firing frequency of is changed (step (60)).

The oscillation pulse of this VCO 73 is used as a clock pulse in the delta modulation circuit 63 and delta demodulation circuit 68 described above.

That is, this delta modulation and demodulation coarsens the clock frequency according to the slope of the waveform to be modulated and demodulated. This is because when modulation and demodulation is performed using clock pulses of a uniform frequency, the modulation and demodulation accuracy decreases where the slope of the waveform to be modulated and demodulated is steep, and on the other hand, it has extra accuracy where the slope is gentle. This is done to maintain sufficient accuracy by increasing the clock frequency where the slope is steep, and to lower the clock pulse frequency where the slope is gentle to avoid unnecessary accuracy. By performing delta modulation and demodulation using a clock pulse frequency proportional to the slope value of the waveform to be modulated and demodulated in this manner, delta modulation and demodulation can be performed with sufficient accuracy depending on the aspect of the waveform to be modulated and demodulated.

The oscillation output of the VCO 73 is supplied to the above-mentioned delta modulation circuit 63 and delta demodulation circuit 68, and is also supplied to the frequency division circuit 74.
After being frequency-divided by 8 and converted into a 1-byte signal (step (61)), it is supplied to the CPU 79 etc. via the serial/parallel conversion circuit 64, parallel/serial conversion circuit 67, and address/data/control bus 75, and the audio signal is converted into a 1-byte signal. When writing or reading signal data to the audio data storage element 81, etc., use a mink pulse. In this state, the CPU 79 accepts the aforementioned 1-byte signal interrupt (step (4),
(62)).

Next, the value of the address counter of the CPU 79 and the value of the ROM 88
It is determined whether the data match (step (63)). CPU79 address counter value and RO
If the data in M88 do not match, the value of the address counter of the CPU 79 is incremented by one address, and the address data in the audio data memory 81 is changed (step (64)). This operation is repeated until the address counter of the CPU 79 and the data of the ROM 88 match (steps (63) and (64)).

That is, since address pointer data indicating the starting address of each partial area of the audio data storage element 81 is recorded in the ROM 88, when starting recording, each part of the audio data storage element 81 must be Recording is started from the first address of the partial area.

When the leading address of each of the 36 partial areas in the audio data storage element 81 is read out in this manner, an address pointer data number is set corresponding to this partial area (step (65)). At the same time, the set address pointer data is written into the RAM 84 (step (66)).

That is, address pointer data at the time of starting recording is recorded in the RAM 84.

At the same time, the marker indicator light 28 corresponding to this address pointer data lights up (step (67)). In this state, the address counter of the ROM 88 is incremented in preparation for the next recording operation.

(Step (68)).

When the recording address in the audio data storage element 81 is determined in this way, the bit-serial digital signal that is the output signal of the delta modulation circuit 63 is transferred to the serial-parallel conversion circuit 63.
4, it is converted into parallel data of 8 bits each (bit parallel data) (step (69)), and is stored in the audio data storage element 81 or, if the memory pack 52 is used, the audio data storage element 103 in the memory pack 52.
Then, the audio signal is stored in the form of bit parallel data (step 70).

Next, when writing of 8-bit bit-parallel audio data using a 1-byte signal is completed, the address counter of the CPU 79 is incremented, and the audio data storage element 8 is incremented.
Preparation is made for writing a bit parallel signal to the next address within 1 (step (71)).

In this state, it is determined whether there is an end marker indicating that the storage capacity in the audio data storage element 81 has been exhausted (step (74)), and if the end marker does not appear, it is determined whether or not the stop switch has been operated. (Step (75
)). If the end marker does not appear and the stop switch is not operated (step (75)), the process returns to step (65) and continues the recording operation after confirming the address of the address pointer data.

In this case, if the address pointer data number set in the previous recording operation and the address pointer data number for the next recording are the same, the RAM in step (66)
(2) Address pointer data is not transferred to or from the 84.

Then, when recording is to be continued into the next divided area of the audio data storage element 81, step (65
) is incremented, and this incremented address pointer data is written to RAM 84 in step (66).

In this way, audio data is sequentially recorded into the audio data storage element 81 or the audio data storage element 103.

Next, when the memory capacity of the audio data storage element 81 is filled and an end marker appears (step (74)), this end marker is written to the RAM 84 (step (78)).
), the 1-byte signal interrupt is stopped (step (7)
9)), it is determined whether there is a memory pack (step (80)).

If there is a memory pack, recording into the memory pack is performed according to the flowchart of the recording operation to the memory pack shown in FIG. 10, which will be described later. If there is no memory pack, the recording operation must be ended now, so the address counter is cleared (step (81)), and the solid-state recording/playback device enters stop mode and stops its operation (step < 82)).

If you want to stop the storage before the end marker appears, that is, while there is still some storage capacity left in the audio data storage element 81, operate the stop switch 26 (step (75)) to interrupt the 1-byte signal. is stopped (step (76)), and address pointer data at this time is written into RAM 85 (step (77)). That is, the address pointer data at the end of recording is written into the RAM 85. Thereafter, the address counter is cleared (step (81)) and the stop mode is entered (step (82)), as in the case without the memory pack described above.

Note that the recording time of the partial area is approximately 10 seconds in this embodiment, and the marker indicator lights 28 are sequentially turned on every 10 seconds to display the recorded area.

40- That is, the CPU 79 counts the 1 by 1 signals, and when the preset number of 1 byte signals generated in 10 seconds is reached, the marker indicator lamps 28 are turned on one by one. The marker indicator light 28 is converted into a decimal number and driven by a drive circuit 89 connected to the address/data/control bus 75.

(2) Skip recording operation If the user desires to record from an arbitrary Nth partial area, by turning on the stop switch 24,
PU79 accepts the interrupt (steps (6), (25)
)), determines the operation mode and moves to skip operation (
Step (18)).

In this case, the CPU 79 sequentially reads data for comparison with the number of 1-byte signals generated within a preset time (10 seconds in this embodiment) from the ROM 88 of the control storage element 83 (step (26)). Based on this data, only one corresponding marker indicator light 28 is sequentially blinked (step (27)).

In this case, the blinking speed of the marker indicator light 28 is approximately 0.0 in this embodiment in order to ensure accurate operation by the user. It is arranged to blink at a rate of 1 per /I seconds.

When the marker indicator light 28 lights up to the point where the user desires to record, step (28) is performed to stop the skip operation.
)), the incrementing operation of the address counter of the ROM 88 is stopped and the read data is held in this state (
Step (29)').

To record in this state, perform the recording operation described above and set the recording switch 21 to 0NL (step (47)).
Hereinafter, the recording operation will be performed according to the flowchart shown in FIG.

In this case as well, it is determined in step (51) whether address pointer data is held in the ROM 88, and if address pointer data is held,
In other words, when a group area of the audio data storage element 810 is selected for performing the skip operation and starting the recording operation, the address pointer data of the ROM 88 is preset in the address counter of the CPU 79 (step (53)).
Since recording is started from this address, recording is performed from the leading address of the partial area of the audio data storage element 81 selected by performing the skip operation. The subsequent recording operation is the same as in normal recording mode.

(3) Repeat recording operation In this case, if the user wants to record the audio signal from the end of the divided area of the audio data storage element 81 first, the partial area can be changed to an address by operating the repeat switch 25 for convenience. This function has a function of quickly selecting the position of a desired partial area by reading out from the larger one at high speed.

That is, by turning on the repeat switch 25 (steps (5), (34)), the CPU 79 starts repeat processing (step (17)). In this case, if a memory pack 52 is connected, in order to start the repeat operation from that memory pack 52, it is first determined whether there is a memory pack 52 (step (35)).
, if there is a memory pack 52, the memory pack indicator light 29 lights up (step (40)), and the control memory element 83 in the main body 51 is switched to the control memory element 97 in the memory pack 52 (step (4, 1)), 43- Sequentially read address pointer data from the ROM 88 in the control storage element 83 (step (42)). However, in this case, the address pointer data is counted backwards from the largest to the smallest and read out sequentially.

Next, in response to reading of the address pointer data in the ROM 88, the marker indicator lights 28 blink sequentially from the larger number to the smaller number. The read speed in this case is the same as the read speed in the case of the skip operation (step (43)).

In this way, the partial areas of the audio data storage element 103 in the memory pack 52 are sequentially read out, and whether or not the reading in the memory pack 52 is completed is determined based on the presence or absence of the end marker.Step (44)) If reading from the pack 52 is not completed, the same operation is repeated until reading from the memory pack 52 is completed.

When the end marker is detected and it is determined that the reading of the memory pack 52 is completed (step (44)), the controller 4/l- of the memory pack 52 controls the combined storage element 97 within the main body 51. 83 (step (45)). Simultaneously with this switching operation, the memory pack indicator light 29 goes out (step (46)
)).

Subsequently, the ROM 88 of the control memory element 83 in the main body 51
The address pointer data is sequentially read from the address pointer data from the largest number (step (36)), and in accordance with this reading operation, the marker indicator lamps 28 blink sequentially from the largest number (step (37)).

If the repeat operation is continued in this way, the above operation is repeated and the repeat switch 25 is turned OFF.
If it has been F (step (38)), at this point R
The decrement of the address pointer data of the OM88 is stopped and the read address pointer data is held (step (39)).The recording operation from this stage onwards is the same as in the case of skip recording, and is performed according to the flowchart in FIG. It is done.

(4) Repeating recording and stopping operations In this case,
This is a case where each of the above-mentioned recording operations is performed multiple times within the capacity of the data storage element.

That is, when recording a plurality of pieces of information after a certain period of time has elapsed or selecting and recording a plurality of divided areas, this is done through a stop operation, but if the recording operation is performed again after the stop operation, the CPU 79 Stop operation (step (
10) and (75)), step (76)) to stop the 1-byte signal interrupt, and step (77) to record the address pointer data at this time in RAM 85.
)), clear the address counter step (81)
), enters stop mode (steps (16), (82
)). Then, by operating the recording switch 21 again (steps (8), (47)), a marker indicator light corresponding to the address pointer data written in the RAM 84 and indicating the starting address of the partial area at the time when recording was started last time. 28 is turned on (step (48)), and the divided area of the audio data storage element 81 in which audio data has already been recorded is displayed.

Then, write the address pointer data at the end of the previous recording to R.
Step (49)) to read from ΔM■85, step (50)) to increment this data, and send this incremented address pointer data to the CPU 7.
Step (52) to preset the address counter of 9.
)), the address counter continues to be incremented (step (63 ), (6/l)), Even if there is sufficient capacity in the partial area at the end of the previous recording, recording will start from the next partial area at the end of this recording.In addition, recording will be performed again in the already recorded partial area. If so, the previously recorded audio data is updated and the newly recorded audio data is stored.

(5) Reproduction operation When the re-F switch 22 is turned on for reproduction (steps (7), (83)), the PI○76 reads the interrupt information and outputs the CP via the interrupt signal line 77.
Interrupt U79.

When this interrupt signal is generated, the CPU 79 determines whether or not there is held data in the RAM 86 of the control storage element 83 (step (84)). If there is held data in the RAM 86, this held data is read out and incremented by 1 byte (step (85)).

In other words, the fact that there is retained data in the RAM 86 indicates that a previous playback operation was performed, and this R
Since the data held in the AM 86 is the address pointer data at the end of the previous playback, by incrementing the data by 1 byte, the data stored in the audio data storage element 8 is
This is because the reproduction operation is performed from the address following the previous reproduction operation of 1.

Next, if there is no held data in the RAM 86, or if there is held data, this held data is incremented by 1 byte, and then it is determined whether or not there is held data in the ROM 88 (step 718-(86)). This determination is whether a skip operation or a repeat operation has been performed.

If there is data held in the ROM 88, a skip or repeat operation has been performed, so this data is transferred to the CP.
The address counter of U79 is preset and playback is prepared from the partial area of the audio data storage element 81 selected by a skip operation or a repeat operation (step (
88)). If there is no retained data, the skip operation or repeat operation has not been performed, so the CPU 79 is preset with the data of step (85), which is incremented by 1 byte from the address pointer data at the end of the previous playback operation, and the data is continued from the previous playback operation. Prepare to play (
step (87)). In this state, the marker indicator lamp 28 is temporarily turned off (step (89)) in preparation for displaying the partial area during the subsequent reproduction operation.

Next, the CPU 79 opens the converted signal bypass circuit 66 of the delta modulation/demodulation section (step (90)) and turns off the muting circuit 71 for howling prevention (step (91)). In addition, variable clock VC
In order to start the operation of O73 (step (92)), since no control voltage is generated at the frequency control input terminal of this VCO 73 at the time of starting reproduction, this VCO 73 starts oscillating at its free running frequency (step (93)). )').

At the same time, the input/output switching circuit 65 is switched to the demodulation side (step (94)).

Next, the output pulse of the VCO 73 is frequency-divided by 8 by the frequency dividing circuit 74 to generate a 1-byte signal (step (95)
)). When a 1-byte signal is generated in this way, CPLJ
79 accepts the interrupt by this 1-byte signal (step (96)), and determines whether the address counter of CPIJ 79 and the data in RAM 84 are the same value (step (97)). and CPtJ7
If the address data of 9 and the address pointer data of RAM 84 do not match, the address counter of the CPU 79 is incremented (step (98)) and continues to be incremented until they match (step (97)).
, (9B)).

That is, by this operation, the partial area of the recorded audio data storage element 81 at the start of recording is read out.

In this way, when the address counter data of the CPU 79 and the address pointer data of the RΔM 84 match,
The matched value is set in the address counter of the audio data storage element 81 of the CPLJ 79 (step (99)).
). At the same time, the marker indicator light 28 of the partial area corresponding to this number is turned on (step (100)), and the address pointer data of the ROM 88 is subsequently incremented in preparation for the next reading (step (101)). The step of reading data from the partial area of the audio data storage element 81 where data is recorded (
Step (102)), the read bit-parallel audio data based on the 1-byte signal is converted into a temporally continuous bit-serial pulse signal 51- by the parallel-to-serial conversion circuit 67 via the input/output switching circuit 65 (step (103)). )). After that, delta demodulation is performed in the delta demodulation circuit 68 (step (104)).
. The demodulated signal demodulated by this delta demodulation circuit 68 is L
After passing through PF69 and adjusting the abutment with variable resistor 70,
The signal is amplified by the amplifier 59 via the muting circuit 71, outputted as an audio output signal, and reproduced by the speaker 57 (step (10'5)).

On the other hand, a part of the output signal of the LPF69 is 5D72,
The slope of the amplitude is detected, and an output voltage is generated depending on the magnitude of this slope. Then, the frequency of the output clock pulse of the VCO 73 is controlled by the VCO 73 according to the magnitude of the output voltage of the 5D 72 (step (106)).
.

In other words, by reading and reproducing the signal using a clock frequency that corresponds to the magnitude of the slope of the voltage amplitude of the demodulated signal, it is possible to reproduce the audio signal on the same time axis as when it was recorded.

After one byte of the audio signal is thus reproduced, the address counter of the CPU 79 is incremented by 52 to prepare for the reproduction of the next one byte of the audio signal (step (107)). In this state, it is determined whether the RAM 84 matches a predetermined set value (step (108)). If the value of RΔM■ 84 matches the set value, the remaining amount indicator lamp 33 or 34 indicating the remaining amount is lit (step (109)).

In other words, in the case of this embodiment, if the last remaining @ interval of the storage capacity of the storage element 81 for audio data to be recorded is 20 seconds or 10 seconds, a warning is issued regarding the remaining capacity of the storage element 81 for audio data. The remaining amount indicator light 33 or 34 lights up.

On the other hand, in a step (110)) to detect the presence or absence of an end marker in parallel, if the end marker has not yet appeared,
That is, if there is still room in the storage capacity of the audio data storage element 81, it is detected whether or not the stop switch 26 is operated next (steps (10) and (111)).
). If the stop switch has not been operated, it is subsequently determined whether or not the cue switch 23 has been operated (step (112)).

In this way, if the end marker does not appear and neither the stop switch 26 nor the cue switch 23 is operated, the address pointer data of the address counter of the CPU 79, that is, the voice incremented in step (107,) It is determined whether the next reproduction address in the data storage element 81 matches the data recorded in the RAM 85 (step (113)).

In other words, it is determined whether or not the audio signal recorded by this operation still remains.

If it is determined in this way that the address pointer data of the address counter of the CPU 79 and the data in the RAM 85 do not match, this indicates that there is still recorded audio data, so the steps continue. (Returning to step 102>, the next audio data is read from the audio data storage element 81 and reproduced.

In addition, the address pointer data of the CPU 79 and the RAM■8
If the data match the data of 5, it indicates that recording in the partial area in the audio data storage element 81 has already been completed, but the next audio data storage element 8
In order to reproduce the recording in the partial area within 1, the next address pointer data is read from RAM 84 (step (114)). The read address pointer data is then preset in the address counter of the CPU 79 (step (115)).

Then, the audio data stored in the partial area of the audio data storage element 81 corresponding to the newly preset address pointer data is played back, and for this purpose, the process returns to step (102) and the address pointer data preset in the address counter is reproduced. Step address pointer data (
100), the audio data is displayed on the marker indicator lamp 28, and at the same time, the audio data in the partial area of the audio data storage element 81 corresponding to this address pointer data is read out (step 100).
102)).

In this way, the recorded data is sequentially played back, and when the storage capacity of the audio data storage element 81 approaches its end, the remaining capacity indicator lights 33 and 34 light up as described above, and the audio data storage element 81 reaches the end. When the storage capacity in the element 81 is completely filled, an end marker appears and step (
110), this end marker is detected, and the interrupt operation of the 1-byte signal to the CPU 79 is stopped (step (1)
16)”).

Next, step (117) to determine the presence or absence of a memory pack.
), if there is no memory pack, the address counter of the CPU 79 is cleared (step (118)), and a stop mode is entered (step (119)). If there is a memory pack, it will be explained later.

If the playback operation is to be stopped even though there is still some storage capacity in the audio data storage element 81, the stop switch 26 can be operated (step (10).
), (111)), the interrupt of the 1-byte signal to the CPU 79 is stopped (step (120)), and the address pointer data at this time is written to the RAM 86 (step (121>)).

That is, the RAM 86 stores the address 56- at the end of playback. Address pointer data is recorded.

After writing the address pointer data to the RAM 86 in this way, the solid-state recording/playback device ? -○ becomes the stop mode (step ((119)).

Note that the reproduction/cueing operation in step (112) will be described later.

In this way, the reproduction operation according to this embodiment is performed by using the address pointer data of the audio data storage element 81 and the RAM 8 of the control storage element 83 while the CPU 79 is reading the audio data.
Constantly compare the address pointer data recorded in 5.
When both data become the same, the one closest to the data from among the address pointer data stored in RAM 84,
A partial area of the audio data storage element 81 is selected, and the audio data is read out and reproduced.

In other words, the unrecorded portions are skipped and only the recorded portions are sequentially played back.

(6) Skip/playback operation In this case, the user desires to playback from a certain partial area in the audio data storage element 81 or the audio data storage element 103, and selects and plays the partial area. . In this case, when the skip switch 24 is turned on, C
The PU 79 determines the skip operation mode (step (6)) and executes the skip processing program (step (1B)).

That is, according to the skip flowchart in FIG.
When the skip switch 24 is operated, step (
25))' The CPU 79 is a ROM in the control storage element 83.
Step (26)) of sequentially reading address pointer data from 88, and sequentially lighting up indicator lamps 28 in partial areas corresponding to the read address pointer data one by one (step (27>)).

Skip switch 2 is the same as the operation during skip recording below.
4 is turned off or not (step 28>>
If the end marker is not turned off, step (30)) determines whether there is an end marker. If the end marker does not appear, continue reading the address pointer data (step (26)). If the end marker appears, the next step is to read the address pointer data. The presence or absence of the memory pack is determined (step (31)), and if there is no memory pack, it is meaningless to continue skipping any further, so the solid-state recording and reproducing device E 20 enters the stop mode (step (24)).

In addition, when the memory pack 52 is connected, the control memory element 83 in the main body 51 is switched to the control memory element 97 in the memory pack 52 (step <32)), and the memory pack is being skipped. Step (33) to turn on the memory pack indicator light 29 to indicate that
)) Continue reading address pointer data (step (26)). Note that the memory pack indicator light 29 is connected to the control memory 83 in the memory pack 52.
The light is turned off at step (24) when the END marker written in RΔM 98 is read out or when the solid-state recording/reproducing device U 20 enters the stop mode.

In this way, when the selected partial area 59- area is reached during the skip operation, the skip switch 24 is turned OFF.
(Step (28)). Skip switch 24 is O
When it is turned FF, the address pointer data in the ROM 88 at this point is incremented, stopped, and held in this state (steps (two steps)).

In the case where reproduction is to be performed, when the reproduction switch 22 is turned on, the CPU 79 determines that it is in the reproduction mode (step (7)) and executes the reproduction program. (Step (19)).

That is, when the playback switch 22 is turned on (step (83)), it is determined whether or not a playback operation has been performed before this playback operation based on whether or not there is data in the RAM 86 (step (84)). If it is determined that the previous playback was performed, the address pointer data of this RAM 86 is read out and incremented by 1 byte.
85)), and if no previous playback operation has been performed, it is determined whether or not there is retained data in the ROM 88 (step (86)), in which case the step 60-(29) described above is performed. Since the address pointer data for 4-nip playback is held in the ROM 88, proceed to step (88), preset this data in the address counter of the CPU 79, and perform the same playback operation as the above-mentioned playback operation. Start from the partial area where the operation was stopped. Note that by performing this skip operation, the marker indicator light 28 that was lit during playback is turned off.

(7) Repeat/playback operation In this case, by turning on the repeat switch 25 during playback, the address pointer is moved faster than the recording address at the rear of the audio data storage element 81.103, which corresponds to the rewinding operation of a normal tape recorder. The data is sequentially scanned and the necessary playback position is selected.

By turning on the repeat switch 25, the CPU 7
Step 9 determines whether the mode is repeat mode (step (5)) and executes the repeat processing program (step (17)).

That is, by turning on the repeat switch 25 (step (34)), it is determined whether there is a memory pack or not (step (35)). Start repeat operation.

That is, the memory pack indicator light 29 indicating that there is a memory pack lights up (step (40)), and accordingly, the control memory element 83 in the main body 51 is switched to the control memory element 97 in the memory pack 52 (step (40)). (41)),
A step (42)) of reading address pointer data from the ROM 88 in the control storage element 83 in order from a large number to a small number, and a step (43) of sequentially blinking the marker indicator lights 28 corresponding to this address pointer data.
)).

In this way, the address pointer data is sequentially read, and the presence or absence of the end marker in the memory pack 52 is determined (step (44)).The above reading operation is continued until the end marker does not appear, and when the end marker appears, switches the control memory element 97 in the memory pack 52 to the control memory element 83 in the main body 51 (step (45)),
A step (46) of turning off the indicator light 29 indicating that there is a memory pack; and a step of sequentially reading address pointer data corresponding to the audio data storage element 81 in the main body from the ROM 88 from the largest number to the smallest number. (36)), the marker indicator lamps 28 are made to blink in sequence in response to this reading operation (step (37)), and it is determined whether or not the repeat switch 25 is turned off (step (3B)). The above operation is continued while the OFF operation is not performed, and when the OFF operation is performed, the address data of ROM8B is incremented at that point, reading is stopped, and this data is held (step (3)
9)).

When the next playback operation is performed in this state, it is determined that the CPLJ 79 is in the playback mode, as in the skip playback mode described above, step (7)>, and the playback processing program is executed (step (1)).

63- That is, when the playback switch 22 is turned on (step (83)>, the data in the ROM 88 is preset to the address counter of the CPU 79 (step <88)), the data in the audio data storage element 81 corresponding to this address pointer data is The playback operation is started from the partial area.

Note that in this repeat operation program, the recording and playback operation is stopped in the memory pack 52 at the same time as recording and playback, and recording and playback cannot be performed from an appropriate partial area of the audio data storage element 103 in this memory pack 52. The program is as follows, but this is because the memory pack 52 originally uses the audio data storage element 103 which has a smaller storage capacity than the audio data storage element 81 of the main body 51.
It is intended for supplementary purposes to compensate for the lack of storage capacity of the audio data storage element 81 in the main body, and the storage capacity of the audio data storage element 103 is not that large, so the repeat operation is This is because it was considered that the selection 64 of the partial area in which the recording/reproducing operation of the audio data storage element 103 in the memory pack 52 is started is unnecessary.

However, the audio data storage element 1 in the memory pack 52
It is also easy to add a repeat recording/playback mode within this memory pack 52 by using a memory element with a large storage capacity M in 03. Note that the marker indicator light 28, which was turned on due to the reproduction operation before the repeat operation, is turned off by the repeat operation.

(8) Cue/playback operation This is a case where the audio data currently being played is skipped and the audio data recorded in the next partial area is played back.

This is carried out by turning on the cue switch 23 during playback.

That is, when the cue switch 23 is turned on, the CPU
79 is running the playback program (step (1)
9)) During this playback program, turn on the cue switch.
is detected (step (112)), and RΔM■ is detected during recording.
Step (122) of reading the address pointer data closest to the address pointer data of the storage element 81 for audio data currently being reproduced from among the address pointer data recorded in the audio data storage element 85.
). Then, the address pointer data closest to and higher than the read address pointer data is read from the RAM 84 (step (114)) 6 Next, the read address pointer data is transferred to the CPU.
79 address counter in a preset step (1
15)), the audio data is read from the address in the audio data storage element 81 corresponding to this address pointer data and reproduction is continued (step (102)).

Through this series of operations, the cue switch 23 is turned on.
When the partial area is played back, the partial area being played back is skipped and the next partial area is played back from the first address.

The main pick-up switch 23 is a type of switch in which, even if it is turned ON once, it turns OFF as soon as the finger is released, and the next cueing operation is performed by turning the cueing switch 23 ON again.

(9) Repeating play/stop operations Turn on the stop switch 26 during data playback.

In step (111)), the address pointer data of the audio data storage element 81 which is currently reading audio data is written into RΔM 86, and the solid-state recording and reproducing device enters the stop mode (step (1')). 19)), when the playback mode is set again (step (83)), it is determined whether there is data at the position where the previous playback ended (step (84)), and the address pointer data of this data is set to 1.
Reproduction is started from the address incremented by byte (step (85)).

That is, when repeating the playback/stopping operation, playback starts at 0 following the address at the end of the previous playback.

(10) Operation of the memory pack The audio data storage element 81 and each scale data storage RAM ■~■8/I~86 stored in the main body 51 and the same type of audio data storage element 103 and RAM ■~■98 ~100
A memory pack 52, which is packaged and can be carried freely, is installed outside the main body, and the main body 67 and the memory pack 52 installed outside are connected to the connector 5.
4.55, and is used to extend the recording and playback time and to edit and copy audio data recorded in the internal audio data storage element 81.

Note that the audio data storage element 1 in this memory pack 52
03 and RAMs 98 to 100, a backup memory 102 is provided in the memory pack memory 52 to prevent stored data from being volatilized when the main body is disconnected from the power supply.

The memory pack 52 includes RAM 98~ with the same function as the main body 51.
The reason why 100 is provided is to avoid any inconvenience in reading the recording address of the audio data storage element 103 when the memory pack 52 in which audio data is already stored is used in a main body other than the main body 51.

Note that when this memory pack 52 is connected to the connector 54, the signal line 95 inside the main body 51 is connected to ground 68- through the connector 54.55 and the signal line 96 inside the memory pack 52, and the CPU 79 is After determining that this is the case (step (2)), various programs associated with the existence of the memory pack are executed (step (3)).

The contents of various programs associated with the existence of this memory pack include, for example, when the end marker stored in the control memory element inside the main body is read, the control memory element inside the main body is switched to the control memory element inside the memory pack. operations (steps (32), (123), etc.), operations to read out the address pointer data for the memory pack in the address pointer data storage ROM 88 following the address pointer data for the main body, lighting of the memory pack operation indicator 29 (steps (33), (124> etc.).

By providing the memory pack 52, in the case of a copy operation to be described later, the copy switch 21 is operated, and the audio data recorded in the audio data storage element 81 in the main body is transferred to the memory via the data save RAM 87. pack 52
It becomes possible to perform a copy operation in which data is sequentially recorded in the audio data storage element 103 in the audio data storage element 103 starting from the first address.

Furthermore, when the end marker of the audio data storage element 81 housed inside the main body 51 is detected, the marker indicator light 28 turns on at the same time as the memory pack indicator light 29 (steps (33), (124), etc.). The marker indicator light 28 will display each partial area of the audio data storage element 103 in the memory pack 52.

Next, the operation when using the memory back 52 will be explained.

<a) Recording mode When the recording switch 21 is turned on, the CPU 79 determines the presence or absence of the memory pack 52 (step (2)). As described above, the presence or absence of the memory pack 52 is determined by connecting the memory pack 52 and installing the signal line 95, thereby determining whether the memory pack 52 is inserted.

When it is determined that the memory pack 52 is inserted, the CPU 79 switches the control memory element 83 in the main body 51 to the control memory element 97 in the memory pack 52 (step (123)), and turns on the memory pack indicator light. 29 is turned on (step (124)). Following this operation, CPU7
9 accepts a 1-byte signal interrupt (step (6)
2)) From then on, the memory pack 52 is
Recording is performed in the audio data storage element 103 inside.

After recording the bit-parallel signal read out by the 1-byte Shingetsu in this way, step (71) increments the address counter in the CPU 79.
), the presence or absence of an end marker in the memory pack 52 is determined (step (125)). If the end marker does not appear and the stop switch 26 is not operated (step (126)), the CPU 79 performs the next step.
After reading the byte signal (62), recording to the audio data storage element 103 in the memory pack 52 is continued.

While recording continues in this manner, whether or not the end marker in the memory pack 52 is detected (step <1
25)), when the stop switch 2671- is operated (step (126)), the interruption of the 1-byte signal to the CPU 79 is stopped (step (127)).
)) and the address counter is cleared (step (12)
8)), solid-state recording and playback device 6? -Ω- becomes the stop mode (step (129)').

In this way, recording into the memory pack 52 is completed.

(b) Skip/recording operation This is an addition of the above-mentioned operation within the memory pack to the skip/recording operation within the main body. The explanation will be omitted.

(C) Repeat/recording operation This is similar to the skip/record operation in (b).

(d) Repeating the recording/stop operation This is the addition of the memory pack operation in the flowchart in Figure 11 above to the record/stop operation of the main unit, and the other operations are the same as the repetition of the record/stop operation of the main unit. Since there is, I will omit the explanation.

72-(e) Reproduction operation The above-mentioned memory pack operation is added to the reproduction operation of the main body.

(f) Skip/reproduction operation This is the addition of the memory pack operation shown in FIG. 11 to the skip/reproduction operation of the main body.

((+) Repeat/playback operation This is the repeat/playback operation of the main unit plus the operation of the memory pack shown in FIG. 11 described above.

(h) Cue/playback operation This is the cue/playback operation of the main body plus the memory pack operation shown in FIG. 11 of the above book.

(i) Repetition of playback/stop operation This is the addition of the memory pack operation in the flowchart of FIG. 11 to the repetition of playback/stop operation of the main body.

(11):] The copy operation is carried out using the audio data storage element 8 in the main body 51.
This is an operation of transferring and transcribing a specified part or all of the audio data stored in the audio data stored in the audio data storage device 103 in the memory pack 52. This operation will be explained according to flowcharts 1 to 1 in FIG. 12.

First, the main unit is played back to find the audio data to be copied to the memory pack 52. After selecting the desired copy location, set to -H stop mode and press copy switch 21.
Turn on. By turning on this copy switch 21, C
The PU 79 determines that it is in the copy mode (step (9)), and executes the copy program described in detail below (step (21>)).

That is, when the copy switch 21 is turned on (step (13)
0)), the presence or absence of the memory pack 52 is first determined in step (131)). If the memory pack 52 is not inserted, the bee operation is impossible, so the main body 51 enters the stop mode (step (131)). 132)). If the memory pack 52 is inserted, the copy indicator light 30 will light up to indicate that the copy operation is in progress (step 133).
, the CPU 79 sets the start address pointer data of the audio data storage element 103 in the memory pack 52 (
Step (134,)).

Next, the data in the RAM 086 in the main body 51 is read out, and the address pointer data corresponding to the previous partial area in the audio data storage element 81 is read out from the RAM 84 (step (135)). 8
4 address pointer data to R in the memory pack 52.
Write to ΔM 98 (step 136)) and read the audio data in the audio data storage element 81 at the address corresponding to this address pointer data (step 1
37). Then, this audio data is written to the audio data storage element 103 in the memory pack 52 (step (1)
38)). Next, the address counter of the CPU 79 is incremented (step (139)).

That is, by the above operation, the audio data storage element 81
A portion of the data to be copied is selected, and the data is sequentially copied starting from the first data recorded in the partial area where the copy switch 21 is turned on.

75- This copy operation is performed when the stop switch 26 is turned on (step (140)), when the end marker is read from the RAM 086 (step (141)), or when the address pointer data at the end of recording is read from the RAM 086. (step (142)), the address pointer data at this time is stored in R in the memory pack 52.
The data is written to the AM 99 (step (143)), the copy indicator light 30 is turned off (steps (14, 4)), and the main body 51 enters the stop mode (step (145)).

In order to copy a plurality of audio data among the audio data recorded in the audio data storage element 81 in the main body 51, turn on the copy switch 1 each time (step (146)), and copy the data stored in the memory pack 52. The address pointer data recorded in the RAM 99 is read out, and the address pointer data corresponding to the partial area of the storage area in the audio data storage element 103 located after this is read out from the ROM 88.
step (147)), and set the address in the audio data storage element 103 corresponding to the read address pointer data (step (147)).
48)). Then, the read address pointer data is written into the RAM 086 in the memory pack 52 (step (1/19)). Then, the data is transferred from the audio data storage element 81 to the set address of the audio data storage element 103 and copied (step (138).
)). The following copy operation is the same as the previous copy operation.

That is, the audio data storage element 1 whose address is larger than the data read from RΔM 99 in the memory pack 52
The address pointer data of the partial area in 03 is stored in ROM8.
8, a segmented area in the audio data storage element 103 corresponding to the data is selected and transferred.

Although not shown in the flowchart of FIG. 12, the copy indicator light 30 is also turned on during the second copy operation.

By the above operation J:, the solid-state recording and reproducing device Chiku of this embodiment transfers the audio data stored in the audio data storage element 81 in the main body 51 to the audio data storage element 103 in the memory pack 52. However, since the transfer speed in this case is determined by the signal processing speed of the CPU 79, it is possible to copy at a much higher speed than with a tape recorder using ordinary magnetic tape.

Next, the operation of the indicator lights of the solid-state recording and reproducing apparatus of this embodiment will be summarized and explained.

(1) Marker indicator light This marker indicator light is composed of a total of 18 LEDs that display time for a total of 180 seconds in 1 ti 10 seconds.
An audio data storage element 81 whose frequency is 10 times the clock frequency of the delta modulation/demodulation circuit 63 and 68 necessary to obtain satisfactory audio quality is converted into bytes and is necessary to store 10 seconds of audio data. .103 partial area storage capacity. Therefore, since the number of address data is the same, we set the address data every 10 seconds in advance, and when we compare the address data during actual operation and the set address data once, and when they become the same value, it means that 10 seconds have passed. Become.

In this embodiment, in order to reduce the number of audio data storage elements 81 and 103, a variable clock system is used for the delta modulation/demodulation circuits 63 and 68, in which the clock frequency differs in proportion to the magnitude of the slope of the audio signal. Errors occur due to differences in information, but by using an average value for the address data value set in advance, the errors are averaged out for 10 seconds and do not cause any practical problems.

In addition, if a time base composed of a crystal pendulum is set in the setting data, and a pulse is generated from the time base every 10 seconds, the address data of the data storage element is recorded in the RAM 84.98. Accuracy can be improved.

(2) Remaining capacity indicator light In the solid-state recording and reproducing apparatus of the present invention, since the audio recording medium cannot be visually seen like a magnetic tape, it is necessary to accurately display the remaining capacity.

In this embodiment, in addition to the marker indicator light 28 described above, the last one
When reaching 0 seconds and the last 20 seconds, the LEDs of the remaining capacity indicator lights 34 and 33 are flashed to alert the user. The timing of lighting the LED is such that the multi-bye break circuit is triggered by the above-mentioned lighting signal of the LED for displaying the remaining amount time, and the circuit performs a blinking display.

As an alternative method, a simple method such as dividing the necessary portions of the marker indicator lamps into different colors may be used.

(3) Recording/playback/play/cue/stop/memory pack operation/skip/repeat/copy indicator light Lights up when the corresponding mode is being operated, and any indicator LED
Also, while the CPU 79 is operating in the relevant mode, the CPU 7
It lights up based on the lighting data from 9. Note that the skip/repeat mode is related to the recording or playback mode, so it does not light up independently.

(4) All the indicator lights mentioned above are connected to each part via drive circuits 89 and 93.

[Effects of the Invention] -8-Q - As explained above, in the solid-state recording and reproducing device of the present invention, a solid-state memory element is used as a storage means, and such a stop switch is provided with a pause function. , there is no quality deterioration such as fluctuations in audio signals or distortion noise caused by mechanical drives, and there is no quality deterioration such as wear and tear on storage media such as magnetic tapes and disks, and it is highly reliable and maintenance-free. The present invention not only provides the effects commonly associated with using a solid-state memory element as a storage medium, but also provides reliable operation without confusion even in the case of urgent operation, and provides high operability.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the overall structure of the present invention, Figs. 2 and 3 are perspective views of an embodiment of the invention, and Fig. 4 is a block diagram showing the circuit structure of an embodiment of the invention. , Figure 5 is the fourth
FIG. 6 is a waveform diagram of the circuit shown in FIG. 5, and FIGS. 7 to 12 are flowcharts showing the operation of an embodiment of the present invention. 61......Audio detection circuit 63
・・・・・・・・・・・・・・・Delta modulation circuit 64・
......Serial-to-parallel conversion circuit 65...
・・・・・・・・・・・・Input/output switching circuit 66...
・・・・・・・・・Conversion signal bypass circuit 67・
・・・・・・・・・・・・Parallel-serial conversion circuit 68...
・・・・・・・・・・・・Delta demodulation circuit 71...
...... Muting circuit 72...
・・・・・・・・・・・・・Slope detector 73・
・・・・・・・・・・・・・・・VCO74・・・・・・
...... Frequency divider circuit 76 ......
・・・・・・PIO79・・・・・・・・・・・・・・・
CPU80・・・・・・・・・・・・Operation button 81
．． 103...Storage element for audio data 82.102...
・Backup battery 83.97...Control memory element 84-87.98-100...RAM88.
・・・・・・・・・・・・ROM89.93...
...Drive circuit 90.94...Indicator light 91...C0M92...
・・・・・・・・・・・・Marudivibrator agent attorney Sa Suyama - Figure 8

Claims (1)

[Claims] an encoding means for encoding an audio signal; a first storage means for storing the audio signal encoded by the encoding means; and a first storage means for storing the encoded audio signal stored in the first storage means. a decoding means for decoding; a stopping means for stopping the operation of reading and reproducing the audio signal stored in the first storage means; a second memory for storing the address of the memory means;
1. A solid-state recording and reproducing device comprising a storage means, and a reproduction start means for starting a reproduction operation successively from an address next to the address stored in the second storage means.