JPS60125063A - Image signal processor - Google Patents

Abstract

PURPOSE:To obtain an output by performing fixed-value slicing processing and pseudo half-tone processing through an image signal processor by addressing a memory which is stored with binary or many-valued information for an image signal through an image signal processor with the image signal. CONSTITUTION:A dither fixed slice ROM60 is stored with patterns of fixed threshold value processing and pseudo half-tone processing. A selector 65 selects a pattern in the ROM60 on the basis of outputs of a subscanning counter 63 and a main scanning counter 64. The ROM60 addressed with the image signal outputs a dither DS and a fixed threshold value CS, and a selector 61 makes a selection to obtain an image output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device that performs binarization or higher multivalue processing on an image signal in a digital copying machine, an electronic file, or the like.

Conventionally, this type of circuit consists of a comparison circuit that compares an image signal and a reference signal, and by making the reference signal value variable, the density of the output image can be adjusted, and by synchronizing the reference signal value with the image signal. The method was to perform pseudo-halftone processing by changing according to a predetermined rule.

FIG. 1 is a block diagram showing an example of the conventional image signal processing circuit.

Blocks 1.2 surrounded by broken lines are blocks for binarization, and by increasing the number of blocks, processing corresponding to multivalue, for example, hexanarization and quaternization is performed. Comparison circuit 10.20 connects a multivalued image input signal and selector 11.21
It compares the multivalued reference signal outputted from the multilevel reference signal, performs binarization, and outputs the comparison result.

The selectors 11- and 21 are switching circuits for switching between a fixed-value reference signal and a pseudo-halftone processing reference signal using a selection signal such as a switch. The latch circuits 13 and 23 are circuits for generating fixed-value reference signals for comparison, and set slice levels for binarization using, for example, the CPU or switches.

The dither ROMI 2.22 is a memory that preferably stores a plurality of reference signals for pseudo halftone processing, and the 0 main scanning counter 30, which stores a predetermined pattern (dither pattern) in advance, controls the image to be compared. The 0 latch circuit 32, which is a counter that operates in synchronization with the signal and synchronizes in the main scanning direction, is connected to the dither ROM 12.22.
This is a circuit for selecting one of a plurality of patterns according to, for example, image quality.

According to the circuit configuration of the first decoy, when performing multi-value processing, blocks 1 and 2 have a number corresponding to the multi-value processing (in the case of 3 values, 2
In addition, when converting a multi-value signal such as 00.01.10.11 in binary numbers, the disadvantage is that only 3 ate) are required in the case of four values, which increases the scale of the circuit. There is also the drawback that it is impractical because the only way to cope with this is to encode the binary image output output from the block, which results in a very large-scale circuit.

Furthermore, when using a comparator circuit to handle an image signal with a large amount of data such as 14 bits or 16 bits, the circuits are connected in cascade and delay time is added, which is disadvantageous for high-speed processing. To further address this,
It is conceivable to use high-speed logic elements, but this also has the disadvantage of being extremely expensive.

In view of the above-mentioned drawbacks, the present invention aims to provide an image signal processing device that can easily handle multilevel processing without using a comparison circuit, and that can be performed at low cost and at high speed.
Specifically, by addressing a memory storing binary or more ternary information for the image signal with the image signal, the image signal can be selectively subjected to fixed value slicing processing or pseudo-halftone processing. It is an object of the present invention to provide an image signal processing device that obtains a multivalued output higher than that.

Hereinafter, the present invention will be explained in more detail with reference to FIG. 2. FIG. 2 is a diagram showing the structure of a digital copying machine to which the present invention is applied. A is a reader that photoelectrically converts and reads the original to be copied, based on the image No. m output from Bd reader A.
This is a printer that records an image on a recording material. 1 in reader A, W to copy, problem is original glass 83
The reference point is on the back left side when viewed from the front. That IQ paulownia is sitting on the manuscript cover 84 b
? , 1 was found on the 2nd floor. The original is illuminated by the full-light lamp 82, and the reflected light is reflected by the mirror B.
An optical path is formed through the 5s 87 and the lens 86 so as to focus the light onto the CCI 810. The mirror 8f and the mirror 851i2 move at a relative speed of 1. This optical unit operates at a constant speed with a left force of 1 while applying PLL using a L)C servo motor.
ra/simple. The size of originals that can be processed is A5 to A3, and the size of originals that can be processed is A5. B5. Each size of A4 is vertical ti1 right, B4. A3 Cyme is a yuzu holder.

Next, regarding the main scanning direction, the main scanning r (y is the maximum horizontal width of A4 size 297 square meters depending on the document placement direction mentioned above.And in order to resolve this at 16 pet/s + w, eel) 810 bits. 4752 as a number (=zo7X
16) bits are required.

Next, referring to FIG. 2, the view of the printer tsf)ta placed under the reader A will be explained. The image signal processed by the reader A and converted into a bit serial is inputted to the laser scanning optical system unit 105 of the printer B. This unit includes a semiconductor laser, a collimator lens, a rotating polygon mirror, and an F0 lens.

It is made up of threads that prevent it from falling down. Icon 4M from the leader
The voltage υ is applied to a semiconductor laser, the electricity and the light are switched, and the diverging laser light is made into parallel light by a collimator lens, and is irradiated onto a polyhedral mirror that rotates at high speed. . The rotation speed of this polyhedral mirror is 2.60 Orpm"C.The scanning 11J is about 400 degrees, and the effective 11!I image 11" is A
It is 291 Tomi with 4 horizontal dimensions. Therefore, the signal frequency applied to the semiconductor laser at this time is approximately 20MBs (NKz
). The laser beam from this unit is transmitted to the mirror 104.
The light is incident on the photoreceptor 88 via.

This photosensitive layer 1488 is made up of three layers, for example, a conductive layer, a photosensitive layer, and an insulating layer. Therefore, process components are arranged to enable image formation. 89
90 is the uII static eliminator, 91 is the primary double charger, 92 is the secondary charger, 93 is the IjIJ side editor 2-7°, 94 is the developer, 95 is the paper feed cassette, 9611'
iMI#, row 2.97 is paper feed guide, 98 is resist -1 2.99 is transfer charger, 100 is separation roller, 1
01 is a conveyance guide, 102 is a standard yfi sushi, and 103 is a tray. The speed of the photoreceptor 88 and the conveyance system is the same as the forward path of reader A (180 m/sec. Therefore, the speed of reader A
When making copies using a combination of and printer B, the continuous output of ° is A4
That's 30 sheets/minute. Also, 1 Printer B uses a separation belt on the front side to separate the copy paper that has arrived on the photosensitive drum on the 8th, but for that reason, the belt) + 71 minutes II
! 1m is missing. If the 13th minute (No. The separation belt is designed to cut the video electrical signal of the print output when it reaches 8 times.Also, if toner adheres to the leading edge of the copy paper, it will be fixed, and the mud layer roller will be jammed. To avoid this, cut #14 with leader A (til) so that toner does not adhere to the leading edge of the paper by 2 + lJ.

The copying apparatus of this example has intelligence such as image editing, but this intelligence is provided by the CCD 81 on the side of the reader A.
Edit the 1st issue you read and turn it into Vi] oshi, reader A
At the output stage, a signal with a constant number of bits (47 aa) and a constant speed is output in all cases. The intelligence function is 0.5 →
Enlarging/reducing to any magnification within the range of 2.0 meters;
Trimming function that extracts III4M only in the specified area, cropped image can be placed anywhere on the copy paper11
There is a function to move the manuscript to r.1 There is a function to record the manuscript placed on the original stand. In addition, there is a pseudo-halftone processing function, AE@ function, which performs dither processing by specifying a key. Furthermore, it has a twisting function that combines these individual intelligent functions.

FIG. 3 is a block diagram showing an example of the configuration of circuit #1 related to reading 1 badge processing in reader A. 1j1. The image of the document is illuminated by a light source, for example a fluorescent light, and is projected onto a one-dimensional array sensor 42 by an optical lens 41.
CI). Original 40 is read by CCD 42]
The scanning position is electrically scanned in the scanning direction (main scanning direction), and the scanning position on the original tree is moved by a sub-scanning drive system (not shown) (sub-scanning)
The original document 40 is sequentially scanned in the illustrated sub-scanning direction to read the entire image.

The CCD driver 43 is a circuit that divides the oscillation output of the oscillation circuit 44 and generates the drive timing of C(,:D42).
It outputs a clock (image clock) corresponding to 42 pixel readouts and a synchronization signal for each main scan input (main scan synchronization signal).

The amplifier circuit 45 is a circuit for amplifying the analog image signals output from the CCD 42, and the amplified analog tI! The II image signal is subjected to analog-to-digital conversion by an A/D conversion circuit 46. This digital lI! Il statue 4
No. 74 is input to the image signal conversion circuit 47 and subjected to simple binarization, binarization by pseudo halftone processing, or more multi-value processing.

The switch 48 is a switch for selecting and specifying whether or not to perform pseudo-medium 1141 itl processing, and the density switch 49 Jd specifies which degree of image density is to be processed during binarization or multi-value conversion. There is a switch for this purpose. The density switch 49 corresponds to, for example, a density lever operated by an operator in a copying machine to specify the copy density.

Next, the operating principle of the image signal conversion circuit 4) according to the present invention will be explained using FIGS. 4 to 10.
FIG. 2 is a diagram showing a basic circuit for value conversion or multivalue conversion processing.

The memory 50 is a randomly accessible memory from which data written at an address determined (by a signal connected to the address signal @51) can be read out at will. For example, d1 Intel's EPROM 27
32A, static) LAM212B, etc. can be used. When using a non-volatile memory such as WFROM, mask LOM, etc., patterns to be described later may be written in advance as data. On the other hand, static) t
When using an intermittent memory such as AM, it is necessary to add hardware to write pattern data every time the power is turned on, but the advantage is that the pattern can be changed arbitrarily. .

The address signal line 51 has a digital image to be processed (ff
By this, the memory 50 is addressed and the data signal line 52 is converted into a binary or multivalued v! Obtain A image output.

#! Using Figure 5, the case of obtaining a 12-valued signal will be explained. (2) The horizontal axis shows the input 1liIl image data value, and the vertical axis shows the output image data value. Human image data is 8 bits in binary, so it has values from 0 to 255 in 1O decimal, where the value 0 is the white level.
Let 255 represent the black level. In the output image data, 0 is white and l is black.

The input image data and address signal line 51 are connected so that the input image data value and the address of the memory 5o match, and 0.
Binarization is performed by writing the pattern 1 in advance.◎ In Figure 5, (a) is I+ of dark I/2 density! ! I image output, (b) moderate Il! (C) shows the respective patterns to be written into the memory to obtain a light-density image output.

Fig. 5 (In the case of a
By the way, since the output 1liII image data value changes from the value 0 to the value 1, the proportion of the value 1 (black) in the output image data increases, resulting in a pale image. Similarly, Fig. 5(b)
Since the input kIJ image data value changes from the value 0 to the value l near the center value -(C) and the value 255, respectively, the image output and N -It depends on how the image appears.

FIG. 6 is an explanatory diagram of the case of quaternization. Input image data is 8 bits in binary, output image is 2 bits in binary, that is,
This is an example in which there are four values in decimal: O=lt 2 *S.

(a), (b), and (c) in Fig. 6 are 8 le when converted to 4fa linearly, and #15 shows the same diagram - 00, OX in the data at the address of the memory 60 corresponding to the image data value. , 10.11 It is good to enter 11 patterns of 11 - 0 Figure 6 (a) shows the appearance of the III image of medium density, (the appearance of the [1! I + image of the density [1! ) becomes the I[!l image output of a person who gets drunk.

Figure 6 shows an example of L1 linear 4-value conversion, but it is also possible to perform multi-value conversion by adding visual correction, so-called γ correction, and distortion for visual effects. Figure 7 is an example of such a reform. Blood INam in the diagram
bvCedme') The output f)m image density becomes darker relative to the input. Therefore, in order to apply this conversion to the 4-value conversion shown in FIG. 6 and change the data in the memory 50, the hl
The advantage arises that an l-image transformation is also achieved.

In addition, in the case of Intel's E)' ROM2732A mentioned above, there are 12 address lines (4 bytes) and 8 data lines.
(8 bits), so if the input Im image signal is 8 bits, there will be 4 address lines, and in the case of 2 ft, there will be 7 extra bits of data lines. (a) , (b) , (Like CJ, by storing multiple different binarization patterns and selecting them with redundant address machine (No. 1), 24JK conversion is possible. Figure 8 is a diagram showing an example of specific data to be written to the memory 60.Human power i11!1gi: The signal is 8 bits and 2
This is an example of converting values into values. The 8-bit data is divided into bits and a pattern is written into each bit. As an example, a pattern is shown in which the output becomes darker from the 0th bit to the 7th bit. As mentioned above, when using the surplus artless signal section,
For example, the upper 4 bits are the select signal, and the lower 8 bits are the I signal.
l! Assigned to 1m signal 7)'V)', M [ooo
OXXXXXXXXJ, [.

001XXXXXXXXJ --noyo') na71't
It is sufficient to create a pattern similar to that shown in FIG. Image II - (The binarized force for d changes.

Next, pseudo halftone processing will be explained.

Figure 9 shows the threshold matrix (8X
Here is an example of 8). When the input Wimms is 8 bits, its value ranges from 0 to 255, so when comparing it with the input image signal and binarizing it, the threshold value for determining whether the value is 12 or higher is as shown in the figure. They are arranged like this. Conventionally, this matrix is written in a LOM, etc., the data is read from the ROM in synchronization with the l#image digital clock main scanning synchronizing signal, and the data is sequentially compared with the input i[IIi image signal by a comparator to generate the pseudo halftone 2 I was doing valuation.

This example uses the above-mentioned binarization and multi-rct conversion methods,
For each of the 64 elements of the matrix in Figure 99,
2 corresponding to the input image fif No. O to 255 in the memory 50
Create a pattern for value conversion or multivalue conversion, and add the 14@ line of matrix selection as an address.
Pseudo-halftone processing is performed by arranging the memory bO corresponding to line C1. Fig. 10 shows a specific example of the stored contents of the memory bO.

The input image signal is input to the lower 8-bit address of the memory 50.
The upper 6 bits contain 3 sub-scanning address signals and 3 main-scanning address signals as element signals of an 8x8 matrix.
This is the case when bits are connected.

In this case, there will be 14 pieces of address glue, so 16 x 8
BIT's Epi6hi, Lumi6hi, Intel L2EI, etc. can be used.

Sub-scanning address signal 1 For each of matrix numbers 0-63 determined by the main-scanning address signal, image signals O-2
All you have to do is write a pattern similar to the pattern shown in FIG. 8 for 55≠.

Also, since there are 8 bits of data, the conversion shown in Fig. 7 is applied to the matrix data shown in Fig. 9 or the input image data value, and then the binarized data is written for each bit. . By doing this, it becomes possible to output a dark image and a trace image by pseudo-halftone processing.

Furthermore, as with the above-mentioned binarization, the address ID of memory 5o is
If you increase the @ line and use it as a select signal, l1
It becomes possible to select iIt&pattern. Further, when a multivalued output of two or more values is required, the configuration is such that several bits tm of the 8 bits of data are selected.

Pseudo middle II using the fixed threshold processing and dither method explained above
m-signal conversion circuit using memory for I-tai processing 4)
Here is an example.

In Figure 1, the corners are processed with pseudo-halftone processing using defined values and the dither method. This is a conventional example of the No. 11 information concealment circuit 47. The dither fixed slice + tOuao uses the memory that stores both the fixed threshold processing and the pseudo medium Illυ4 processing described above, and by switching this, it also supports the processing of shear deviation. For example, in the case of 8 bits σ], 4 bits are used for fixed dark value C8 and 4 bits are used for dither DS, and 8 bits are output simultaneously.This output is output by halftone specifying switch 4. For example, 1 bit in the case of 2 values and 2 bits in the case of 4 values are selected and outputted by the selector 61, which is manufactured according to the operation. It plays the role of manufacturing selection corresponding to No. 49.

In addition, in the example of FIG. 11, the concentration +a from the concentration switch 49
The number is the dither fixed slice I ((7M
It can be directly connected to 60 address signals.

In the case of dithering, the address signal given to the dither fixed slice ROM 60 must be a dither matrix element selection signal synchronized with the input image data, and in the case of fixed threshold processing, a fixed address signal must be given.
It is necessary to change the way addresses are given outside of the element selection signal for identification slice processing and dither processing.Selector 65, which is operated by halftone designation switch 48 in the same way as selector 61, switches the address signal according to the processing. It is. The selector 65 selects a density of +11 when the slice is fixed.
The 8W62 signal is selected, and the dither matrix selection signals of the sub-scanning counter 63 and main-scanning counter 64 are selected during dithering.

Note that the density fine adjustment switch 62 is for carrying out a finer adjustment than the density switch 49, and is connected to the address line of the dither fixed slice (10M60) together with #1L4 from the density switch 49.

In the example of FIG. 11, when the type of dither processing is increased by ψ, the size plate of L6M (dither, fixed slice) becomes large size. Therefore, in the actual example shown in FIG. 12, the image processing using the density 1a@ is performed as rr by the correction shown in FIG. 7.

Correction 1tOMyoi is a memory for correcting the characteristics of the input signal as shown in FIG. Yes, use a memory like the one shown in Figure 4. Connect the human image (fj) and the density signal to the address f, and store the results of the calculation at the address determined by the image signal. 0 data is written in advance.In this case, songs a to C are selected using m=density No. 16 from switch 49.

The dither fixed slice 1tOM71 is the same memory as the dither fixed slice 5M in FIG. 11, but in this case, the density selection is supplemented in advance. becomes available.

Selector 72, Dark g (SW73. Main scanning counter 74,
The vice running food counter 75 and the selector 76 each have a feed 11.
These are similar to 61, 62, 63, and 64.65 in the figure.

Figure 13 is manuscript II! I image density, for example l57LII;
! Another embodiment of iI which has a function of changing the binary or higher multi-value conversion operation depending on the background level of the document 1IiIl to improve the quality of the original 1IiIl image! 1 is a configuration example of a 1-signal conversion circuit 47.

In FIG. 13, parts with the same functions as those in FIG. 11 are given the same reference numerals. The difference from FIG. 11 is that instead of the density fine adjustment switch 62, a density detector 66 is used as a selector 65.
This is the point connected to the input of

The concentration detector 66 has an A/D K conversion II! 1 road 4
When the V4 image signal from 6 is input, the peak value (white peak and/or black peak) of each line of this image signal is detected, and from this, the Ii! Determine the content of image 1 d and i! Selector 65 selects detection fi: No. 1 for obtaining binary or multivalued output according to the II image signal.
Enter.

When Shujingaku value processing is selected by the select signal,
The selector 65 selects the detection signal (No. 1) from the m-degree detector 66 and outputs this detection signal to the address frame as the selection signal of the dither identification slice RUM60.Therefore, as described above, the dither fixed slice) 40M60 Appropriate 2 for image signal with detection signal on address line
Multi-value data of the value or more will be selected.

Note that the density detector 66 may form a detection signal based on the peak value of 2 in. Also, before the actual reading of the original, a preliminary scan of the original may be performed to detect the entire surface of the original. 1
The detection signal may also be constructed based on the 111 image. In addition, both the # degree & key switch 62 shown in FIG. 11 and the fa degree detector 66 shown in FIG. 13 may be provided so that they can be selected as necessary.

According to this, it is possible to perform binary or higher multilevel conversion suitable for an image very well.

In the above embodiments, the selection between halftone processing and definition threshold processing was made by the operator using the switch 48.
It is also possible to judge the condition of the image by reading No. 1.3 and automatically switch between medium-dark toning and line drawing selection No. 1d. In this way, halftone i1! It is also possible to satisfactorily process images containing a mixture of Il images and line drawings.

It goes without saying that the image No. 1d processing described above can be applied to facsimiles, electronic files, etc. in addition to digital copying machines.

As explained above, according to the present invention, it is possible to perform binary or higher multilevel conversion of image No. 1d with a simple configuration, at low cost, and in processing. This improves the efficiency of ll image processing.

[Brief explanation of drawings]

! Figure 1 shows the configuration of a conventional image signal processing circuit, Figure 2
The figure shows the structure of a digital armpit photo to which the present invention is applied;
Fig. S is a block diagram showing an example of the circuit configuration related to read signal processing according to the present invention. Fig. 5 is a diagram explaining the basic circuit of the present invention. Fig. 6 is a diagram showing the 2-suppressing operation. FIG. 7 is a diagram showing the image signal correction operation; FIG. 8 is a diagram showing an example of data written to the memory; FIG. 9 is a diagram showing an example of a threshold matrix; FIG. 11, 12, and 13 are 12 diagrams showing examples of the configuration of the No. 116 conversion circuit, 40 is the original, and 42 Company CCt+. 46 is the Nφ conversion circuit, 47 is the side A100 conversion circuit, 50i
, i mesori, 60 and 71 are dither fixed slice ILO
M, 61.615972 and 16 are selectors. 1st official

Claims (1)

[Claims] Shio (1) Select fixed value slice processing or pseudo-halftone processing of the image signal by addressing a memory storing binary or more false value information for the image signal with the image signal. An image signal processing device 0 characterized in that it obtains a binary or higher multi-value output obtained by performing a fixed value slice process. An image signal processing device characterized in that during tone processing, an element signal corresponding to the image signal is further provided as a memory address signal.