JPH0738684B2 - Image signal processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image signal processing device for binarizing an image signal in a digital copying machine, an electronic file, or the like, or multi-valued. .

[Prior art]

Conventionally, this kind of circuit is composed of a comparison circuit for comparing an image signal and a reference signal, and by adjusting the reference signal value, the shading of the output image is adjusted, and the reference signal value is synchronized with the image signal. Pseudo halftone processing is performed by changing according to a predetermined rule.

FIG. 1 is a schematic diagram showing an example of the conventional image signal processing circuit.

Blocks 1 and 2 surrounded by broken lines are blocks for binarization, and by increasing the number of blocks, processing corresponding to multi-value, for example, ternarization and quaternization is performed. Comparison circuit
Reference numerals 10 and 20 compare the multi-valued image input signal with the multi-valued reference signals output from the selectors 11 and 21, perform binarization, and output the comparison result.

The selectors 11 and 21 are switching circuits for switching either a fixed value reference signal or a reference signal for pseudo halftone processing by a selection signal such as a switch. Latch circuit 13,
Reference numeral 23 is a circuit for generating a reference signal having a fixed value to be compared, and sets a binary slice level by, for example, a CPU or a switch.

The dither ROMs 12 and 22 are memories that preferably store a plurality of reference signals for pseudo halftone processing, and store a predetermined pattern (dither pattern) in advance. The main scanning counter 30 operates in synchronization with the image signal to be compared, and is a counter for synchronizing in the main scanning direction. The latch circuit 32 is a circuit for selecting one of a plurality of patterns of the dither ROMs 12 and 22 according to, for example, the image quality.

According to the circuit configuration of FIG. 1, when performing multi-valued processing, the blocks 1 and 2 have a number corresponding to the multi-valued processing.
On the other hand, in the case of 4-value, only 3 etc.) are required, and there is a drawback that the scale of the circuit becomes large.

Also, when performing multi-valued signal conversion such as 00, 01, 10, 11 in binary number, it is necessary to encode the binary image output output from the above block and deal with it, and it is a very large scale circuit. Therefore, there is a drawback that it is not practical.

Further, when an image signal having a large amount of data such as 14 bits or 16 bits is handled by using a comparison circuit, the circuits are connected in cascade and delay time is added, which is disadvantageous for high speed processing. Further, in order to deal with this, it is possible to use a high-speed logic element, but there is a drawback that the cost becomes very high.

Therefore, it is possible to perform binarization or multi-value conversion of the input image signal by addressing the memory storing the binary output or multi-value output corresponding to the level of the image quality signal with the input image signal. It is known from JP-A-58-186266 and JP-A-57-75379. According to the techniques disclosed in these publications, it is possible to perform binarization or multi-value conversion processing of an image signal with a simple configuration.

[Problems to be Solved by the Invention]

However, the one disclosed in the above publication does not consider the processing such as the halftone processing and the fixed threshold processing of the image signal which are different from each other. Therefore, depending on the type of the input image, a high-quality image cannot be obtained. There was a need for further improvement.

The present invention has been made in view of the above-described prior art, and is stored in the storage means and is subjected to halftone-processed binary or multivalued information and fixed threshold-processed binary or multivalued which is addressed and specified by an image signal. By making it possible to select either one of the information, whether the input image is a halftone image or a character image, a high-quality binary or multi-valued input image can be obtained with a simple configuration and at high speed. It is an object of the present invention to provide an image signal processing device that can be converted into an image.

A further object of the present invention is to specify halftone-processed information and fixed threshold-processed information stored in the storage means by using the digital converted image signal obtained by converting the density characteristic of the input image signal as an address signal. According to the present invention, it is possible to provide an image signal processing device capable of obtaining a halftone processed image and a fixed threshold value processed image whose density is corrected to an optimum density at a high speed with a low cost configuration using a memory having a relatively small memory capacity. It is in.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, an image signal processing device of the present invention is an input means for inputting an image signal, a first selecting means for manually selecting the density of an output image, and a density characteristic of the input image signal. Based on the selection of the first selecting means, and a characteristic converting means for outputting a digital converted image signal; and first information obtained by performing halftone processing on the digital converted image signal in a binary or multivalued manner. Storage means for storing second information that has been subjected to fixed threshold processing in binary or multi-value, and the first information that has been subjected to the halftone processing and the second information that has been subjected to fixed threshold processing stored in the storage means. Second selection means for selecting one of the two, and the halftone stored in the storage means which is addressed and specified by the digital converted image signal whose density characteristic has been converted by the characteristic conversion means. And outputting either one of information selected by said second selection means among the second information which is the first information and the fixed threshold processing, which are physical.

〔Example〕

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.

FIG. 2 is a diagram showing the structure of a digital copying machine to which the present invention is applied. A is a reader for photoelectrically converting and reading a document to be copied, and B is a printer for recording an image on a recording material based on an image signal output from the reader A. In the reader A, the document to be copied is placed on the document glass 83 downward, and the placement reference is on the left back side when viewed from the front.
The document is pressed onto the document glass by the document cover 84. The original is illuminated by the fluorescent lamp 82, and an optical path is formed so that the reflected light is condensed on the surface of the CCD 81 via the mirrors 85 and 87 and the lens 86. The mirror 87 and the mirror 85 move at a relative speed of 2: 1. This optical unit uses a DC servo motor
Move from left to right at a constant speed while applying the PLL. This moving speed is equal to 18 at the same magnification in the forward path irradiating the original.
It is 0 mm / sec and 468 mm / sec on the return return path. The resolution in the sub-scanning direction is 16 lines / mm. The size of the manuscript that can be processed is from A5 to A3 size, and the placement direction of the manuscript is A5, B5, and A4 in the vertical orientation, and B4 and A3 in the horizontal orientation.

Next, with respect to the main scanning direction, the main scanning width becomes a maximum A4 size lateral width of 297 mm depending on the document placement direction. Then, in order to resolve this at 16 pel / mm, the CCD81 needs 4752 (= 297 × 16) bits.

Next, referring to FIG. 2, an overview of the printer B placed under the reader A will be described. The image signal processed by the reader A and converted into bit serial is input to the laser scanning optical system unit 105 of the printer B. This unit consists of a semiconductor laser, collimator lens, rotating polyhedron mirror,
It consists of an Fθ lens and a tilt correction optical system. The image signal from the reader is applied to a semiconductor laser and converted into electric light, and the diverging laser light is collimated by a collimator lens to be parallel light, which is applied to a polygon mirror that rotates at a high speed, and the photoconductor 88 is scanned with the laser light. . The rotation speed of this polyhedral mirror is 2600 rpm. The scanning width is about 400 mm, and the effective image width is 297 mm, which is the A4 horizontal dimension. Therefore, the signal frequency applied to the semiconductor laser at this time is about 20 MHz (NRz). The laser light from this unit is incident on the photoconductor 88 via the mirror 104.

The photoconductor 88 is, for example, a conductive layer-photosensitive layer-insulating layer
Consists of layers. Therefore, the process components are arranged which allow it to be imaged. 89 is the front static eliminator,
90 is a pre-electrification lamp, 91 is a primary charger, 92 is a secondary charger,
93 is a front exposure lamp, 94 is a developing device, 95 is a paper feed cassette,
Reference numeral 96 is a paper feed roller, 97 is a paper feed guide, 98 is a registration roller, 99 is a transfer charger, 100 is a separation roller, 101 is a conveyance guide, 102 is a fixing device, and 103 is a tray. The speed of the photoconductor 88 and the transport system is 180 mm / sec, which is the same as the forward path of the reader A. Therefore, the speed at which a copy is made by combining the reader A and the printer B is 30 sheets / minute at A4. Further, since the printer B uses a separation belt on the front side to separate the copy paper that is in close contact with the photosensitive drum 88, the image corresponding to the belt width is missing because of this. If a signal is added to the width, the toner will be developed, and the toner will stain the separation belt, which will also stain the subsequent paper. The width of 8 mm is designed to cut the video electric signal of the print output. Also, if toner adheres to the tip of copy paper, it will cause a jam when it is wrapped around the fixing roller when fixing, so cut the electrical signal on the League A side so that toner does not adhere to the width of 2 mm at the tip of the paper. ing.

Although the copying machine of this example has intelligence such as image editing, this intelligence is processed by the reader A side by processing the signal read by the CCD81, and at any stage when it is output from the lead A. Even in this case, a constant speed signal is output with a constant number of bits (4752). As the intelligence function, it is possible to enlarge / reduce to any magnification in the range of 0.5 → 2.0 times, trimming function to extract the image only in the specified area, and move the trimmed image to any place on the copy paper. It has a moving function and a function of recognizing a document placed on the platen. In addition, a pseudo halftone processing function using dither processing by key designation,
Has AE function. Furthermore, it has a decoding function that combines these individual intelligent functions.

FIG. 3 is a block diagram showing an example of a circuit configuration related to the read signal processing in league A. The original 40 is illuminated with a light source, for example, a fluorescent lamp, and the original image is formed by an optical lens 41 on a one-dimensional array sensor 42, for example, a CCD.
The document 40 is electrically scanned in the reading scanning direction (main scanning direction) of the CCD 42, and the document 40 is sequentially moved in the sub-scanning direction shown by movement of the scanning position on the document (sub-scanning) by a sub-scanning drive system (not shown). It is scanned and the whole image is read.

The CCD driver 43 is a circuit that generates the drive timing of the CCD 42 by dividing the oscillation output from the oscillation circuit 44. The CCD driver 43 outputs a clock (image clock) corresponding to the image reading of the CCD 42 and a synchronization signal (main scanning synchronization signal) for each main scanning line.

The amplifier circuit 45 is a circuit for amplifying the analog image signal output from the CCD 42, and the amplified analog image signal is converted into an analog-digital signal by the A / D conversion circuit 46. This digital image signal is input to the image signal conversion circuit 47, and is simply binarized, binarized by pseudo halftone processing, or further multivalued processing.

The switch 48 is a switch for selecting and designating whether or not to perform pseudo halftone processing, and the density switch 49 is a switch for designating how much image density is processed in binarizing or multi-valued processing. Is. The density switch 49 is, for example,
It corresponds to a density lever that is operated by an operator in a copying machine and specifies a copy density.

Next, the operation principle of the image signal conversion circuit 47 according to the present invention will be described with reference to FIGS.

FIG. 4 is a diagram showing a basic circuit for binarization or multi-value conversion processing.

The memory 50 is a randomly accessible memory, and can arbitrarily read the data written at the address determined by the signal connected to the address signal line 51. For example, Intel EPROM 2732A, Static
RAM2128 etc. can be used. When using a non-volatile memory such as an EPROM or a mask ROM, a pattern described later may be written in advance as data. On the other hand, when using a volatile memory such as a static RAM, it is necessary to add hardware for writing the pattern data every time the power is turned on, but there is an advantage that the pattern can be arbitrarily changed.

A digital image signal to be processed is connected to the address signal line 51 so that the memory 50 can be addressed by the data signal line.
From 52, an image output that has been binarized or multivalued is obtained.

A case where a binarized signal is obtained will be described with reference to FIG.

The horizontal axis represents the input image data value and the vertical axis represents the output image data value. Input image data is 8 bits in binary, so 0 in decimal
A value of 0 to 255 is taken, with a value of 0 representing a white level and a value of 255 representing a black level. In the output image data, 0 is white and 1 is black.

The input image data and the address signal line 51 are connected so that the input image data value and the address of the memory 50 match,
Binarization is performed by writing 0 and 1 patterns in the memory corresponding to the address in advance.

In FIG. 5, (a) shows a dark image output, (b) shows a medium image output, and (c) shows patterns to be written in the memory to obtain a light image output.

In FIG. 5A, since the output image data value changes from 0 to 1 when the input image data value is close to 0, the ratio of value 1 (black) in the output image data increases. The image becomes dark. Similarly, the input image data value is the center value in FIG. 5 (b), and the value 255 in FIG. 5 (c).
Since the value changes from 0 to 1 at positions close to, respectively, medium image output and light image output are obtained.

FIG. 6 is an explanatory diagram for the case of quaternarization.

Input image data is binary 8 bits, output image is binary 2
This is an example of a case where bits have four values of 0, 1, 2, 3 in decimal.

(A), (b), and (c) in FIG. 6 are the cases of linear quaternaryization, respectively, and the data of the address of the memory 50 corresponding to the input image data value is 00, 01, 1 as in FIG.
You only need to write the 0 and 11 patterns. FIG. 6A shows an image output of medium density, FIG. 6B shows an image output of dark density, and FIG. 6C shows an image output of light density.

Although FIG. 6 shows an example of performing linear four-valued conversion, it is also possible to perform multi-valued conversion in consideration of visual correction, so-called γ correction, and conversion for the purpose of visual effect.

FIG. 7 is an example of such a conversion. Curve a in the figure,
The image density of the output increases with respect to the input in the order of b, c, d, and e. Therefore, if this conversion is applied to the quaternization in FIG. 6 and the data in the memory 50 is changed, there is a merit that image conversion can be achieved simultaneously with quaternization.

In addition, in the case of the EPROM 2732A of Intel, etc., since there are 12 address lines (4K bytes) and 8 data lines (8 bits), there are 4 address lines when the input image signal is 8 bits, and In the case of binarization, the data line has an excess of 7 bits. In these surplus parts, FIG.
As shown in (b) and (c), a plurality of different binarization patterns are written and selected by a select signal by an extra address line, so that the density at the time of binarization can be changed. it can. When the 2732A is used as the memory 50, 2 ⁴ × 8 = 128 kinds of binary patterns can be selected.

FIG. 8 is a diagram showing an example of specific data to be written in the memory 50. An example in which the input image signal is binarized with 8 bits is described. The 8 bits of data are divided bit by bit, and a pattern is written in each. As an example, a pattern in which the image output becomes darker from the 0th bit to the 7th bit is written. As described above, when the surplus address signal lines are used, for example, the upper 4 bits are assigned to the select signal and the lower 8 bits are assigned to the image signal, and the address lines “0000 ××××××××” and “0001 ×” are assigned. ×××
A plurality of patterns similar to those shown in FIG. 8 may be created for addresses such as "XXXXX" .... As a result, by changing the value of the select signal, the binarized output for the same image signal changes.

Next, the pseudo halftone process will be described.

FIG. 9 shows a threshold matrix (8 ×
It is an example of 8). When the input image signal is 8 bits, its value is 0 to 255. Therefore, when the input image signal is binarized compared to the input image signal, the threshold value for determining black when the value is more than that is shown in the figure. It is arranged like this. Conventionally, this matrix is written in a ROM or the like, data is read from the ROM in synchronization with an image clock and a main scanning synchronizing signal, and sequentially compared with a comparator input image signal to perform binarization by pseudo halftone.

This embodiment applies the above-described binarization and multi-value conversion method, and applies a memory 50 to each of the 64 elements of the matrix in FIG.
In addition to creating a pattern for binarization or multi-value conversion corresponding to the input image signals 0 to 255, a signal line for matrix selection is added as an address, and the pattern is arranged corresponding to the signal line so that a pseudo halftone is obtained. It is something that is processed.

FIG. 10 shows an example of specific storage contents of the memory 50.

This is a case where the input image signal is connected to the lower 8-bit address of the memory 50, and the sub-scanning address signal and the main scanning address signal are connected to the upper 6 bits as an element signal of an 8 × 8 matrix by 3 bits each. In this case, the address line is 14
Since it is a book, 16K x 8-bit EPROM Intel 27128
Etc. can be used.

For each of the matrix numbers 0 to 63 determined by the sub scanning address signal and the main scanning address signal, the image signals 0 to 255
A pattern similar to the pattern shown in FIG.

Further, since the data has 8 bits, the conversion as shown in FIG. 7 is applied to the matrix data of FIG. 9 or the input image data value, and binarized data is written for each bit. By doing so, it is possible to output a dark image and a thin image by the pseudo halftone process.

Further, similarly to the binarization described above, if the number of address signal lines of the memory 50 is increased and this is used as a select signal, a plurality of patterns can be selected. Further, when multi-value output of two or more values is required, it is configured to select several bits out of 8 bits of data.

An example of the image signal conversion circuit 47 to which the memory for the fixed threshold value processing and the pseudo halftone processing by the dither method described above is applied is shown.

FIG. 11 is a configuration example of the image signal conversion circuit 47 capable of performing pseudo halftone processing by the fixed threshold and the dither method. The dither fixed slice ROM 71 is a memory that stores both the patterns of the fixed threshold value processing and the pseudo halftone processing described above, and by switching between these, any processing is supported. A plurality of bits of data are used. For example, in the case of 8 bits, the fixed threshold CS is divided into 4 bits, and the dither DS is divided into 4 bits, and the divided bits are simultaneously output. This output is selected by the selector 72 operated by the operation of the halftone specifying switch 48, for example, 1 bit in the case of binary and 2 bits in the case of 4-value, and is output as an image. The selector 72 is
It plays the role of fixed threshold and dither selection.

The address signal given to the dither fixed slice ROM 71 must be given in synchronization with the input image data of the dither matrix element selection signal in the case of dither, and the fixed address signal must be given in the case of fixed threshold processing. It is necessary to change the way of giving an address by the element selection signal by using the dither processing. The selector 76, which operates with the halftone specifying switch 48 similarly to the selector 72, switches the address signal according to the processing. The selector 76 selects the signal of the density fine adjustment SW 73 during fixed slice, and the sub scanning counter 75 and the main scanning counter 74 during dithering.
The dither matrix selection signal of is selected.

The density fine adjustment switch 73 is for performing finer density adjustment than the density switch 49.
It is connected to the address line of the dither fixed slice ROM 71 together with the density signal from 49.

In the example of FIG. 11, even if the types of dither processing are increased, the density characteristics of the input image signal are converted according to the density signal in order to prevent the capacity of the dither and fixed slice ROM from becoming large. Is configured.

The correction ROM 70 is a memory for correcting the characteristics of the input signal as shown in FIG. Again, it is a memory as shown in FIG. 4, in which the input image signal and the density signal are connected to the address signal line, and the operation result is stored at the address determined by the image signal. For example, the input image signal is 8 bits and the output image signal is 8 bits, and data is written so that the input / output characteristics shown in FIG. 7 are obtained. In this case, the curves a to e are selected by the density signal from the density switch 49.

The dither fixed slice ROM 71 is a ROM 70 that corrects the density selection in advance.
Since it will be done in, the smaller capacity can be used.

In the above embodiment, the operator selects the halftone processing and the fixed threshold processing with the switch 48, but the image signal state is judged by the read signal, and the select signal is automatically detected according to the halftone image or the line drawing. You may make it switch to the target.
By doing so, it is possible to favorably execute the processing of the image in which the halftone image and the line drawing are mixed.

Needless to say, the image signal processing described above can be applied to a facsimile, an electronic file, etc. in addition to the digital copying machine.

〔The invention's effect〕

As described above, according to the image signal processing apparatus of the present invention, halftone processed binary or multivalued information and fixed threshold processed binary or multivalued information stored in the storage means and addressed and specified by the image signal. By making it possible to select either one of the value information, regardless of whether the input image is a halftone image or a character image, a high-quality binary or It can be converted into a multi-valued image.

Further, the present invention is to identify the halftone processed information and the fixed threshold value processed information stored in the storage means by using the digital converted image signal obtained by converting the density characteristic of the input image signal as an address signal, As a result, it becomes possible to obtain the halftone processed image and the fixed threshold value processed image whose density has been corrected to the optimum density with a low cost configuration using a memory having a relatively small memory capacity and at high speed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a conventional image signal processing circuit, and FIG.
FIG. 3 is a diagram showing the structure of a digital copying machine of an embodiment of the present invention to which the present invention is applied, FIG. 3 is a block diagram showing an example of a circuit configuration relating to read signal processing according to the embodiment of the present invention, and FIG. FIG. 5 is a diagram for explaining a basic circuit of the embodiment, FIG. 5 is a diagram showing a binarizing operation, FIG. 6 is a diagram showing a quaternarizing operation, FIG. 7 is a diagram showing an image signal correcting operation, and FIG. Is a diagram showing an example of data written in the memory, FIG. 9 is a diagram showing an example of a threshold matrix, FIG. 10 is a diagram showing another example of data written in the memory, and FIG. 11 is an image in the embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of a signal conversion circuit, in which 40 is a document, 42 is a CCD, and 46 is
Is an A / D conversion circuit, 47 is an image signal conversion circuit, 50 is a memory, 70
Is a correction ROM, 71 is a dither fixed slice ROM, and 72 and 76 are selectors.

Claims (1)

[Claims] 1. Input means for inputting an image signal, first selecting means for manually selecting the density of an output image, and conversion of density characteristics of the input image signal based on the selection by the first selecting means. A characteristic conversion means for outputting a digital converted image signal; first information that has been halftone-processed to be binary or multivalued with respect to the digital converted image signal; and fixed threshold value processing that has been binary-valued or multivalued. And a second selection unit for selecting one of the halftone-processed first information and the fixed threshold-processed second information stored in the storage unit. The first half-value-processed first information stored in the storage unit, which is addressed and specified by the digital converted image signal having the density characteristic converted by the characteristic conversion unit, and the fixed threshold value processing An image signal processing apparatus and outputs the information of one side selected by the second selection means among the second information.