JPS60125062A - Image signal processor - Google Patents

Abstract

PURPOSE:To generate plural outputs by addressing a memory which is stored with a binary or many-valued information for an image signal by an image signal processor with the image signal. CONSTITUTION:The image signal processor converts the image signal into a binary signal or many-valued signal more than it, input image data and an address signal line 51 are so connected that the input image data value coincides with the address of the memory 50, and plural kinds of ''0'' and ''1'' pattern are written in the memory corresponding to addresses to perform the binary coding. Then a desired output signal is selected among plural outputs.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an image signal processing device that performs binarization or higher multivalue conversion on an image signal in a digital copying machine, an electronic file, or the like.

Conventionally, this type of circuit consists of a comparison circuit that compares an image signal and a reference signal, and by making the reference signal value variable, the density of the output image can be adjusted, and by synchronizing the reference signal value with the image signal. Pseudo-halftone processing was performed by changing according to a predetermined rule.

FIG. 1 is a block diagram showing an example of the conventional image signal processing circuit.

Blocks 1.2 surrounded by broken lines are blocks for binarization, and by increasing the number of these blocks, processing corresponding to multivalue, for example, hexanarization and quaternization is performed. Comparison circuit 1
0.20 compares the multi-value image input signal with the multi-value reference signal output from the selector 11.21, performs binarization, and outputs the comparison result.

The selector 11.21 is a switching circuit for switching between a fixed value reference signal and a pseudo halftone processing reference signal using a selection signal such as a switch. The latch circuits 13 and 23 are circuits for generating fixed-value reference signals for comparison, and set the slice level for binarization using, for example, a CPU or a switch.

Dither n0M12, 22 is a reference signal for pseudo-halftone processing; preferably, it is a memory storing a plurality of patterns, and a predetermined pattern (dither number turn) is stored in advance. The main scanning counter 30 is a counter that operates in synchronization with the image signals to be compared and synchronizes in the main scanning direction. The latch circuit 62 is fROM12.2
This is a circuit for selecting one of the plurality of turns in step 2, depending on the image quality, for example.

According to the circuit configuration shown in FIG.
(1, 6 in the case of 4 values, etc.), which has the drawback of increasing the scale of the circuit.

In addition, when converting a multi-level signal such as Do, 01.10.11 in binary numbers, the 2 output from the above block is
Another drawback is that it is impractical because the only way to deal with it is to encode the digitized image output, which requires a very large-scale circuit.

Furthermore, when using a comparator circuit to handle an image signal with a large amount of data such as 14 bits or 16 bits, the circuits are connected in cascade and delay time is added, which is disadvantageous for high-speed processing. To further address this,
It is conceivable to use high-speed logic elements, but this also has the disadvantage of being extremely expensive.

In view of the above-mentioned drawbacks, the present invention aims to provide an image signal processing device that can easily handle multi-value processing without using a comparison circuit, is low-cost, and can be increased in speed. By addressing a memory that stores multiple binary or higher multilevel information for an image signal with the image signal, it is possible to output multiple binary or higher multilevel outputs of the image signal. An object of the present invention is to provide an image signal processing device.

Hereinafter, the present invention will be explained in more detail using a 0 Wtz diagram. It is a diagram showing the structure of a digital copying machine to which the present invention is applied. A is 1! It'j4. A reader that photoelectrically converts and reads the original to be read. B is the L! that is output from reader A.
Image recording is performed on the recording material based on the Iiv/# signal.
Now printer. Reader A (C) is placed face down on the original glass 83 to be copied, and its placement is on the back left side when viewed from the front.The original is held down on the original glass by the original cover 84. The document is illuminated by a fluorescent lamp 82, and an optical path is formed such that the reflected light is focused onto the CCL 81 via mirrors 85, 87 and a lens 86. The mirror 8 is moved at a relative speed between the mirror 8f and the mirror 85d2:l. This optical unit is operated at a constant speed while applying PLL by an iJC servo motor.
It is ec. The resolution in this sub-scanning direction is 16 Lines.
The size of manuscripts that can be processed is A5 to A3, w, and the orientation of the manuscript is A5. B5. Each size of A4 is vertical @14, and B4. The A3 size is a yuzu holder.

Next, in the main scanning direction, the main rectangular eclipse rlJ has a maximum horizontal width of A4 size 297-, depending on the above-mentioned document placement orientation. In order to resolve this with 16pel/IIg, the number of bits of CCL)81 is 4752 (==:29
7.times.16) bits required.Next, referring to FIG. 2, the overview of printer B placed below reader A will be explained. The image No. 4d processed by the reader A and made into bit serial is input to the laser scanning unit 105 of the printer B. This unit consists of a semiconductor laser, a collimator lens, a single-turn polygonal mirror, and a )'tJ lens.

The original character is made up of threads to compensate for the fall. The ghost signal from the reader is applied to a semiconductor laser, which undergoes electrical-to-optical conversion.The scattered laser light is made into parallel light by a collimator lens, and is irradiated onto a polyhedron Mi2- which rotates at high speed.The laser light is thereby exposed to light. scan body 88; The rotational speed of this polyhedral mirror is 2.60 Orpm, and during scanning it is approximately 400u+, and the effective image is 29mm in width on A4 paper.
It is 7m. Therefore, the signal frequency applied to the semiconductor laser at this time is about 20 MHz (Nltl). The laser beam from this unit passes through the mirror 104 to the photoreceptor 88.
is incident on the

For example, the photoreceptor 88 is made up of three layers: a conductive layer, a photosensitive layer, and an insulating layer. Accordingly, process components are arranged 11 that make image formation a single process. 89i
j front turtle remover, 9o mouth 11 lamp, 91 bar next 'R7
m device, 92 tit: secondary band 1Nim, 93 is front exposure 2 fins, 194 is developing device, 95 is paper feed cassette,
96#'i pongee paper roller, 97 branch paper feed guide, 98 is registration roller, 99 is transfer? l) Heavy equipment, lo.

is a separation roller, lol is a transport kite, 102iJ fixing device, and 103 is a tray. The speed of the photoreceptor 88 and the conveyance system is the same as the forward path of the beam gauge A (180 W/sec).

Therefore, the speed when copying using the combination of reader A and printer B is 30 A4 sheets/minute. In addition, G/R B uses a separating belt on the front side to separate the copy paper that is in close contact with the photosensitive drum 88, but because of this, the wA image of the belt mountain portion is missing. If a signal is added to that amount, the toner will be developed and the separation belt will be stained by the toner, which will also stain subsequent sheets of paper. Belt height 8II1
1 is set to cut the video electrical signal of the print output. Also, if toner adheres to the leading edge of the copy paper, when it is fixed, it will wrap around the foot roller and cause a jam, so an electric signal must be sent to the reader A side to prevent the toner from adhering to the leading edge of the paper. It's being cut.

The copying device in this example is +1! ! It has intelligence such as 1-image editing, but this intelligence is on the reader A side and C
The signal read by the CD81 is processed, and in any case at the stage of outputting from reader A,
- A constant speed signal is output by the number of foot bits (4752). As for the intelligence function, 05
→Enlarge/reduce to any magnification of 2,0x drive,
It has a trimming function that extracts an image only from a designated area, a movement function that moves the trimmed image to an arbitrary location on the copy paper, and a function that moves the original placed on the original table. In addition, it has a pseudo-halftone processing function using one-key specified digital processing, an AE function, and a crease function that combines these individual intelligent functions.

FIG. 3 is a block diagram showing an example of a circuit configuration related to Ray 1 processing in reader A. Original 4° line light source,
For example, the document image is illuminated by a mirror lamp and an optical lens 41
C:L:
imaged on l). The scanning direction 40 is electrically scanned in the reading scanning direction (main scanning direction) of the ccD 42, and the scanning position on the document is moved (regular scanning*) by a sub-scanning thread (not shown). 4o, a forward and backward scan 6 is performed in the illustrated Th1 scanning direction, and the entire image is read.

The COD driver 43 is a circuit that performs frequency division processing on the oscillation output of the oscillation circuit 44, etc., to generate the clock timing of the CCD 42. In addition, the CCI) driver 43 is the CCD4
A clock (iLll clock) corresponding to pixel readout of No. 2 and a synchronization signal +j (main scan synchronization signal) for each main scan l input are inputted for tLl.

The amplification circuit 45 is a circuit for amplifying the analog image (N number) outputted from the CCD 42, and the amplified analog image signal is converted into an analog-digital signal by the A/D transformation circuit 46. The image signal is input to the image signal conversion circuit 47, where it is subjected to simple binarization, binarization by pseudo-halftone processing, or more multi-value processing.

The switch 4B is a switch for selecting and specifying whether or not to perform pseudo halftone processing, and the -j degree switch 49ti
This is a switch for specifying the degree of obscurity to be processed during Z-value conversion or multi-value conversion. Concentration switch 49
corresponds, for example, to a density lever operated by an operator in a copying machine to specify the copy density.

Next, the operating principle of the image signal conversion circuit 47 according to the present invention will be explained using FIGS. 4 to 10.

! Diagram R4 is a diagram showing a basic circuit for 2+ conversion or multi-value conversion processing.

Memory 50 is a randomly accessible memory;
Data written at an address determined by a signal connected to address signal &151 can be read out arbitrarily. For example, 1 Intel's EPR (JM 2
'732A % Static i (AM2128 etc. can be used. EPROM, mask) When using the LOM hemorrhoid non-capturing memory, please write the pattern described later as data in advance. On the other hand, when using a static memory such as static RAM, it is necessary to add hardware to write pattern data every time the power is turned on, but the advantage is that the pattern can be sewn arbitrarily. occurs.

A digital image signal to be processed is connected to the address signal N51, and the memory 50 is addressed thereby to obtain a binary or multivalued I# image output from the data signal line 52.

Using the M5 diagram, the case of obtaining a binary signal will be explained.

The horizontal axis shows input image data values, and the vertical axis shows output image data values. The input l1iII image data is 8 bits in binary, and therefore has values from 0 to 255 in lO base.

It is assumed that 255 represents the white level and 255 represents the black level.

Output ll! In the Ii image data, 0 is white and l is black.

The human image data and the address signal i51 are connected so that the input image data value and the address of the memory 50 match, and the memory corresponding to that address is preset with 0, 1.
By writing the pattern in advance, binarization is performed.

In Fig. 5, the patterns to be written to the memory are shown to obtain a medium image output with a high density, and (C) to obtain an image output with a light density. ing.

Figure 5 (in aJ, when the input image data value is close to the value O, the output image data value changes from the value 0 to the value l, so the proportion of the value l (black) in the output image data Similarly, in Fig. 5(b), the input image data dispersion is the center value, and in Fig. 5(C), it is the value 2.
55, the value changes from the value 0 to the value lK at each point.
Therefore, the image output is medium and the light -1aIl image output respectively. ◎ This is an explanatory diagram for the case of M6 image data and 4 images. 〇 The input image data is 2 copies of 8 bits, and the output image is binary and 2 bits, i.e.
This is the case when the valence is Ot l * 2 e 3 in the lO base.

(aJ, (b) l (C) in FIG. 6 are the cases where linear 4-value conversion is performed, and as in FIG. 5, 0 is added to the data at the address of the memory 50 corresponding to the human car image data value.
It is good to write patterns of 0.01, 10, and 11. FIG. 6(a) shows an image output with a medium density, (b) an image output with a high density, and FIG. 6(C) shows an image output with a dark density.

w, In Figure 6, V3 shows an example of linear 4-value conversion, but it is also possible to perform multi-value conversion by adding visual correction, so-called γ correction, and conversion for visual effects. It is.

FIG. 1 is an example of such a transformation. Song IM a in the diagram
The output image density increases in the order of e b e c e d w e compared to human power. Therefore, this conversion can be expressed as 4 in Figure 6.
If you change the data in the memory 5o to adapt to the value conversion, you can convert it to 4i and get iI at the same time! There is an advantage that the Ii image conversion can also be achieved.

In addition, in the case of Intel's EPItOM2732A mentioned above, there are 12 address lines (4 bytes) and 8 data lines.
(8 bits), so if the input 1llIl image signal is 8 bits, there will be 4 address lines, and in the case of binarization, there will be 7 extra data lines. I'm busy stacking up multiple different two-domain patterns like (c>) and selecting them with Select No. 44 using the extra address line.
It becomes possible to take many turns to improve the density during binarization.

5 is a diagram illustrating an example of specific data to be written into the iris 8 diagram line memory 50. FIG. This is an example in which the input [1!1m signal is binarized with 8 bits. The 8-bit data is divided into bits and a pattern is written into each bit. 0
As an example, a pattern is shown in which the output becomes darker from the 7th bit to the 7th bit. As mentioned above, when using extra address signal lines, for example, use the upper 4 bits as the select signal and the lower 8 bits as the image signal.
XXXXXJI r.

ooxxxxxxxxxxx''----5h7 Create multiple 1IIb patterns similar to those in Figure 8 for the DoVs. The binarized output for the image signal changes.

Next, pseudo halftone processing will be explained.

#I9 figure is a threshold matrix (8
This is an example of X8). When the input image signal is 8 bits, its value is 0 to 255, so when comparing it with the input w4 image signal and binarizing it, if the value is 1 or more, it is determined to be a car. The dark values are arranged in rows as shown in the figure. Conventionally, this matrix is written in a LOM, etc., and the data is read from the i'tOM in synchronization with the image clock and main scanning synchronization signal, and is sequentially compared with the human image signal using a comparator to generate pseudo halftones. Binarization was performed.

The present embodiment applies the above-mentioned binarization and multi-iG counting method, and stores two signals corresponding to the input 1II image signals 0 to 255 in the memory 50 for each of the 64 elements of the matrix in FIG.
Create a pattern for value conversion or multivalue conversion, and add line 1d of matrix selection as an address.
By arranging them in correspondence with the signal lines, pseudo halftone processing is performed.

FIG. 1O shows a specific example of the contents stored in the menu 50.

Input the human image signal to the first 8-bit address of the memory 50.
This is a case where three bits each of a sub-scanning address signal and a main-scanning address No. 54 are connected to the upper six bits as element signals of an 8×8 matrix.

In this case, there will be 14 jurisdictional addresses, so 16 x 8
Bit EP) LOM Intel 2712E] etc. can be used.

For each of matrix numbers 0 to 63 determined by the sub-scanning address signal and main-scanning address signal, image signals 0 to 2
All you have to do is write a pattern similar to the pattern shown in FIG. 8 for 55.

Also, since there are 8 bits of data, the conversion shown in Fig. 7 is applied to the matrix data shown in Fig. 9, or the input mta data value is sieved and binarized data is written for each bit. . By doing this, you can achieve a dark color due to pseudo-halftone processing! Il image output and light image output become possible.

Further, in the same manner as in the binarization described above, by increasing the number of address signal lines of the memory 50 and using this n as a select signal, it becomes possible to select a plurality of patterns. In addition, if multi-value output of two or more values is required, configure the system so that several bits out of 8 bits of data are selected. 〇Memory for pseudo-halftone processing using the fixed threshold processing and dither method described above is provided. Applied I
An example of the # signal 4j conversion circuit 47 is shown.

Diagram 11 shows an example of the configuration of a circuit 47 that performs pseudo-halftone processing using a fixed hook value and a dither method. The dither fixed slice xttjMeo is a memory that stores both the fixed threshold value processing and the pseudo medium 1tl tone processing described above, and also corresponds to the processing of the rotation ψ deviation depending on the switching process. Data uses multiple bits,
For example, in the case of 8 bits, set 4 bits to C8 for fixed threshold value,
It is divided into 4 bits and used as a dither DS, and outputs 8 bits at the same time. This output is the intermediate designated switch 4.
For example, in the case of binary data, 1 bit is selected, and in the case of 4 data, 2 bits are selected by the selector 61 that performs the select operation by the operation of 8.
! ! It becomes a li image output. Selector 61 #i, fixed threshold;
It plays the role of dither selection and density selection corresponding to the density switch 49 in FIG.

In the example of FIG. 11, the density signal from the density switch 49 is directly connected to the address signal of the dither fixed slice xROMeo as described above.

Dither Fixed Slice) The address signal given to the LOM 60 must be a dither matrix element selection signal synchronized with the input image data in the case of dithering, and a fixed address signal in the case of fixed threshold processing. It is necessary to change the way addresses are given depending on the element selection signal between fixed slice processing and dither processing.The selector 65, which is operated by the halftone designation switch 48 like the selector 61, switches this address signal according to the processing. It is. Selector 65 Mori, density fine adjustment 5 when fixed slice
Select the signal W62 and use the sub-scanning counter 6 during dithering.
3. Select the dither matrix selection signal of the main scanner 4.0 Note that the density fine adjustment switch 62 allows even finer density #! than the density switch 49. It is connected to the address line of the dither fixed slice ROM 60 together with the density No. 16 from the density switch 49.

In the example of FIG. 11, when the types of dither processing are increased with ψ, the 8 blocks of LOM (dither, fixed slice) become large. Therefore, the embodiment shown in FIG. 12 is configured to first perform image processing using a density signal using the correction shown in FIG.

The correction ROM F0 is a memory for correcting the characteristics of the input signal as shown in FIG. It is a mesori as shown in Fig. 1g4, and the manually generated image signal and the density signal are connected to the address I@ line, and the result of the calculation is stored at the address determined by the - signal.

Write the data. In this case, selection of song B-6 is made by the density (r1) from the density switch 49.

The dither fixed slice ttoNt7x is a memory similar to the dither fixed slice (LOM) shown in FIG.

Selector 72, ili[5W73, main scanning counter 74
, sub-scanning carantuff 5, and selector mallo are the first
These are similar to 61162.63 and 64.65 in Figure 1.

FIG. 13 shows another embodiment that has a function to satisfactorily reproduce the original image by varying the binarization or higher multi-value conversion operation depending on the original image density, for example, the original level of II'i original. 1
1! This is an example of the I signal conversion circuit 4).

In Fig. 13, the same mechanisms as in Fig. 11 are given the same reference numerals. o The difference from Fig. 11 is 11Nk@m.
In place of the switch 62, the image signal from the A/D conversion circuit 46 is input to the 0 density detector 66, which is connected to the selector 650 manually. Then, the peak value (white peak and/or black peak) of each line of this image signal is detected, and based on this, the content of the image signal of each line is determined, and 11! Detection (No. 71 is input to the selector 65) to obtain a binary or multivalued output according to the Ii image signal.

When fixed threshold processing is selected by the select signal,
The selector 65 selects the detection (it number) from the density detector 66 and outputs this detection signal to the address line as the select signal of the dither identification slice RUM60.Therefore, as described above, the dither fixed slice) LOM60 selects this address. I at the detection signal on the line! ]! Appropriate binary or more multi-value data for the image signal is selected. Note that the density detector 66 may form a detection signal based on the peak value of MW & 9in, or it may perform a preliminary scan of the original before actually reading the original, and detect the image area on the entire surface of the original. You can also form a detection signal based on
In the history, the concentration fine adjustment switch 62 in FIG. 11 and the 13th
The density detector 66 shown in the figure is also provided and can be configured to be selectable as required.According to this, binary or higher multilevel conversion suitable for m-images can be carried out very well. It is.

In the above embodiments, the selection between halftone processing and fixed threshold processing was made by the operator using the switch 48.
Read the image state (tK @) and automatically switch between 1 out of 1 III sea bream L!ll image and line drawing. It can also process images containing line drawings well.

In addition to digital copiers, facsimile machines, electronic files, etc. can also be used as described above. Needless to say, II image fa processing can be applied.

As explained above, according to the invention, the binary or higher multivalue operation of the III image 1d can be achieved with a simple configuration, at low cost, and at high speed. This improves the efficiency of Jl image processing.

[Brief explanation of drawings]

Figure 1 shows the configuration of a conventional image signal processing circuit, Figure 2 shows the configuration of a conventional image signal processing circuit.
The figure shows the structure of a digital copying machine to which the present invention is applied;
FIG. 3 is a block diagram showing an example of a circuit configuration related to read signal processing according to the present invention, FIG. 4 is a diagram explaining the basic circuit of the present invention, FIG. 5 is a diagram showing #'i binarization operation, and FIG. The diagram is 4
7 is a diagram showing the image signal correction operation, FIG. 8 is a diagram showing an example of data written to the memory, and FIG. 9 is a diagram showing the value conversion operation.
The figure shows an example of a threshold value matrix, the ilO diagram shows another example of data written to the memory, and FIGS. In the block diagram shown, 40 is the manuscript, 42 is the CCLI. 46 is the Nφ variable circuit 4F is the drawing variable circuit, 50Fi
Mesori, 60 people 71 are dither fixed slice ILOM,
61, 65, 72 and 76 are selectors. 3E fixed "To complete 1-'L"

Claims (1)

[Claims] (1) Binarize the image signal by addressing the memory that stores multiple values of binary or higher multivalue information for the image signal with the image signal, or (1) Output multiple values of higher multivalue output. An image signal processing device that is characterized by eight things that are possible. Q) An image signal according to claim (1), characterized in that it has a selection means for selecting either a plurality of binary outputs or a multilevel output output from the memory. Processing equipment. 6) In claim (1), there are two or more
An image signal processing device characterized in that multivalued information of a value or more is stored at the same address.