JPS60125043A - Modem signal obtaining system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates generally to digital modems and, more particularly, to a method for rapid modem carrier acquisition and synchronization. A modem, or modem, is a device commonly used for transmitting digital data signals on telephone lines and other communication links. On the transmitting side of the communication link, the modem modulates a high frequency carrier signal according to a specific modulation scheme. Basically, the data signal to be transmitted is encoded as a change in frequency, amplitude or phase angle of a carrier signal. Another one on the receiving side
Two modems demodulate this carrier signal to recreate the transmitted data.

Because the transmitting and receiving ends of a communications link are typically located at remote locations from each other, the receiving modem must be precisely synchronized with the incoming signal before it can be accurately demodulated.

Various synchronization and timing schemes have been developed in the past. However, the present invention relates to modem operation according to the type of transmission scheme established by the proposed United States Federal Standard FED-3TD-1007. This standard, which is widely adopted by modem manufacturers, is
600 bits or 9.6. has established a signal format for transmission at speeds of bps. This standard also defines a preamble format for signals, and the present invention is primarily concerned with this preamble format.

This preamble is 800 (automatic gain control) and −
The synchronization time 128 is - i.e. 55 m5 (milliseconds), followed by the balancer adjustment time 584 - i.e. 160 m.
Contains 5i. - Synchronization time, as its name suggests, precisely synchronizes the receiving modem to one speed of the incoming signal. The adjustment time is used to adjust the receiving modem's adaptive balance device to properly respond to the incoming signal. Within this adjustment time, various types of adaptive balancers /
4' parameter is adjusted to optimize the performance of demodulation of the data-carrying signal following the preamble.

The present invention is concerned with two fundamental problems that arise in the operation of modems according to the same type of transmission standard as the FED-8TD-1007. The first problem concerns the use of this standard in what are known as half-duplex systems. In this operation method, 1
Two communication links are used for transmission in both directions, but never at the same time. The proposed standard was intended for use in transmitting relatively large amounts of data in one direction. If two-way transmission is required, one or two transmission links may be used in each direction; however, this standard It can be applied.

One such application is the transmission of digitized spoken data in telephone communications.

The use of digital signals to transmit spoken language facilitates data scrambling for safety purposes. Even when safety is not a critical issue, digitized spoken signals can be more easily compressed for better utilization of communication links and are more easily stored in complex communication networks. This makes it easier to switch from one line to another. The digitized spoken word signal is
Although it can be transmitted in full-duplex mode as appropriate using separate communication links for transmission rounding in each direction, the ability to use half-duplex mode allows for 509G line cost savings.

A practical limitation of using half-duplex for speech transmission is that the transmitting modem must change line direction to begin operating as a receiving modem and vice versa. It takes time. If the time required to resynchronize the receiving modem is unreasonably long, an unacceptable delay will occur between the phases of the speaker and listener sides of the telephone conversation.

According to this standard, signals are transmitted using rectangular amplitude modulation (QAM). In this method, the amplitude and relative phase angle of the carrier signal are modulated. In one synchronization part of the preamble, two consecutive signal phasors
) are transmitted alternately, and the two 7 Acers have different amplitudes and phase angles.

During this synchronization phase, a typical receiving modem will have at least three adaptive control loops active: a phase-locked loop, an automatic gain control loop, and a synchronization subloop. Because of the alternating phase and amplitude shifts of the incoming phasers, the three control loops tend to interact unduly and also tend to slow down the acquisition process. These conventional methods result in unacceptably delayed acquisition times when switching the transmission direction in half-duplex mode. The second major problem with this Federal Standard is that the balancing device is The purpose is to timely detect the start of the adjustment time. It is important that the receiving modem be able to accurately determine the end of the Solenble baud synchronization time and the beginning of the balancer adjustment time. The simplest and most economical way to tune a modem adaptive balancer is to generate the necessary reference pattern that is synchronized with the received tuning pattern. However, in order to do this, it is necessary to know exactly when the adjustment time starts. Failure to obtain accurate synchronization between the received and next-adjusted parent turn and the locally generated reference or turn may result in poor performance or to compensate for any resulting timing inaccuracies. requires a more complex and expensive balancing device. The only other alternative is to try this with some timing assumptions,
The method is to find the best fit for the start of the adjustment time. This method also involves extra cost and complexity.

It will be appreciated from the foregoing that significant improvements are needed in the field of modems for use with transmission standards of the same type as FED-STD-1007.

In particular, what is needed is the ability for this transmission standard to use baud synchronization time for the transmission of spoken language in a half-duplex manner! This is a method of shortening it to the length of wheat so that it is acceptable. What is further needed is a method for accurately detecting the beginning of the balancing device adjustment time that preambles the two signals before transmitting the data. The present invention satisfies these two needs.

The present invention relates to a modem apparatus and method, which determines the speed of acquisition of incoming signals in two important respects: - an additional improvement in at least one of two important points: the synchronization and the detection of the beginning of the adjustment time of the balancer; According to the invention, the receiving modem selects one of two alternating phasers. - a rounding means for determining whether it is being received by the modem during the synchronization time and a ninth means for calculating the phase error signal between the phase angle of the signal being received and the theoretical phase angle of the receiving phaser; and the means of
and a phase lockout for calculating sine and cosine values from this phase error signal for use in demodulating the incoming signal.
The means for determining which phasar is being received includes an arctangent circuit, a delay circuit and two subtraction circuits.The arctangent circuit calculates the phase angle of the received phasar from a pair of complex coordinates. Calculate.

This phase angle includes an error signal component, and the delay circuit
is delayed by one interval and sent in delayed and undelayed form to one of the subtraction circuits.

The phase difference thus obtained represents the change in phase angle during the last interval and is compared with a constant angle in the other subtraction circuit. If the result of subtracting the fixed angle from the phase difference is positive, one of the two predicted phasers is displayed; if the result is negative, the other of the predicted phasers is displayed. The displayed facer angle is then subtracted from the originally calculated angle derived from the arctangent circuit, and the result is the error signal component for entry into the phase-lock Luso.

According to another feature of the invention, a prediction circuit is coupled to the phase locus to compensate for modem time delays. The prediction circuit includes a time delay circuit which provides a delay approximately half the time delay inherent in the modem's adaptive balancer.

Another important area of improvement provided by the present invention is in the generation of modem timing signals in detecting the beginning of the balancer adjustment time.

In this respect, the device of the invention is approximately balanced within the interval 1-! ! adjustment sequence detection means for detecting the start of the adjustment sequence of the modem; the essence of this detection means is a complex match filter coupled to accept the complex phaser signal from the modem; An envelope detector coupled to the side. Since the first 7 gos of the adjustment sequence are equal to the backlighting of the signal preamble by the last 7 of the synchronization part, the match filter has a deep null in its output characteristics in the transmission of the preamble to the adjustment sequence. can be designed to represent

The main criterion for detecting the start of the adjustment sequence is that the output of the match filter falls below a selected minimum threshold. This minimum threshold is determined by a second envelope detector to which the same signal as the match filter is input, and a low-9 filter coupled to receive the signal from the second envelope detector. . This low-9 filter provides a signal proportional to the average value of the demodulated signal. Further, by multiplying this average value by a predetermined two-actor, the minimum threshold value can be obtained.

In other words, this minimum threshold is a selected fraction of the average signal level.It is desirable to apply two other threshold tests to the output of the match filter to avoid false indications of the beginning of the adjustment sequence. . First, the output of the match filter is delayed, smoothed, and compared to the product of the average signal level and another preselected factor. If the delayed smooth output of the match filter does not exceed this product, no change will be detected. Finally, the average signal level must be above a preselected predetermined level in order for a transition to be detected. This prevents electrical signals from interfering with the detection circuitry when no signal is present. The predetermined threshold is set above the expected average noise level. By ANDing the results of the three tests of this variation, the desired timing signal is obtained. The availability of this timing signal greatly simplifies subsequent balancing device adjustments. This is because in this case there is no uncertainty as to the correct synchronization of the coordination signal and the locally generated reference pattern.

The method described above for generating this modem timing signal has the advantage that one detects the start of a regulation sequence within one interval. Furthermore, the method is substantially independent of the characteristics of the communication channel and the phase and amplitude of the incoming signal.

It will be appreciated from the above description that the present invention represents a significant advance in the field of modems.

In particular, the improved modem of the present invention? - a device for more quickly acquiring an input signal by rapidly identifying phasers received within a synchronization time, and means for detecting the start of a balancer adjustment sequence within one interval; bl. Other aspects and advantages of the invention will become apparent from the following more detailed description, taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in the drawings for purposes of illustration, the present invention essentially relates to improvements in modems.

More particularly, the present invention relates to more rapid synchronization of receiving modems due to incoming speed and more timely detection of the beginning of an incoming signal balancer adjustment sequence. It is something.

According to the background, the upper part of FIG. 4 shows the basic structure of the receiving modem. This structure consists of 10 automatic gain control (800) circuits, 12 heterodyne circuits, and a low A4
It includes a filter 14, an adaptive balance device 16, a demodulator 18, and a phase-locked loop 2°. The incoming signal is sent to AGC circuit 10 through line 22. Its output is sent to the heterodyne circuit 12 over line 24 and provides a baseband output signal on line 26. This output signal is passed through a filter 14 to a low-pass F wave tL, and the F-wave output of the line 28 is sent to an adaptive balance device 16, and the output from this device is transmitted to a demodulator 18 through a line 30. Ru. Output data from modem 18 is available on line 32. In response to the timing of the demodulated signal input on line 34, phase-locked loop 20 generates a signal on line 30 for transmission to heterodyne line 12, effectively locking the demodulation process to the frequency of the incoming signal carrier.

Before data is transmitted to the modem and properly read, a signal preamble is first transmitted and used for synchronization and timing purposes. Figure 1 shows the United States Federal Standard FED-
1 shows a modem signal preamble scheme according to sTD-1007. The preamble consists of a first segment consisting of a dead time of 20 milliseconds (ms), a second segment of 53m5 for AGC and no synchronization, a third segment of 160m5 for balancer adjustment, and a third segment of 160m5 for scramble synchronization. It can be seen that it has a fourth segment of 2 oms. The invention relates only to the second segment for synchronization and the third segment for the adjustment of the balance device.

128M-with spacing? - Alternating phasers of the type denoted A and B are transmitted in the 28th factor during one synchronization. Each phaser indicates the amplitude and relative phase angle of the carrier signal transmitted during the data interval. It can be seen that facer A has an angle of 180° and facer B has an angle of 31-5°. Unfortunately, AGC circuit 10 and phase-locked loop 20 cannot do this because the modem must respond quickly to the alternating sequence of A and 8 phasers in order to synchronize with the data rate of the incoming signal. It tends to interact with one synchronization process and delay its completion. - Slow synchronization speeds are of little concern when transmitting large amounts of data in one direction, but when transmitting digitized spoken word signals in half-duplex mode, This is extremely important when using the modem for other purposes. Acquisition time is extremely important in such cases. This is because an unreasonably long acquisition time will result in an unacceptable delay between transmitted and received data.

One important aspect of the invention is that, as shown in FIG. 3, means are provided for determining which phaser A or B is being received by the modem. More specifically, the means for identifying the male-synchronized phaser is the arctangent circuit 40, ? - Interval delay circuit 42.
Three subtraction circuits 44, 46 and 48 and an addition logic circuit.

It is equipped with 50. A complex signal indicative of the latest phaser position and magnitude is extracted from the adaptive balancer through line 52 and sent to arctangent circuit 40.
provides the corresponding angle value on line 54 and sends it to delay circuit 42. This angle value is also passed through line 56 to subtraction circuit 44.
is sent to the positive input side of the subtraction circuit 48 through line 58.
is sent to the positive input side of The output of the delay circuit 42 is connected to the line 60
and is sent to the subtraction circuit 44 as a negative input.

Subtraction circuit 44 operates to provide a corresponding positive result on line 62. Thus, if the result of the subtraction, i.e. the change in phase angle from the previous interval to the current interval, is, for example, -135°, this is expressed as the corresponding positive angle +225°. . In other words, the subtraction circuit 44 performs calculations based on 360 degrees.

This positive phase angle difference is transferred to the second subtraction circuit 4 by line 62.
6. The other input of this subtraction circuit 46 is 64
As shown in , it is a value of 180°. The result on line 66 will be positive or negative depending on whether Phaser A or Day is currently being received. The logic circuit 50 is at an angle of 180° of facer A or facer B.
Either one of the angles of 515° is selected as the output to the line 68. The selected value is subtracted from the actually received phase angle by a third subtraction circuit 48. Subtraction circuit 48 sends the error signal from circuit @70 to phase locked loop 20.

For example, if the line 540 angle signal is 180° plus a small error component, the angle beyond line 60 will be 315° plus this error component.

The result of the subtraction in the subtraction circuit 44 is 225° plus an error component. Subtracting 180° gives a result of 45° plus the error component, which indicates that Acer^ has been selected. Alternatively, if the angle signal on line 54 is about 315° and the angle signal on line 60 is about 180°, the result of the subtraction in subtraction circuit 44 is about 13
It will be 5°. Subtracting 180° gives a result of approximately -45°, indicating that phaser-8 is selected.

Phase-locked loop 20, which may be of any suitable design as shown in detail in FIG. 3, provides a set of sine and cosine signals to heterodyne circuit 12 over line 72. The phase lock loop in Figure 3 is line 70.
A first aggregation circuit 80 for aggregating the most recent error signals of , and a delayed version of the output of this aggregation circuit.

The output of this summing circuit 80 is multiplied by a zf parameter C1 in a multiplier 82 and sent as an input to a second summing circuit 84. The error signal on the line 70 is also multiplied by a counter meter C2 in the multiplier 86 and input to the second totalizing circuit 84. The output of this aggregation circuit 84 is connected to a prediction circuit 90 through a line 88.

The output of the prediction circuit is passed through a line 92, multiplied by a factor C3 in a multiplier 93, and then sent to a totalization circuit 84 as a third input. A constant is added to the output of the second aggregation circuit 84 in a third aggregation circuit 94, and then an accumulation circuit 96
and then enters hookup circuit 98 to provide sine and cosine values for transmission to heterodyne circuit 12.

The prediction circuit 90 is of a conventional design, and the delay circuit 10
0, a subtraction circuit 102, a totalization circuit 104, and a data interval delay circuit 106. The input of line 88 is input to the positive side of delay circuit 1110 and subtraction circuit 102;
The negative input of the subtraction circuit 102 is the output of the delay circuit 100.
obtained from.

The output of subtraction circuit 102 is sent to aggregation circuit 104, and the output of aggregation circuit 104 is then sent to output line 92 and ? - coupled to the interval delay circuit 106; Delay circuit 106 provides a second input to aggregation circuit 104. The purpose of prediction circuit 90 is to compensate for relatively long delays within the modem, particularly in adaptive balance device 16.

As shown in FIGS. 4-6, detection of the beginning of the balancing device adjustment sequence is another important feature of the invention. As shown in FIG. 4, the basic element of this adjustment sequence detector is a complex match filter 110. This filter 110 has seven stages, and when the adjustment sequence starts, its output characteristic sharply represents O. The solution used for this feature of the invention is such that the first seven go's of the adjustment sequence are equal to the backlighting of the preamble go synchronization time of the signal, and the last seven go's of the signal preamble go synchronization time are equal to b. Take advantage of facts.

Complex match filter 110 may be provided in any suitable form. One of these is shown in detail in FIG. 5, for example. Basically, this match filter is a complex number ix
This is a shift register for inputting +jy. In each stage of the seven-stage filter, this complex quantity is multiplied by a complex factor u-1-JV. The real component of this output is derived from the sum of the real components of the multiplication at each stage. Similarly, the imaginary component of this output is obtained by summing the imaginary components of the multiplications at each stage.

The input of this match filter is led from the output of the modem's low-pass filter 14 through line 1]2. The output of the match filter 110 passes through an envelope detector 114 and is then sent to a subtraction circuit 116. This match filter 1
10, there is another envelope detector 118 and a low pass filter 120. Its purpose is to determine the average amplitude of the signal sent to the match filter.

To determine the start of the adjustment sequence, the output of the match filter 11 (ll) is set to a fraction of the average signal level, e.g. 0.6
compared to This portion used is sent to the multiplier 122) determined by the analog meter C1 -5 and the result is sent to the other input of the subtractor 116. - The method of detecting the displacement between the synchronization time and the adjustment sequence of the preamble can be best understood from FIG. In the Kerr synchronization part of the preamble the output of the match filter accumulates heavily and reaches a stable state after 7-. When the 7 in the shift register of the match filter goes in and out alternately between the inside and outside of the phase depending on one reference, this output moves up and down irregularly with small undulations. In reality, the amplitude of this undulation is reduced by the action of the communication channel.

Communication channels tend to obscure this go, so the received signal does not exactly match the reference.

On the preamble side? - When the synchronization part and the adjustment part of the balancer begin, the signal modulation pattern is FED-5TD-1
007 indicates a phase shift of 180° according to the code sequence defined by 007. When the phase moves in the opposite direction, the contribution from the new GA in the first stage of the matched filter's shift register cancels the contribution from GA in the last stage of the matched filter's shift register. As a result, the magnitude of the output of the match filter drops rapidly as shown in FIG. 2 of changes upon change to adjustment sequence
The contributions due to both sides cancel out and the output of the match filter exhibits a deep null that falls below the threshold set by subtraction circuit 116.

Two other threshold tests are performed to prevent misrepresentation of changes, and the results are ANDed as shown by 126.

First, the output of the envelope detector 114 is sent to the delay circuit 128.
, averaged with the IIIf-interval earlier value as indicated by adder 129 and multiplier 130, first multiplied by a factor C2 as indicated by multiplier 13z, with nine average signal levels; The subtraction circuit 131 receives the subtraction circuit 131. As shown graphically in FIG. 6, the delayed form of the output of the match filter must be greater than 02 times the average signal value of the detected change. Finally, the average signal level itself is 0 in another subtraction circuit 134.
3.

This threshold C5Fi is set higher than the expected noise level to prevent the possibility that detection of a change will be hindered by noise when there is no input signal.

Additionally, by attempting to detect changes to the average signal and pels, this portion of the detection circuitry is trapped to respond to changes in level rather than absolute signal level.

The output of AND gate 126 is preferably used to latch a flip-flop 136, and the output of flip-flop 136 is used to provide the desired transition time indication on line 138. The main advantage of this method is that it simplifies the adjustment of the next balancer by removing all uncertainties regarding the correct synchronization between the signal and the reference sequence. Furthermore, this method is reliable and accurate and provides a time signal varying within one beat interval. Finally, this method is sensitive to the characteristics of the communication channel, signal amplitude or signal phase. Another advantage is that this method is computationally efficient if the modem is implemented digitally.

Change detection only needs to be performed during the baud synchronization part of the preamble, so that the full computational power is available during computation-intensive balancing device adjustments.

From the foregoing description, it will be appreciated that the present invention represents a significant advance in the field of high speed modems. In particular, the present invention provides a method for quickly acquiring a received signal and reducing the table acquisition time required to operate effectively in half-duplex mode. Furthermore, the present invention provides a new method for detecting the start of a balancer adjustment sequence in the signal preamble prior to the transmission of data.

It will also be understood that while particular embodiments of the invention have been described in detail for purposes of illustration, various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not limited except by the scope of the appended claims.

[Brief explanation of drawings]

FIG. 1 is a timing diagram illustrating the various segments of the signal preamble incorporated in the data transmission standard FED-8-1007. FIG. 2a is a phaser diagram showing the phaser transmitted during the baud synchronization segment of the preamble of FIG. FIG. 2C is a phaser diagram showing possible phaser positions used for transmitting data signals after the passage of FIG. 2. FIG. FIG. 5 shows that the signal preamble is in accordance with one invention for faster signal acquisition during one synchronization time. 1 is a block diagram showing a receiving modem with a middle stage coupled to the modem; FIG. 4 is a block diagram illustrating a receiving modem with a coordinated sequence detector in accordance with the present invention. 5 is a block diagram showing an example of a complex match filter used in the adjustment sequence detector of FIG. 4. FIG. 6 is a graph showing the amplitudes of various signals of the adjustment sequence detector of FIG. 4. . Explanation of drawing numbers 10... Automatic gain control circuit, 12... Heterodyne circuit, 14... Loaf 4 filter, 16... Adaptive balance device, 18... Demodulator, 20... Phase locked loop . 40... arctangent circuit, 42... - interval delay circuit,
44.46.48... Subtraction circuit, 50... Addition logic circuit %80... First summation circuit, 82... Multiplier, 8
4... Second counting circuit, 86... Multiplier, 90...
Prediction circuit, 93... Multiplier, 94... Fifth tally circuit, 96... Accumulation circuit, 98... Fukuatsuzo circuit,
100...Delay circuit, 102...Subtraction circuit, 104
...Aggregation circuit. 106... is a -interval delay circuit, 110... Complex match filter, 114... Envelope detector, 116
... Subtraction circuit, 118 ... Envelope detector, 1
20...Low pass filter, 122...Magnification i. 126...And? -), 128...delay circuit, 1
29... Adder, 130... Multiplier, 131...
Subtraction circuit, 134... Subtraction circuit, 136... Flip-flop.

Claims (9)

[Claims] (1) In a fast carrier acquisition device for use in a receiving modem: two alternating phaso
rs) being received by the modem; and: for calculating a phase error signal from the actual angle of the phaser being received and the expected angle of the phaser being received. Means: The apparatus comprises a phase-locked loop for calculating, from the phase error signal, sine and cosine values for use in demodulating the carrier wave. (2) said means for determining which 7 acers are being received; an arctangent 9 circuit providing a signal indicative of the actual angle of the phacer being received; 11-intervals earlier received; a delay circuit for providing a signal indicative of the actual angle of the Acer; means for subtracting a signal indicative of the phase angle and a signal indicative of the delayed phase angle to provide a signal indicative of the difference in phase angle; means for comparing the signal indicating the difference with the signal indicating the constant angle to obtain a signal indicating which of the two alternating phasers is currently being received. The device according to item 1. (3) Two alternating facers 1800 and 315
with an angle of 1800°: the phase angle difference has one of two possible values, approximately 135° and approximately 225°;
43. The apparatus of claim f42, wherein said comparing means provides a value of approximately +45° or approximately -45° depending on which 7 Acer is being received. 4. The device of claim 2, wherein the phase a-lock loop includes a prediction circuit to compensate for modem time delays and thereby stabilize operation of the device. (5) In an apparatus for detecting the start of an adjustment time of a balancing device for use in a receiving modem: a complex match filter coupled to receive a complex phaser signal from the modem; an output of said match filter; and means for providing a timing signal indicative of the start of an adjustment sequence. (6) means for obtaining an average signal value of the complex phaser signal sent to the match filter; means for multiplying the average signal value by a predetermined seven actors for use as a threshold signal for comparison in the means; 6. The apparatus according to claim 5, further comprising: h. (7) The means for obtaining an average signal value includes: an envelope detector to which the same signal as that input to the match filter is input; and a low A4 filter to which the output signal from the envelope detector is input. 7. A device according to claim 6, comprising: (8) means for delaying the output of the match filter: comparing the delayed output of the match filter with a predetermined multiple of the average signal value; means for generating a first enable signal when the timing signal is greater than a multiple of the timing signal, such that the first enable signal must be present before the timing signal can be generated. The device according to item 7. (9) further comprising means for comparing the average signal level with a predetermined threshold value and generating a second enable signal when the average signal level exceeds a predetermined dark value, the second enable signal also being a timing signal; 9. A device according to claim 8, which must be present beforehand. (to) In a fast carrier wave acquisition method for use in a receiving modem: Go to determine which of the two alternating 7 ACERS is being received by the modem during the synchronization time: calculating a phase error signal from the angle and the expected angle of the phaser being received; and deriving from the phase error signal sine and cosine values for use in demodulating the carrier wave. The above method. αB Said determination step; generates an angle signal indicative of the actual angle of the phacer being received in the arctangent circuit; delays the signal generated in said generation step to obtain the actual phacer angle received one interval earlier; providing a delayed angle signal indicative of: subtracting said angle signal from the delayed angle signal to provide a signal indicative of the phase angle difference; and comparing the signal indicative of the phase angle difference with a signal indicative of a predetermined angle to obtain two alternating phasers. 11. A method as claimed in claim 10, including each step of obtaining an indication of which of the following is currently being received. (12 The two alternating phasers have angles of 180° and 315°; the phase angle difference has two possible values, namely about 1350 and about 2
25°: The predetermined angle is 180°, such that the comparison means give a value of approximately +45°t71Cri approximately -45° depending on which phaser is being received. The method according to item 11. 13. The method of claim 11, wherein said step of deriving sine and cosine values is performed in a phase lock loop and includes a step of compensating for modem time delays. ■ A method for detecting the start of the adjustment time of a balancing device for use in a receiving modem, the method comprising: filtering the complex phaser signal provided by the modem with a multi-stage complex match filter: output signal from the complex match filter; and providing a modem timing signal based on the results of the comparison steps. α51 Obtaining an average signal value from a complex facer signal that is passed through a complex match filter; further comprising each step of multiplying the average signal value by a predetermined factor in order to use it as a threshold value or signal in the comparison step h. 15. The method according to claim 14. 16. The method of claim 15, wherein said step of obtaining an average signal value includes the steps of: obtaining an envelope signal from a signal passed through a complex match filter; and filtering said envelope signal by a loaf filter. . (!η Delay the output of the match filter: compare the delayed output of the match filter with a predetermined multiple of the average signal value; only when the output of the match filter is greater than the predetermined multiple of the average signal value 17. The method of claim 16, further comprising the steps of generating a potential signal: comparing the Ql average signal value with a predetermined dark value: when the average signal value is greater than the predetermined threshold; 18. A method as claimed in claim 17, including each step of generating only a second enable signal.