JPS60123964A - Interpolation arithmetic device - Google Patents

Abstract

PURPOSE:To make interpolation at a high speed with a simple constitution, by holding an output read out from a memory in a latch circuit and again writing the output in the memory after shifting the output by a prescribed clock portion together with the output of the latch circuit. CONSTITUTION:Data from a CPU are written in a memory 1 through a buffer 2. An output read out from the memory 2 is latched by a latch circuit 4 and delayed by a designated clock portion at a shift register 5. The output of the shift register 5 and that of the latch circuit 4 are written in the memory 1 through a buffer 7 after they are added to each other at an adder circuit 6.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to computer tomograph (CT)
y) The present invention relates to an interpolation calculation device that performs positional interpolation of data when performing back projection to obtain a reconstructed image from projection data in the device.

[Prior art]

Conventionally, one of the methods for reconstructing images from projection data in CT equipment is back projection, in which projections that have been removed in each direction are returned to the pixel plane, and the images are summed to obtain a reconstructed image. There is a law (pack projection). When performing this back projection, the coordinate system is changed, resulting in mismatching of the grid points. Therefore, interpolation is necessary to obtain a high-quality image. This interpolation is usually performed linearly with respect to the distance between two nearby grid points, and the following methods are conventionally available, but each has its own problems.

In other words, since interpolation involves multiplication, it takes too much time to perform calculations in software, and the scale is too large for hardware. There is also a method of creating a table using a ROM or the like, but increasing accuracy requires a large amount of memory, making it impractical.

[Purpose of the invention]

The porpose is to do.

The interpolation calculation device of the present invention includes a memory that can be written to and read from, an address scan circuit that scans the addresses of this memory in forward and reverse directions, a latch circuit that holds the read output of the memory, and a A structural feature includes: a shift register that delays data by a specified clock; and an adder that receives the outputs of the shift register and the latch circuit as inputs, and uses the output as the write input of the memory again. That is.

[Embodiments of the invention]

The present invention will be described in detail below using the drawings.

FIG. 1 is a block diagram showing an embodiment of an interpolation calculation device according to the present invention. 1 is a writable and readable memory, 2 is a buffer for writing data from the CPU into this memory 1, and 3 is an address scan such as an up/down counter that sequentially scans the addresses of the memory 1 in forward and reverse directions. A circuit, 4 is a latch circuit that holds the read output of the memory 1, 5 is a shift register such as a multi-level pipeline register, which delays data from the child circuit by a specified clock, and 6 is this software. An adder 7 which inputs the outputs of the register 5 and the latch circuit 4 and adds them together is a buffer which writes the output from the adder 6 to the memory 1 as an input.

FIG. 2 is an operational explanatory diagram showing the contents of the memory 1 at each operation stage when the interpolation calculation device having such a configuration is used to perform the interpolation calculation during back projection. In the figure, arrows indicate the magnitude and direction of the data shift in the shift register 5. Here, a case is shown in which the minute s*',: is increased by eight times by interpolation. (4) shows the state in which data has been written from the CPU to memory 1. Using 8 times the memory of the original data, data is written every 8 addresses, and the data in the addresses in between is 0. . Move this data in the forward direction (
latch circuit 4
It is then added to the shift register 5.

After shifting by one stage in the shift register 5 as shown by the arrow, the contents are added to the contents of the latch circuit 4 in the adder 6, and the content as shown in (13) is written to the memory 1 (forward scan one stage shift). . Next, the contents of (B) are scanned and read in the reverse direction (in the direction in which the addresses decrease), added to the latch circuit 4, and the contents of the latch output shifted by one stage in the shift register 5 as described above are transferred to the child circuit 4. When added to the contents, the contents of memory 1 become as shown in (C) (reverse scan, one stage shift). Similarly, (D) is the case where the forward scan is shifted by 2 steps, @) is the case where the reverse scan is shifted by 2 steps, CF is the case where the forward scan is shifted by 4 steps, and (G) is the case where the reverse scan is shifted by 4 steps. show. This result (4
) has been linearly interpolated and smoothed. The following table shows the calculation time when the interval of interpolated data is changed. Here, T is 1 for projection data only.
This is the time required to scan once.

For example, if the frequency is 6 MHz and the data is 512, then T=
It becomes 80 μs. When 3-bit interpolation is performed using 512 data, the calculation time is 4 ms, which is shorter than the frame time.

FIG. 5 is an operational explanatory diagram showing the contents of the memory 1 at each operation stage when projection data is smoothed using the above interpolation calculation device.

The projection data is sequentially written to each address of the memory 1 as shown in (A). In the same way as in the case of Figure 2, this is shifted one step in the forward scan to (13), shifted one step in the reverse scan to (C), shifted two steps in the forward scan to CD), and vice versa. The image after two scan steps is shown in (g)). The smoothed result (E) can also be thinned out and used to obtain the required resolution.

The interpolation arithmetic device configured as described above performs processing using hardware, and uses only the addition function as the arithmetic function, so it is capable of high-speed operation.

In the above embodiment, the memory 1 is read/written in one clock cycle, but in this case,
Reading and writing may be performed alternately using two memories.

Further, since the interpolation smoothing of back projection data and the smoothing for orthogonal projection performed for evaluating and simulating a reconstructed image can be performed using exactly the same process, the configuration can be simplified.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an interpolation calculation device that performs interpolation at high speed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an interpolation calculation device according to the present invention, and FIGS. 2 and 3 are diagrams illustrating the operation of the device shown in FIG. 1. 1...Memory, 5...Address scan circuit, 4.
... U, circuit, 5... shift register, 6... adder.

Claims (1)

[Claims] a writable and readable memory, an address scan circuit that scans addresses of this memory in forward and reverse directions, and a latch circuit that holds a read output of the memory;
This includes a shift register that delays data from a child circuit by a specified clock, and an adder that receives the outputs of this shift register and the latch circuit as input, and uses the output as a write input to the memory again. interpolation calculation device.