JPH02139799A - Two-dimensional shift register and dynamic vector detecting arithmetic circuit using the register - Google Patents

Abstract

PURPOSE:To reduce the number of data to be read out from a memory by using a two-dimensional shift register to store data required for block processing in the register. CONSTITUTION:A shift register 2 for storing image element values outputted from a memory 1 and a two-dimensional shift register 3 for storing image element values outputted from the register 2 are prepared and data from a shift register 4 for storing a reference image element value are outputted to an arithmetic circuit 5 for computing a matching error function to be a similarity evaluating reference between two blocks. Since the image element value read out from the memory 1 is stored in the register 3 to utilize it, rereading of the same data from the memory 1 can be omitted. Consequently, the reading frequency of the image element values from the memory can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic circuit for detecting motion vectors used in video codecs and the like.

BACKGROUND OF THE INVENTION FIG. 10 shows an example of the configuration of a conventional motion vector detection arithmetic circuit. In FIG. 10, 22 is a memory that stores pixel values, and its output is input to 24. 23 is a shift register for storing reference pixel values;
It is connected to its output A. 24 is an arithmetic circuit for a matching error function, which serves as a similarity evaluation criterion between two blocks.

Figures 11 and 12 are blocks with two-dimensional images (4×
4 pixels). D(x,y) and R(x,y)
represents the pixel value. FIG. 13 shows the block in FIG. 12 moved one pixel to the left.

FIG. 14 shows the block in FIG. 12 moved to one pixel cloth. FIG. 15 shows the block in FIG. 12 moved one pixel downward. FIG. 16 shows the movement order of blocks. It sequentially moves from 1 to 49 pixels one pixel at a time over 49 pixels.

Next, the operation of the above conventional example will be explained. Let us calculate the matching error function F(n, m) of the block in FIG. 12 using the block in FIG. 11 as a reference.

shall be. At this time, the pixel values D (x, y) of the entire image shown in FIG. 12 are stored in the memory 22, and the shift register 23
The pixel value R(x, y) of the block in FIG. 11 is held. First, D(n, m) from the memory 22 and shift register 23, respectively.

R(n,m) is output. And arithmetic circuit 24TEF (
n, m)=lD(n, rn)−R(n, m) 1
is calculated. Next, memory 22 and shift register 23
, D(n+1.m) and R(n+1.m) are output, respectively. Then, in the arithmetic circuit 24, F(n, m)-p(n
, m)+ID(n+1, m)-Jn+1, m) is calculated. By performing the same operation below, ])(n
, m) ~D(n+3.m+3), R(n, m)
Arithmetic processing is performed on ~R(n+3.m+3),
Finally, F(n, m) is obtained. Figures 13 and 14
figure.

When calculating the matching error function of each block in FIG. 15, the same operation as above is repeated, and each F(n+
11m)IF(n-11m)IF(n,m+1) is obtained. It is necessary to read 16 pixel values from the memory 22 for calculation of each block. Therefore, if the matching error function is calculated each time the block is moved pixel by pixel as shown in FIG.
X 49 = 784 When an arithmetic circuit processes a certain block and then processes a block one pixel to the left of the same block,
D(n, m) to D(n+2.m+ of 16 pixel values
There is a problem that the 12 pixel values of 3) need to be output again from the memory 22, and the processing time is long.

The present invention is intended to solve these conventional problems.
An arithmetic circuit for detecting motion vectors capable of high-speed arithmetic processing In order to achieve the above object, the present invention provides a shift register that can be shifted in two-dimensional directions, and stores pixel values once read from a memory there for use. This is an attempt to reduce the amount of data read from memory.

Effects The present invention has the following effects due to the above configuration. That is, by holding and using the pixel values read from the memory in the two-dimensional shift register, there is no need to read the same data from the memory again. Therefore, it is possible to reduce the number of times pixel values are read from the memory.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 1 is a memory that stores pixel values, and its output is input to 2.

2 is a shift register that holds pixel values output from the memory, and its output is connected to 3. 3 is a two-dimensional shift register that holds the pixel value output from shift register 2, and its output is connected to 5.

4 is a shift register that holds a reference pixel value, and its output is connected to 5. Reference numeral 5 denotes a matching error function calculation circuit, which serves as a basis for evaluating the similarity between two blocks.

FIGS. 2 and 3 show pixel values held in the two-dimensional shift register 3 and shift register 4 in the above embodiment. In FIGS. 2 and 3, 6.8 is the pixel value held in the two-dimensional shift register 3. In FIG. 7 and 9 are pixel values held in the shift register 4.

4 to 9 show pixel values held in the shift register 2 and the two-dimensional shift register 3 in the above embodiment. In Figures 4 to 9, 10.12, 14, 1
6, 18.20 are pixel values held in the shift register 2. 11 , 13 , 15 , 17 , 19 .

21 is a pixel value held in the two-dimensional shift register 3.

Next, the operation of the above embodiment will be explained. First, the 11th
Based on the block in the figure, the block in Figure 12 and the first
3. A case will be described in which the matching error functions F(n, m) and F(n+1.m) of the blocks shown in FIG. 3 are successively calculated. At this time, the pixel values of the entire image shown in FIG. 12 are stored in the memory 1, and the pixel values of the entire image shown in FIG.
The pixel values of the blocks in the figure are held. First, memory 1
The pixel values shown in FIG. 12 are transferred from the 2D shift register 3 to the 2D shift register 3, and the pixel values D(n, m) to D(n, m+3), R(n
, m) to R(n, $3) are output simultaneously. Then, in the arithmetic circuit 5, F(n, m)=Σl D(n, m+j)−
R(n, m+j) is calculated. Next, the pixel values are write rotated and transferred from the two-dimensional shift register 3 and shift register 4 to D(n+1, m) to D(n+1
, m+3).

R(n+1.m) to 几(n+1, m+3) are output at the same time. Then, the arithmetic circuit 5 calculates -R(n+1.m-+-j). By performing similar operations below, D(
n, m) ~ D (n 10: 3. m + 3), R (n, m)
Arithmetic processing is performed on ~R(n-1-3°m+3), and m+j) is finally obtained. At this time, the pixel values held in the two-dimensional shift register 3 and shift register 4 have returned to the state shown in FIG.

Memory 1 to D(n+4.m) to D(n+
4゜m+3) is read out and stored in shift register 2 as shown in Fig. 4.
Pixel values such as 0 are held. Then, the output is write-shifted to the two-dimensional shift register 3 before processing the next block. The pixel values held in the two-dimensional shift register 3 are as shown at 13 in FIG. From this state, an operation similar to that of the previous block is performed and -R(n+1+i, m+j) 1 is obtained. At this time, only four pixel values are read out from the memory 1 for the calculation process of F(nl,m).

Next, using the block in FIG. 11 as a reference, the matching error function F(n
, m) and F(n-1, m) are successively calculated in order. The processing of the blocks in FIG. 12 is the same as above.

During the processing, memory 1 to D(n-1, m) to D(n-1
m+3) is read out and the pixel value is held in the shift register 2 as shown in FIG. Then, the output is left-shifted to the two-dimensional shift register 3 before processing the next block. The pixel values held in the two-dimensional shift register 3 are as shown in FIG. From this state, an operation similar to that of the previous block is performed to obtain -R(n-1+i, m-+-j). At this time, only four pixel values are read out from memory 1 for post-block processing.

Furthermore, using the block in FIG. 11 as a reference, the matching error function F(n
, m) and F(n, m+1) are successively calculated in order. The processing of the blocks in FIG. 12 is the same as above.

During the processing memory 1 to D(n, m+4) to D
(n+3°m+4) is read out and the pixel value is held in the shift register 2 as shown in FIG. The output is then upshifted to the two-dimensional shift register 3 before processing the next block. The pixel values held in the two-dimensional shift register 3 are as shown at 21 in FIG. From this state, the same operation as the processing of the previous block is performed and -:R(n+i, m+1+J) 1 is obtained. At this time, only four pixel values are read out from memory 1 for post-block processing.

Therefore, if the matching error function is calculated each time the block is moved pixel by pixel as shown in FIG. 16, the number of pixel values read out from the memory 1 will be 16+4×48=208.

Effects of the Invention As is clear from the above embodiments, the present invention uses a two-dimensional shift register and stores data necessary for block processing therein, making it possible to reduce the number of data read from memory. .

In the conventional example and embodiment described above, 784 is reduced to 208. Since the processing time of the motion vector detection arithmetic circuit is almost determined by the memory read time, reducing the number of memory reads has the advantage that the processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an arithmetic circuit for motion vector detection according to an embodiment of the present invention, and FIGS. 2 to 9 are diagrams for explaining an arithmetic method using a two-dimensional shift register of the present invention.
Figures 2 and 3 are diagrams showing pixel values held in the two-dimensional shift register 3 and shift register 4, respectively, and Figures 4 to 9 show pixel values held in the shift register 2 and two-dimensional shift register 3 [' 10 are block diagrams of conventional motion vector detection calculation circuits, FIGS. 11 and 12 are diagrams showing pixel dimensions of a block in a two-dimensional image, and FIG. 13 is a block diagram of the block in FIG. 12. A diagram with pixels shifted to the left, Figure 14 is the first
Figure 15 is a diagram in which the block in Figure 2 is shifted one pixel to the right, Figure 15 is a diagram in which the block in Figure 12 is shifted one pixel down, and Figure 16 is a diagram in which the block in Figure 12 is shifted one pixel down.
The figure shows the movement order of blocks. 1...Memory, 2,4...Shift register% 3
...Two-dimensional shift register, 5... Arithmetic circuit, 6,
8,11゜13.15,17,19.21...Pixel value held in two-dimensional shift register 3, 7,9...Pixel value held in shift register 4, 10,12,14,16,1
8.20... Pixel value held in shift register 2. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (2)

[Claims] (1) Memory elements arranged in a matrix, and a means for shifting data stored in the memory elements column by column (or row) by inputting a shift pulse, and outputting the data in parallel from an output side. . means for shifting each piece of data in the matrix in parallel to an adjacent row or column each time parallel data is input from one side of the matrix. (2) a memory that stores data of frames of moving images;
A first shift register for holding the image data output from the memory, a second shift register for storing the data of the reference image frame, and a second shift register for holding the image data output from the first shift register. A moving vector comprising: the two-dimensional shift register according to claim 1; and an arithmetic circuit for calculating a motion vector between the image data of the two-dimensional shift register and the image data of the second shift register. Detection calculation circuit.