JPS60123096U - 2 wire transmitter - Google Patents
2 wire transmitterInfo
- Publication number
- JPS60123096U JPS60123096U JP553984U JP553984U JPS60123096U JP S60123096 U JPS60123096 U JP S60123096U JP 553984 U JP553984 U JP 553984U JP 553984 U JP553984 U JP 553984U JP S60123096 U JPS60123096 U JP S60123096U
- Authority
- JP
- Japan
- Prior art keywords
- output
- capacitor
- sample
- wire transmitter
- hold circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の２線式伝送器の一例を示す回路構成図、
第２図、第４図は本考案の一実施例を示す回路構成図、
第３図、第５図は第２図、第４図の動作説明図である。
１・・・・・・変換回路、２・・・・・・演算増幅器、
３・・・・・・出力トランジスタ、Ｃ□・・・・・・コ
シデンサ、４，１０・・・・・・スイッチ、５・・・・
・・タイミング回路、６・・・・・・サンプルホールド
回路、７・・・・・・交流発振器、９・・・・・・カレ
ントミラー回路、Ｔ１．Ｔ２・・・・・・出力端子、１
１゜１２・・・・・・伝送線、ＲＬ・・・・・・負荷、
ＥＢ・・・・・・直流電源。
」上下π丁「
１′１１ｒｌ−１高１．’−，’
μ匪臼諷
５巴司−二７丁１
〜 ＋
ＥＢ＝
牛、ｃｆ １へ４ −
Ｔ２ ノ２Figure 1 is a circuit diagram showing an example of a conventional two-wire transmitter.
2 and 4 are circuit configuration diagrams showing an embodiment of the present invention,
FIGS. 3 and 5 are explanatory diagrams of the operations in FIGS. 2 and 4. 1... Conversion circuit, 2... Operational amplifier,
3...Output transistor, C□...Cocidencer, 4,10...Switch, 5...
...Timing circuit, 6...Sample hold circuit, 7...AC oscillator, 9...Current mirror circuit, T1. T2...Output terminal, 1
1゜12...Transmission line, RL...Load,
EB・・・DC power supply. "Upper and lower π-cho"1'11rl-1 height 1.'-,' μ匪うす諷5巴士-27-cho 1 ~ + EB= Cow, cf 1 to 4 - T2 ノ2
Claims (1)
されると共にプロセス量に対応しｆ出力電流を上記出力
端子を介して上記伝送線に送出する２線式伝送器におい
て、上記出力電流を制御する出力トランジスタと、上記
出力電流に関連した電流により充電されるコンデンサと
、このコンデンサの充電々荷を放電するスイッチと、上
記コンデンサの端子間電圧をサンプルするサンプルホー
ルド回路と、上記スイッチ及び上記サンプルホールド回
路を駆動するタイミング回路と、上記サン□ プ
ルホールド回路の出力信号と入力信号との差を増幅して
上記出力トランジスタを制御する増幅器とを有する２線
式伝送器。In a two-wire transmitter that is supplied with power from the outside via two transmission lines from a pair of output terminals and sends an output current corresponding to a process amount to the transmission line via the output terminals, the output current a capacitor that is charged by a current related to the output current; a switch that discharges the charge of the capacitor; a sample-and-hold circuit that samples the voltage between the terminals of the capacitor; A two-wire transmitter comprising: a timing circuit that drives the sample and hold circuit; and an amplifier that amplifies the difference between the output signal of the sample and hold circuit and the input signal to control the output transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP553984U JPS60123096U (en) | 1984-01-18 | 1984-01-18 | 2 wire transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP553984U JPS60123096U (en) | 1984-01-18 | 1984-01-18 | 2 wire transmitter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60123096U true JPS60123096U (en) | 1985-08-19 |
Family
ID=30482136
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP553984U Pending JPS60123096U (en) | 1984-01-18 | 1984-01-18 | 2 wire transmitter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60123096U (en) |
-
1984
- 1984-01-18 JP JP553984U patent/JPS60123096U/en active Pending
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