JPS60121590A - Storage integrated circuit - Google Patents

Abstract

PURPOSE:To improve the stability of a reading action and to shorten the cycle time by turning on a coupling transistor which short-circuits a pair of digit lines in a precharge mode to inactive a sense circuit and then turning off the coupling transistor after the precharge mode to actuate the sense circuit. CONSTITUTION:Digit lines D and -D are precharged at the same potential with arrival of a coupling signal phiC and immediately after the start of precharge. At the same time, sense nodes A and B are also precharged at the same potential. When the precharge is ended [t=phiL, phiC (OFF)], the potential of both nodes A and B drop at the same level with supply of electronic charges given from lines D and -D. Then the difference voltage is obtained by receiving the effect of a dummy cell as well as a memory cell at and after the drive mode [t=phiW, phid (ON)] of the address and dummy address signals. The node B of a high potential is set at the potential of the line -D with the drive [t=QS (ON)] of the sense signal. While the node A of a low potential drops down to a low potential of a power supply together with the line D. This low potential is written to the memory cell of the address which is read out in the form an information signal. Then a refresh action is carried out.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory integrated circuit using an insulated gate field effect transistor called an IC memory or MOS memory.

Integrated circuits using insulated gate field effect transistors have been developed into large-scale integrated circuits because they can be easily increased in density.

In particular, large-capacity memory integrated circuits have large-capacity memory cells on a common semiconductor substrate, and realize high-performance, highly reliable semiconductor devices. A preferred memory cell for this is 1
Transistor Exhibition Random Access Mesori (ITR-
In this type of MOS memory (RAM), switching transistors and information storage capacitive elements are arranged at matrix intersections where word lines and digit lines intersect. In this ITR-RAM, in order to prevent the capacitance value of the capacitive element from increasing as the capacity increases, it becomes necessary to add a highly sensitive sense circuit to the digit line. A conventional preferred circuit technique is to provide the sense circuitry and digit lines with transistors operating in saturation.

In addition, this circuit technology was introduced in 1975 with the
C.C. Technical Digest Papers (
'75 I8SCCTechnicml Digest
Papers) J nihe2- (L, G, He1l
er) etc., the sensing operation is started by a signal to the sense node that is larger than the signal amplitude of one digit line.

However, in this conventional circuit technology, the precharge state of the digit line before the start of the sense operation governs the conditions at the start of the sense circuit operation, and this precharge operation is performed through a transistor in a saturated state, so the sense circuit It takes a long time to reach the equilibrium precharge obtained at the end of the precharging of the digit lines on both sides, and the cycle time when performing information read operations one after another is long. There is a drawback that the sense node amplitude cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory integrated circuit with a highly sensitive circuit configuration that provides stability in read operations and short cycle times.

According to the invention, a plurality of word lines and a plurality of disks)
Memory cells each having a transistor and a capacitive element are provided at the intersections of the matrix and matrix where M intersects, and a sense circuit for sensing a signal generated in a pair of digits is connected to the pair of gauge and T lines, and the digit line In a memory circuit connected to a precharge circuit that supplies a precharge voltage to a memory circuit, a coupling transistor that shorts the pair of digit lines is turned on during precharging, a sense circuit is made inactive, and the coupling transistor is turned on after precharging. There is obtained a memory integrated circuit characterized in that the sense circuit is controlled to be turned off and the sense circuit is put into an operating state. The memory integrated circuit obtained here is the so-called lTR
- RAM or the first and second digit lines are a pair of digit lines, and a switching transistor and a capacitive element are provided for each of the first and second digit lines at the portion where they intersect with the word line, 2TR-20 -RAM
Applies to.

In the memory integrated circuit of the present invention, the first and second digit lines are forcibly balanced during recharging by the coupling transistor, so that a balanced state can be obtained before the end of precharging and a read operation can be started. can. Therefore,
This reduces the access time to start reading and the cycle time, making it a faster storage device.In addition, as will be explained later, it reduces the sensitivity caused by successive access to different addresses as seen in conventional circuits. There is no point in causing instability in the accompanying motion.

Next, an embodiment of the present invention will be described using FIG. 9.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, multiple word lines (φW,...)
and a plurality of digit lines (D, D, . . . ) and a plurality of digit lines (D, D, . . . ) each have a memory cell formed of a transistor and a capacitor at each intersection of a matrix.

For simplicity, this figure only shows one address signal line 11, one dummy address signal J112, and digit lines D extending on both sides of the sense circuit. Dummy address line 11 is driven by dummy address signal φd when reading information from a memory cell coupled to one digit MD, and transmits information from a dummy cell having a similar configuration to the memory cell to the other digit line. That is, the transistor Q of the memory cell
One of the xa drain and source is connected to one digit line, the other is coupled to one end of the capacitive element C, and the gate electrode is driven by an address signal φ7. Furthermore, one of the drain and source of the dummy cell transistor Q2 is connected to the other digit line bK, the other is coupled to one end of the capacitive element C2, and the gate electrode is driven by the dummy address signal φd.

Further, transistors Qs and Q4 are provided between each digit line b and the sense circuit, respectively.
D and D are coupled to sense node A%BK of the sense circuit and output regions called drain and source of each transistor QB and Q4O, respectively. Transistor Q8. Q4 obtains saturated II (triode region) operation because the drive voltage applied to the gate electrode is equal to or lower than the highest potential of the sense node B. The sense circuit includes precharge transistors Qs, Qs and sense transistors Q7, Q.
s and a current outflow transistor Q9.

The precharge transistors Qs, Qs have drains connected to the high potential l1IvDK of the power supply, sources connected to the sense node A1B, and gate electrodes driven by the precharge signal φ1. Sense transistor Q7, Qs
The drains are connected to the sense nodes A and H, respectively, the sources are commonly connected to the node K, and the gates are connected to each other's drains. In addition, the drain and source of the current outflow transistor Q are connected to the node and the low potential line GND of the power supply, respectively.
K connection is made, and the gate electrode is driven by the sense signal φ3.

Furthermore, digit lines D and Dec extend on both sides of the sense circuit.
The output region of the a-coupling transistor Q1° is connected, and by driving the coupling signal φC to the gate electrode of this transistor, both digit lines are forcibly brought to the same potential during precharging.

FIG. 2 shows an operating waveform diagram of a conventional ITR-RAM. In this circuit, the output regions are connected to sense nodes and BK, respectively. After reading the reverse information of the subsequent address in the preliminary read operation, during the precharge period from 1-0 to t-φc (OFF), the sense node A%B rises to about 6Vt, and the digit line D%D rises. It is precharged at approximately 3vi. The voltage conditions here are that the power supply voltage is 8V, the drive voltage is 5.5V, and the gate threshold of all transistors is IV.
This is an N-channel insulated gate transistor. At the end of precharging (1-φL1φC(off)), the precharge level of D does not reach complete equilibrium for the digit line with large load capacity, so the sense node is opened when the coupling transistor transitions to cutoff operation. Charge is transferred to and from the digit line through a transistor that operates in the A%Ba saturated state, changing the potential. Due to the history of reading reverse information at different addresses, the potential of sense node B drops more rapidly than that of one sense node AK due to the inflow of electron charge from the digit line.

When the drive of the address signal starts (1-φW, φd (ON)), the digit line is activated, and when the accumulated charge of the layer information of the capacitor of the memory cell and the dummy cell changes the potential of the digit line, the sense node becomes The potential is lower than that of sense node B,
A differential voltage ΔV is generated at the start of sensing (-φ8 (ON)). The load capacity of digit line D%D is 1.2 each.
pp, the capacitance values of the memory cell capacitor and dummy cell capacitor are 0.12 pF and 0.06 pF, respectively.
In this case, this voltage difference is at most 0.15V. This differential voltage is amplified by driving the sense signal, and when the sense ends [
−φ. ,φ.

(ON), t-φ7, φ4, φ, (OFF)), precharging is started again.

This conventional circuit requires a very long time to completely balance the precharge to D due to the digit line.
Access and cycle times for reading stored information are slowed down. Furthermore, if the precharge time is shortened to shorten this time, the precharge levels of the digit lines will become incompletely balanced, resulting in a differential voltage of 71%, making the information detection operation unstable and uncertain.

FIG. 3 is a signal waveform diagram of the integrated circuit of the invention shown in FIG.

The precharge signal φ is at a high potential of about 7 V during the precharge period, and becomes a low potential before the address signal φ and the dummy address signal φd reach a high potential. Combined signal φ.

is a signal opposite to the address signal, and when the address signal φ7 and the dummy address signal are at a low potential, tkK becomes a high potential, forcing the digit lines on both sides of the sense circuit to be in a balanced state. Also, the sense signal φ8 is an address signal J) 10 to 3
It becomes a high potential with a delay of 0 nanoseconds, and becomes a low potential immediately after the address signal becomes a low potential.

FIG. 4 is an operational waveform diagram of the embodiment of the invention shown in FIGS. 1 and 3. Immediately after the start of precharging (t-0), the coupling signal ``digit line 5'' is precharged to the same potential, and accordingly, the sense node B is also precharged to the same potential. That is, During the precharge period, a precharge operation is already performed in an equilibrium state, and the influence of reverse information due to a read operation of another address is removed by driving the combined signal.Precharge end [t■φ φ.(OFF
)), the potential of the sense node λB falls at the same potential due to the inflow of electron charge from the digit line D%D, and the address signal,
When driving the dummy address signal [-φ1, φ.

(ON)) to obtain a differential voltage ΔV under the influence of the memory cell and dummy cell. Under the same conditions as the conventional circuit described above, this embodiment produces a voltage difference of 0.4V or more.

When the sense signal is driven (t-QB(ON)), the sense node B with a high potential is the potential of the digit line of this sense node example, and the sense node A with a low potential is the potential of the digit line on the side of this sense node. At the same time, the voltage drops to the low potential (-0V) of the power supply, and this low potential is written as an information signal to the memory cell at the address being read, and a refresh operation is performed. Also, before precharging starts again, a digit line with high and low potentials clearly dispersed,]5.
Alternatively, information is read from the memory cell from a read circuit (not shown) connected to the sense node A%B or one of them, and then precharging is started again.

In the lTR-RAM, the amount of charge to the capacitive element of the dummy cell is controlled during the precharge period, and this amount of charge is controlled so that the change in the sense node B occurs between the memory cell information "11" and °o2 when a word signal is driven. In other words, in the above explanation, the read operation of the information 101 is shown in which the node on the transistor side of the capacitive element C□ of the memory cell in FIG. 1 is Ov, but in the read operation of the information "l", The characteristics of this sense node A' are shown below.

In addition, in the 2TR-RAM that is being tried in the near future, the dummy address line and the address line in Figure @1 are the same address line, and the memory cell and dummy cell are composed of exactly the same transistor and capacitive element. , information 111°0'' or social information @0'', °l'' is always stored in the memory cell.The capacitive element of the memory cell that obtains the differential voltage The capacitance value of the dummy cell is reduced to less than 1/2, and charge control during precharging of the dummy cell is no longer necessary, resulting in extremely safe and reliable operation.

In both 1TR-RAM and 2TR-RAM, the balance of the digit lines extending on both sides of the sense circuit is achieved compared to the invention line conventional circuit, so the differential voltage at the sense node at the start of sensing is large, which reduces the precharge time. Information can also be reliably read. According to the present invention, the access time and cycle time of 100a8 and 170n8 in the conventional circuit example are shortened to 50n8 and 120n8, respectively, and reading is possible even if the capacitance value of the memory cell is reduced to V4.

Although the embodiments of the present invention have been described above, additions and changes to the present invention can be easily made as necessary. That is, the coupling transistor makes a pair of digit lines extending on both sides of the sense circuit conductive during precharging, and is an essential component of the present invention. It is also possible to add transistors and connect their drains and sources to two sense nodes, respectively.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is an operating waveform diagram of the conventional circuit, Fig. 3 is a drive signal waveform diagram of the embodiment of Fig. 1, and Fig. 4 is a diagram of the drive signal waveform of the embodiment of Fig. 1. FIG. 3 is an operational waveform diagram of the embodiment. In the figure, 11 is an address line, 12 is a dummy address line%D
%D is the digit line extending on both sides of the sense circuit %Q□ is the transistor of the memory cell, C□ is the capacitive element of the memory cell sQz is the transistor of the dummy cell, C2 is the capacitive element of the dummy cell, C3, Q4a digit line, D and Transistors s Ql respectively couple the sense circuits. is a procedural amendment (method) for combining digit lines D%5 Director General of the Patent Office 1, Indication of case 1982 Patent Application No. 101952 2, Title of invention Memory integrated circuit 3, Relationship with the person making the amendment case Applicant: 5-33-1 Shiba, Minato-ku, Tokyo

Claims (1)

[Scope of Claims] A memory cell provided at each intersection of a plurality of word lines and a plurality of digit lines intersecting these, and a sense control signal connected to a pair of digit lines to which the memory cell is connected. a sense circuit that performs a sensing operation in response to the above, and a sense circuit that supplies a precharge voltage to the pair of digit lines in response to the precharge signal, respectively. and a coupling transistor configured to stop the sense control signal during precharging to make the coupling transistor conductive, and trap the coupling transistor to be non-conductive after precharging to supply the sense control signal to the sense circuit. A memory integrated circuit characterized by: