JPS60119141U - logic circuit - Google Patents
logic circuitInfo
- Publication number
- JPS60119141U JPS60119141U JP13690584U JP13690584U JPS60119141U JP S60119141 U JPS60119141 U JP S60119141U JP 13690584 U JP13690584 U JP 13690584U JP 13690584 U JP13690584 U JP 13690584U JP S60119141 U JPS60119141 U JP S60119141U
- Authority
- JP
- Japan
- Prior art keywords
- logic gate
- logic circuit
- input signals
- element constituting
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はプログラマブルデイバイダ回路のブロック図、
第２図は第１図に用いる従来のＮＯＲ回路図、第３図及
び第４図は本考案の実施例をそれぞれ示す図である。
図において、９．１４はＰチャンネルトランジスタ景、
１１．１５は負荷用Ｎチャンネルトランジスタ、１７．
２０はＮチャンネルトランジスタ群、１９．２１は負荷
用Ｐチャンネルトランジスタをそれぞれ示す。
−巾・軒〉Ｉ
Ｊ〜））−ＯＶＱ、 ｌ ’ 、−」昇１’ｍ！、−
［
−−一弓士−・・
−７−
□
穎“１−Figure 1 is a block diagram of the programmable divider circuit.
FIG. 2 is a conventional NOR circuit diagram used in FIG. 1, and FIGS. 3 and 4 are diagrams showing embodiments of the present invention, respectively. In the figure, 9.14 is a P-channel transistor diagram,
11.15 is an N-channel transistor for load; 17.
Reference numeral 20 indicates a group of N-channel transistors, and reference numerals 19 and 21 indicate load P-channel transistors. -Width/Eaves〉I J~)) -OVQ, l', -''Rise 1'm! ,−
[ −−Archer−・・−7− □ Ying “1−
Claims (1)
力信号をうける第２の論理ゲートと、該第２の論理ゲー
トの出力を前記第１の論理ゲートに入力する手段とを有
し、前記第１の論理ゲートを構成する素子よりも前記第
２の論理ゲートを構成する素子が小さな面積で形成され
ていることを、 特徴゛とする論理回路。a first logic gate receiving a plurality of input signals, a second logic gate receiving a plurality of input signals, and means for inputting an output of the second logic gate to the first logic gate; A logic circuit characterized in that an element constituting the second logic gate is formed in a smaller area than an element constituting the first logic gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13690584U JPS60119141U (en) | 1984-09-10 | 1984-09-10 | logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13690584U JPS60119141U (en) | 1984-09-10 | 1984-09-10 | logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60119141U true JPS60119141U (en) | 1985-08-12 |
Family
ID=30695337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13690584U Pending JPS60119141U (en) | 1984-09-10 | 1984-09-10 | logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60119141U (en) |
-
1984
- 1984-09-10 JP JP13690584U patent/JPS60119141U/en active Pending
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