JPS60118955A - Main storage protecting device - Google Patents

Abstract

PURPOSE:To prevent a main storage area form being destroyed by providing a means comparing a memory address transmitted from a CPU and a main storage start address using in sharing and commoly one physical memory by a main storage and a control storage. CONSTITUTION:The CPU6 transmits a memory address (CPU-A) to a bus 19 at memory access. In case of CPUA<MSSA (main storage start address 8), an output of a comparator 10 only in a comparator circuit 9 and when the CPU6 requests a control storage access, since a signal line 20 is set, the access is permitted. In case of CPU=MSSA or CPUA>MSSA, either a coparator 11 or a comparator 12 is set and when the CPU6 request the main storage access, a signal line 21 is set, then the access is permitted.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention provides a computer system in which one physical memory is divided and shared between main memory and control memory. This invention relates to a main memory protection device for preventing

[Technology background]

The control memory that stores firmware software often needs to be expanded, and as one means for such cases, conventionally, a puncturing method has been used in which the address space of the control memory has a multiplexed structure.

FIG. 1 shows mapping on the address space in the case of puncture-based control storage. In the figure, 1 is an address space, 2 is a control storage address register, 3 is a puncture address register, 4 is a main storage address register,
5 indicates a main memory start address (MSSA) register.

The N punctures in the control storage area are specified by the puncture address register 3, and the addresses within each puncture are specified by the control storage address register 2. On the other hand, the address of the main memory area is absolutely specified only by the main memory address register 4.

Here, even if it is possible to port up to N punctures on the heart side, the firmware side may not need even 7il-N punctures, or there may be reasons such as a lack of absolute amount of address space. Accordingly, when the main memory start address (MSSA) is set to the position shown in Figure 2 by the main memory start address register 5,
Control memory punctures 3 to N will have the same address space as the main memory. In other words, the start address (MSSA) of Punk 3 can be accessed as the "MSSA" address for control memory access or the "15SA" address for main memory access. Therefore, due to a runaway of the firmware, etc., the Punk 3 to N specified [Objective and Structure of the Invention] An object of the present invention is to solve the problem in a memory in which a main storage area and a punctured control storage area are arranged adjacent to each other. The main purpose of this invention is to provide a means for protecting the main memory area against control memory access, and therefore compares the memory address sent from the CPU with the main memory start address and uses the result to protect the main memory area from control memory access. and allows/disallows main memory access.

Accordingly, the configuration of the present invention includes a memory that is divided into a main memory and a puncture-structured control memory, and a signal means for instructing whether to access the main memory or the control memory. In a computer system equipped with a CPU, a circuit that compares a register that holds a start address of a main memory with a memory address sent from the CPU of the main memory, and a circuit that compares a memory address that is a main memory start address as a result of the comparison. If the signal means for instructing the control memory access exists, the signal means is transferred to the memory, and the memory address is equal to or larger than the main memory start address. The present invention is characterized by comprising a logic circuit that transfers the signal means to all memories when the signal means for instructing main memory access is present.

[Embodiments of the invention]

The details of the present invention will be explained below based on examples.

FIG. 3 is a configuration diagram of an apparatus according to an embodiment of the present invention. In the diagram, 6 is C! PU, 7 is a memory, 8 is a main memory start address register, 9 is a comparison circuit, 10 to i to 12 are comparators, 13 is an OR dirt, 14 is a protection logic circuit, 15 to 1
7 is ANDf-to, 18 is interrupt request register, 19
is an address bus, 20 is a control storage access signal line, 21
2 represents a main memory access signal line, and 22 represents an interrupt signal line.

C! The PU 6 sends a memory address (hereinafter referred to as OPU A) onto the address bus 19 during memory access, and turns on either signal line gray or 21 depending on whether it is a control memory access or a main memory access. Make it.

A main memory start address (hereinafter referred to as MSSA) is set in the main memory start address register 8 in advance.

(The 3PU 6 sends the address CPU A, which is the memory address used inside the CPU when accessing the main memory plus MSSAi, to the memory 7.

Comparison circuit 9 compares 0PUA and MSSA using three comparators 10, 11, and 12 when wide open. Comparator lO
The output of the comparator 11 is on when CPUA=MSSA, and the output of the comparator 11 is on when CPUA=MSSA, and the comparator ratio is OPUA. In the case of OPUA (MSSA), only the output of comparator 10 is turned on, and an on level is applied to one input of AND dart 15 in protection logic circuit 14. At this time, 0PU6 is requesting control memory access. In this case, the control memory access signal line 20 is on, so the output of the AND dart 15 is on, and the CPU 6 is on.
control storage access is granted and the memory 7 is notified. This is allowed because as long as 0PUA is smaller than MSSA, there is no way that a main storage area that is always larger than MSSA will be accessed.

In the case of OPUA=MSSA or OPU A)IsSA, the output of either the comparator 11 or the comparator 12 is turned on, and the A-ND gate in the protection logic circuit 14 is output via the OR gate 13. and 17 are turned on. At this time, if 0PU6 requests main memory access, the main memory access signal line 21 is on, and the output of the AND gate 17 is on, allowing 5.0PU6 to access the main memory. The memory 7 is notified. On the other hand, if 0PU6 requests control memory access at this time, the control memory access signal is prohibited in A, ND dart 15, and the AND
The output of the dart 16 is turned on, the 1 interrupt request register 18 is set, an interrupt signal due to the access exception is sent to the CPU 6 via the interrupt signal line 22, and the 0PU6 performs 90% interrupt processing.

In this latter case, as long as OPUA)MSSA,
Since the control memory access of 0PU6 is to be made to the main memory area, this access is not permitted.

Note that when the CPU 6 requests main memory access 'Thff', C! Since PUA is always thicker than MSSA (as described above, 0PU6 sends out the address added by Is SAi), the condition CPUA<MSSA does not exist.

The above explanation can be summarized as shown in Table 1 below.Table 1 [Effects of the Invention] According to the present invention, even if the firmware goes out of control in a computer system with bank-structured control memory, the main memory access can be reliably prevented and the reliability of the system can be increased.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the address space of the control memory of the bank system, Fig. 2 is an explanatory diagram of the address space when the MSSA of the main memory is set in the bank of the control memory, and Fig. 3 is an explanatory diagram of the address space of the control memory of the present invention. FIG. 1 is a configuration diagram of an embodiment of the device. In the figure, 6 is a CPU, 7 is a memory, 8 is a main memory start address register, 9 is a comparison circuit, 14 is a protection logic circuit, 1
8 is an interrupt request register, 19 is an address bus, and 2 (
) represents a control memory access signal line, and 21 represents a main memory access signal line. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) Figure 1 Figure 2

Claims (1)

[Claims] In a computer system equipped with a memory that is divided into a main memory and a punctured control memory, and a CPU that is provided with a signal means for instructing whether to access the main memory or the control memory, A circuit that compares a register holding a memory start address with a memory address sent from a CPU of the main memory; forwarding the signal means to the memory when there is a signal means instructing the memory access;
Furthermore, when the memory address is equal to or larger than the main memory start address and there is a signal means for instructing the main memory access, a logic circuit is provided to transfer the signal means to the memory. A main memory protection device in a computer system characterized by: