JPS60117675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60117675A JPS60117675A JP22722483A JP22722483A JPS60117675A JP S60117675 A JPS60117675 A JP S60117675A JP 22722483 A JP22722483 A JP 22722483A JP 22722483 A JP22722483 A JP 22722483A JP S60117675 A JPS60117675 A JP S60117675A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polycrystalline silicon
- protrusions
- polysilicon layer
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 238000010884 ion-beam technique Methods 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims description 40
- -1 argon ions Chemical class 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 4
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- 229910052724 xenon Inorganic materials 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 abstract 8
- 239000011229 interlayer Substances 0.000 abstract 2
- 230000001154 acute effect Effects 0.000 abstract 1
- 238000000992 sputter etching Methods 0.000 abstract 1
- 230000005684 electric field Effects 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001659 ion-beam spectroscopy Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体装置、特に書込み消去特性の優れたＥ
Ｅ Ｐ ＲＯＭ （Ｅｌｅｃｔｒｉｃａｌｌｙ Ｅｒ
ａｓａｂｌｅａｎｄ Ｐｒｏｇｒａ＋ｕ＋ａｂｌｅ Ｒ
ｅａｄ ０ｎｌｙ Ｍｅｍｏｒｙ ）に関するものであ
る。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor device, particularly an electronic device with excellent write/erase characteristics.
E P ROM (Electrically Er
asable and Progra+u+able R
ead 0nly Memory).
従来この種の装置としてその製造方法を第１図に示すも
のがあった。図において、１は半導体基板、２は５ｉ０
２等の絶縁層、３は第１ポリシリコン層、４は５ｉ０２
等の絶縁層、５は第２ポリシリコン層、６は５ｉ０２等
の絶縁層゛、７は第３ポリシリコン層、８はリンガラス
層、９はＡβ電極である。Conventionally, there has been a device of this type whose manufacturing method is shown in FIG. In the figure, 1 is a semiconductor substrate, 2 is 5i0
2 is the insulating layer, 3 is the first polysilicon layer, 4 is 5i02
5 is a second polysilicon layer, 6 is an insulating layer such as 5i02, 7 is a third polysilicon layer, 8 is a phosphor glass layer, and 9 is an Aβ electrode.
実際のＥＥＰＲＯＭでは、Ａｌ１Ｗ１９の上にさらにパ
シベーション層がつけられるが、動作の本質とは関係が
ないので省略しである。In an actual EEPROM, a passivation layer is further added on top of the Al1W19, but it is omitted because it has no relation to the essence of the operation.
次にこの従来のＥＥＦＲＯＭの製造方法と動作について
説明する。まず第１図（ａ）のように、シリコン等の半
導体基板１の上に形成された５ｉ０２等の絶縁Ｎ２上に
、第１ポリシリコンパターン３をフォトリソグラフィ技
術を用いて形成する。第１ポリシリコン層３には、例え
ばリンのような不純物を混入させて適当な導電性を持た
せである。次いでこのポリシリコン層３を９００℃以上
の高温でアニールするとポリシリコングレイン成長する
結果、第１図（ｂｌのように、ポリシリコン３の表面に
凹凸ができてくる。このようにした後に、第１図（Ｃ）
のように、ポリシリコン３の周囲に例えばポリシリコン
３を熱酸化して作った５ｉ０２からなる絶縁層４を１０
００人程度形成し、その上に、一部が第１ポリシリコン
層３と重なるような配置で第２ポリシリコン層５のパタ
ーンを形成する。この第２ポリシリコン層５に対しても
、上記と同様の熱処理を加えて、その表面を第１図（ｄ
）のように凹凸にする。そうしてさらに、第１図（１３
）のようにこの第２ポリシリコン層５のまわりを絶縁層
６で囲んで、その上に、一部が第２ポリシリコン層５と
重なるような形で、第３ポリシリコン層７を形成する。Next, the manufacturing method and operation of this conventional EEFROM will be explained. First, as shown in FIG. 1(a), a first polysilicon pattern 3 is formed using photolithography on an insulating layer N2 such as 5i02 formed on a semiconductor substrate 1 made of silicon or the like. The first polysilicon layer 3 is doped with an impurity such as phosphorus to give it appropriate conductivity. Next, when this polysilicon layer 3 is annealed at a high temperature of 900° C. or higher, polysilicon grains grow, resulting in unevenness on the surface of the polysilicon layer 3 as shown in FIG. Figure 1 (C)
As shown in FIG.
About 0.00 people are formed, and a pattern of second polysilicon layer 5 is formed thereon in such a manner that a portion thereof overlaps with first polysilicon layer 3. This second polysilicon layer 5 is also subjected to the same heat treatment as described above, and its surface is polished as shown in FIG.
) to make it uneven. Then, furthermore, Figure 1 (13
), this second polysilicon layer 5 is surrounded by an insulating layer 6, and a third polysilicon layer 7 is formed thereon so as to partially overlap with the second polysilicon layer 5. .
これ以降は通常のＭＯＳデバイス作成フローと全く同様
に、第１図（ｆ）のように全体にリンガラス層８を形成
して加熱平坦化し、第１図（勢のように第１と第３のポ
リシリコン層３．７にコンタクト穴を設けて、その部分
にＡｌ電極９をつける。第２ポリシリコンパターン５は
Ａｌ電極をつけず、電気的にはフローティングに保たれ
る。From this point on, in exactly the same way as the normal MOS device fabrication flow, a phosphorus glass layer 8 is formed on the entire surface as shown in FIG. A contact hole is formed in the polysilicon layer 3.7, and an Al electrode 9 is attached to the contact hole.The second polysilicon pattern 5 is not attached with an Al electrode and is kept electrically floating.
このようにして形成されたＥＥＦＲＯＭの書込み、消去
動作は次のとおりである。即ち例えば第１ポリシリコン
層３をアースし、第３ポリシリコン層７に正の高い電圧
、例えば２５Ｖを加えると、第２ポリシリコン屓５と第
１ポリシリコンＪｉｔ３の重なり部分にも強、い電界が
加わり、しかも第１ポリシリコン層３表面につけられた
凹凸部分が電界集中して一層強電界となり、酸化膜４の
中をトンネリングによって電子が通り抜けて第２ポリシ
リコン層５の中にためられる。これがＲＯＭの書き込み
に相当する。逆に書き込まれた内容を消去する場合は逆
の電界を加えて、第２ポリシリコン層５中にためられた
余分の電子を吸いとればよい。The writing and erasing operations of the EEFROM thus formed are as follows. That is, for example, if the first polysilicon layer 3 is grounded and a high positive voltage, for example 25V, is applied to the third polysilicon layer 7, the overlapping portion of the second polysilicon layer 5 and the first polysilicon Jit3 will also be strong. An electric field is applied, and the electric field is concentrated on the uneven portions formed on the surface of the first polysilicon layer 3, resulting in an even stronger electric field, and electrons pass through the oxide film 4 by tunneling and are stored in the second polysilicon layer 5. . This corresponds to writing to ROM. Conversely, if the written content is to be erased, a reverse electric field may be applied to absorb the excess electrons stored in the second polysilicon layer 5.
ところで一般的に、第４図を用いて後にも説明するよう
に、凹凸部分での電界強度は突起部の曲率半径に反比例
することが知られているが、従来のＥＥＦＲＯＭでは凹
凸の形成を熱処理時のポリシリコンのグレイン形成で行
っていたためあまり曲率半径を小さくしたような突起は
出来ず、その結果として、従来のＥＥＦＲＯＭでは書き
込み、消去時に２５Ｖといった高電圧が必要で、５ｖ単
一電源の他の素子と同じ電源で動作させられないと同時
に、信頼性の保持も高集積化も共にむずかしいという欠
点があった。By the way, as will be explained later with reference to FIG. 4, it is generally known that the electric field strength at the uneven portion is inversely proportional to the radius of curvature of the protrusion, but in conventional EEFROMs, the unevenness is formed by heat treatment. Since this was done by forming grains of polysilicon at the time, protrusions with a small radius of curvature could not be created, and as a result, conventional EEFROMs required a high voltage of 25V for writing and erasing, and in addition to a single 5V power supply. They had the disadvantage that they could not be operated with the same power supply as other elements, and at the same time, it was difficult to maintain reliability and achieve high integration.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、ポリシリコン等の電極表面をイオ
ンビームでエツチングすることにより、曲率半径の小さ
な突起を多数形成し、電界集中を強くして低電圧でも容
易かつ確実に書き込み、消去ができる半導体装置を提供
することを目的としている。This invention was made in order to eliminate the drawbacks of the conventional ones as described above. By etching the surface of an electrode such as polysilicon with an ion beam, a large number of protrusions with a small radius of curvature are formed, thereby strongly concentrating the electric field. The object of the present invention is to provide a semiconductor device that can be easily and reliably written and erased even at low voltage.
以下、この発明の一実施例を図について説明する。第２
図は、この発明の一実施例による半導体装置の製造方法
を示す断面模式図であり、図において、１０はｉｏ〜３
０ＫｅＶ程度のエネルギーを持つイオンビームである。An embodiment of the present invention will be described below with reference to the drawings. Second
The figure is a schematic cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 10 is io to 3.
It is an ion beam with an energy of about 0 KeV.
第２図（ａ）は従来法の場合と全く同じものを示し、絶
縁層２の上に第１ポリシリコンパターン３が形成されて
いる。この第１ポリシリコン層３に対して、第２図（ｂ
）のようにイオンビーム１０を照射して、表面をスパッ
タエツチングすると、ポリシリコン表面には頂角が約２
０°の円錐状の突起が無数に出来る。この現象が起きる
のは、第３図に示すように、イオンによるスパッタリン
グ収量が入射角依存性を有し、８０°でほぼ最大となる
ことに起因している。照射するイオンとしては、１０〜
３０Ｋｅ■のエネルギーを持つＡｒ”（アルゴンイオン
）やＸｅ十（キセノンイオン）のような希ガスイオンが
最も有効であることも確かめられている。FIG. 2(a) shows exactly the same as the conventional method, in which a first polysilicon pattern 3 is formed on an insulating layer 2. For this first polysilicon layer 3, as shown in FIG.
), when the surface is sputter-etched by irradiating the ion beam 10, the polysilicon surface has an apex angle of approximately 2.
Countless conical protrusions with an angle of 0° are formed. This phenomenon occurs because, as shown in FIG. 3, the sputtering yield by ions has an incidence angle dependence and is approximately maximum at 80°. The ions to be irradiated are 10~
It has also been confirmed that rare gas ions such as Ar'' (argon ion) and Xe (xenon ion) having an energy of 30 Ke■ are the most effective.
このようにして、第１ポリシリコン層３上に鋭い頂角を
持つ凹凸を作った上で、第２図（ｃ＋に示すように、従
来例と同様に眉間絶縁膜４、第２ポリシリコン層５を形
成する。そしてまた、第２図（ｄ）に示すように、第２
図（ｂ）の場合と同様にイオンビーム１０を照射して、
第２ポリシリコン層５の表面にも鋭い突起を作る。この
後は、従来例と全く同様にして、第２図（ｅ）のように
眉間絶縁膜６、第３ポリシリコン層７を形成し、第２図
（ｆｌのように、リンガラスｆｆ１８． Ａｔｔ電極９
を形成してＥＥＦＲＯＭを完成する。In this way, after creating irregularities with sharp apex angles on the first polysilicon layer 3, as shown in FIG. 5. Then, as shown in FIG. 2(d), a second
Irradiate the ion beam 10 in the same way as in the case of Figure (b),
Sharp protrusions are also formed on the surface of the second polysilicon layer 5. After this, in exactly the same manner as in the conventional example, as shown in FIG. 2(e), the glabellar insulating film 6 and the third polysilicon layer 7 are formed, and as shown in FIG. Electrode 9
is formed to complete the EEFROM.
さて、このようにして頂角２０“という鋭い突起をポリ
シリコン表面に持たせると、低電圧、例えば５ｖを加え
ただけでも突起の先端部分では電界集中が起きる結果、
はぼ１０ Ｍ Ｖ ／ｃｍといわれる酸化膜への電子の
トンネリング注入を起こすに充分な電界となって、第２
ポリシリコン層５への電子の注入（書き込み）や過剰電
子の引きぬき（消去）が可能になる。なぜなら、第４図
Ｊこ示すように、棒状で平坦なプラス電極１１とマイナ
ス電極である突起電極１２との間に電圧■を印加した場
合、該突起電極１２の先端部分の電界強度Ｅは、突起の
先端の曲率半径をａとすると、はぼＥｏｃ■／ａ（Ｖは
印加電圧）の関係にあるためで、曲率半径ａを５分の１
にすれば、印加電圧を５分の１に下げても先端部分では
同じ電界強度が得られるためである。Now, when a sharp protrusion with an apex angle of 20" is provided on the polysilicon surface in this way, an electric field will be concentrated at the tip of the protrusion even if a low voltage, for example 5V, is applied.
The electric field is said to be about 10 M V /cm, which is sufficient to cause tunneling injection of electrons into the oxide film, and the second
Injection (writing) of electrons into the polysilicon layer 5 and extraction (erasing) of excess electrons becomes possible. This is because, as shown in FIG. 4J, when a voltage ■ is applied between the rod-shaped flat positive electrode 11 and the negative protruding electrode 12, the electric field strength E at the tip of the protruding electrode 12 is This is because if the radius of curvature at the tip of the protrusion is a, then the relationship is Eoc /a (V is the applied voltage), and the radius of curvature a is 1/5
This is because the same electric field strength can be obtained at the tip even if the applied voltage is reduced to one-fifth.
なお、上記実施例では、ポリシリコンのパターン形成を
終えた後にイオンビーム照射をする場合について述べた
が、フォトリソグラフィによってパターン形成をする前
にイオンビーム照射をして、ポリシリコン表面に突起を
作っておいてもよいことは言うまでもない。In the above example, the case was described in which ion beam irradiation was performed after pattern formation of polysilicon, but ion beam irradiation was performed before pattern formation by photolithography to create protrusions on the polysilicon surface. Needless to say, you can leave it as is.
以上のように、この発明に係る半導体装置によれば、ポ
リシリコン等の電極の表面にイオンビームエツチングに
よって曲率半径の小さな突起を多数形成するようにした
ので、非常に低い電圧で書き込み、消去のできるＥＥＰ
ＲＯＭが得られるという著しい効果がある。As described above, according to the semiconductor device of the present invention, a large number of protrusions with a small radius of curvature are formed on the surface of an electrode made of polysilicon or the like by ion beam etching, so that writing and erasing can be performed with a very low voltage. EEP that can be done
This has the remarkable effect of providing ROM.
第１図は従来のＥＥＦＲＯＭの製造方法を示す断面側面
図、第２図はこの発明の一実施例によるＥＥＰＲＯＭの
製造方法を示す断面側面図、第３図はイオンビームのス
パッタリング収量の入射角依存性の実験データを示す図
、第４図は突起部において電界集中が起きることを説明
するための図である。
１は半導体基板、２は絶縁層、３は第１ポリシリコン層
、４は絶縁層、５は第２ポリシリコン層、６は絶縁層、
７は第３ポリシリコン層、８はリンガラス層、９はＡＪ
組電極１０はイオンビーム、１１はプラス電極、１２は
マイナス電極である突起電極。
なお、図中同一符号は同−又は相当部分を示す。
代理人 大岩増雄
第１図
第１図
第２図
第２図FIG. 1 is a cross-sectional side view showing a conventional EEFROM manufacturing method, FIG. 2 is a cross-sectional side view showing an EEPROM manufacturing method according to an embodiment of the present invention, and FIG. 3 is an incident angle dependence of ion beam sputtering yield. FIG. 4 is a diagram illustrating the fact that electric field concentration occurs at the protrusion. 1 is a semiconductor substrate, 2 is an insulating layer, 3 is a first polysilicon layer, 4 is an insulating layer, 5 is a second polysilicon layer, 6 is an insulating layer,
7 is the third polysilicon layer, 8 is the phosphorus glass layer, 9 is AJ
The set of electrodes 10 is an ion beam, 11 is a positive electrode, and 12 is a negative electrode, which are projecting electrodes. Note that the same reference numerals in the figures indicate the same or equivalent parts. Agent Masuo OiwaFigure 1Figure 1Figure 2Figure 2
Claims (1)
小さな多数の針状突起が形成された電極を備えたことを
特徴とする半導体装置。 （２）上記イオンビームとして、１０〜３０ＫｅＶのア
ルゴンイオン、キセノンイオン等の希ガスイオンを用い
たことを特徴とする特許請求の範囲第１項記載の半導体
装置。 （３）上記電極が、ポリシリコンからなることを特徴と
する特許請求の範囲第１項又は第２項記載の半導体装置
。Claims: (l) A semiconductor device comprising an electrode on the surface of which a large number of needle-like protrusions with a small radius of curvature are formed by irradiation with an ion beam. (2) The semiconductor device according to claim 1, wherein rare gas ions such as argon ions and xenon ions of 10 to 30 KeV are used as the ion beam. (3) The semiconductor device according to claim 1 or 2, wherein the electrode is made of polysilicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22722483A JPS60117675A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22722483A JPS60117675A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60117675A true JPS60117675A (en) | 1985-06-25 |
| JPH0363829B2 JPH0363829B2 (en) | 1991-10-02 |
Family
ID=16857440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22722483A Granted JPS60117675A (en) | 1983-11-29 | 1983-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60117675A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136880A (en) * | 1985-12-11 | 1987-06-19 | Fujitsu Ltd | Semiconductor memory device and manufacture of the same |
| JPH01241177A (en) * | 1988-03-23 | 1989-09-26 | Toshiba Corp | Nonvolatile semiconductor storage device and manufacture thereof |
| JPH0611563U (en) * | 1992-07-17 | 1994-02-15 | 株式会社アオイ工芸社 | Scented picture frame |
-
1983
- 1983-11-29 JP JP22722483A patent/JPS60117675A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62136880A (en) * | 1985-12-11 | 1987-06-19 | Fujitsu Ltd | Semiconductor memory device and manufacture of the same |
| JPH01241177A (en) * | 1988-03-23 | 1989-09-26 | Toshiba Corp | Nonvolatile semiconductor storage device and manufacture thereof |
| JPH0611563U (en) * | 1992-07-17 | 1994-02-15 | 株式会社アオイ工芸社 | Scented picture frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0363829B2 (en) | 1991-10-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2631186B2 (en) | Memory device | |
| JP3431367B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| US6914290B2 (en) | Split-gate type nonvolatile memory devices | |
| JP2585180B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| JPH01248670A (en) | Nonvolatile semiconductor storage device, and operation and manufacture thereof | |
| US5625213A (en) | Top floating-gate flash EEPROM structure | |
| US5972750A (en) | Nonvolatile semiconductor memory device and manufacturing method of the same | |
| JPS60117675A (en) | Semiconductor device | |
| JP2904498B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| JPH02284473A (en) | Semiconductor integrated circuit device and its manufacture | |
| JPH0640587B2 (en) | Semiconductor memory device | |
| JP2637149B2 (en) | Manufacturing method of nonvolatile semiconductor memory device | |
| KR100836426B1 (en) | Non-Volatile Memory Device and fabrication method thereof and apparatus of memory including thereof | |
| JPH04221857A (en) | Nonvolatile memory | |
| JPS5821368A (en) | Manufacture of erasable and programmable read only memory | |
| JPS61225872A (en) | Semiconductor nonvolatile memory device and manufacture thereof | |
| JPH0685280A (en) | Manufacture of nonvolatile semiconductor device | |
| US5737264A (en) | Non-volatile semiconductor memory cell | |
| TWI710113B (en) | Operation method of electronic writing erasable rewritable read-only memory | |
| KR100493004B1 (en) | Non volatile memory device having improved program and erase effeciency and fabricating method therefor | |
| JPH0529587A (en) | Nonvolatile semiconductor memory and manufacture thereof | |
| US5360756A (en) | Method of manufacturing a semiconductor device having a monocrystal silicon layer | |
| JP3139165B2 (en) | Method for manufacturing nonvolatile memory cell | |
| JPH02128477A (en) | Nonvolatile memory device | |
| JPH0227773A (en) | Manufacture of nonvolatile semiconductor memory |