JPH02284473A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor integrated circuit wherein the deterioration of a gate insulating film and the irregularity of erasing characteristics between bits can be prevented, by rounding the lower side corners of end- portions of a floating gate electrode, and preventing the concentration of electric field at the corner parts. CONSTITUTION:A flash type nonvolatile memory element Qm is constituted on the main surface of a P-type well region 3 in a region whose periphery is defined by an element isolation insulating film 4 and a channel stopper region 5. The element Qm is composed of the following; a P-type well region 3, a first gate insulating film 6, a floating gate electrode 7, a second gate insulating film 8, a control gate electrode 9, and a source and drain region. The lower side corner parts 7E of both end-portions of the electrode 7 are rounded. By using the structure wherein the corner parts 7E are rounded in this manner, the concentration of electric field at the corner parts can be prevented, so that dielectric breakdown of the insulating film at edge parts of the electrode 7 can be prevented and the erasing and writing frequency of an EEROM can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a technique that is effective when applied to a semiconductor integrated circuit device having a nonvolatile memory circuit.

[Conventional technology]

A single-element type nonvolatile memory cell has been proposed as an electrically erasable read-only nonvolatile memory cell.This nonvolatile memory cell has a floating gate electrode (gate electrode for information storage) and a control electrode (gate electrode for control It is composed of a field effect transistor MI 5FET with an electrode). The source region of this MISFET is connected to a source line, and the drain region is connected to a data line.

The non-volatile memory cell is a 7-flush cell.
) type nonvolatile memory cell, and is constructed of a hot electron insertion type and a tunnel erase type; r'.

In other words, the information writing operation of a nonvolatile memory cell is performed by generating hot electrons in a high electric field near the drain region and injecting these hot electrons into the information storage gate electrode. On the other hand, in the information erasing operation of a non-volatile memory cell, electrons accumulated in the information storage gate electrode are sent to the source region through the forward-nord
heirn t3'pe's tune 1 i ng
This is done by emitting it.

E, which is composed of one flash type non-volatile memory cell,
As mentioned above, the EFROM is a one-element type device and the cell area can be reduced6, so it has the characteristic of being able to increase the capacity.

Regarding the EEFROM mentioned above, the 1988 I
E E E International 5ol
id-8tate Circuits Conference
ce pp 132. 133 and 330
j'H has been done.

[The question that the invention attempts to solve]

As a result of inspecting the above-mentioned EEFROM, the inventor found that the following problems occurred.

In other words, there have been problems such as poor reliability due to large variations in erase characteristics between memory cells and the relatively small number of times that it can be repeatedly rewritten.

The erase characteristics largely depend on the shape of the floating gate electrode, especially at its ends. The electric field applied between the floating gate electrode and the source region during erasing is 1
0"V/m or more, but the intensity distribution is not uniform (due to the so-called edge effect, the edge of the gate electrode,
In particular, they tend to be concentrated in corner areas. Therefore, slight variations in the shape of the gate electrode cause large variations in the erasing characteristics.

Furthermore, if the applied electric field during erasing is concentrated in a specific location, the area where the electric field is concentrated will be prone to breakdown or deterioration. For this reason, the number of times the erase voltage is applied, that is, the number of repeated replacements is reduced.

Further, since the source region is formed by a self-alignment ion implantation process with respect to the floating gate electrode and the control gate electrode, the overlapping region between the source region and the floating gate electrode cannot be made sufficiently large. Therefore, large variations in erase characteristics occur due to process variations.

Further, the arsenic ion implantation for forming the source region described above is performed through an insulating film, such as a thermal oxide film, which may not be provided on the surface of the semiconductor substrate. At this time, oxidation occurs at the extreme end of the floating shield, and dangling bonds are generated in the film. Due to this dangling bond, a leakage current flows between the unloading gate ti1m and the source region.
The pressure between the floating gate electrode and the source region is reduced, and the number of repetitions of refilling is reduced. Furthermore, the aforementioned leakage current causes variations in erase characteristics between memory cells.

An object of the present invention is to provide a technology that reduces variation in erasing characteristics between memory elements and increases the number of times that it can be repeatedly rewritten, thereby making it possible to create a highly reliable nonvolatile memory element. The above-mentioned and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

I would like to provide an overview of representative inventions disclosed in this application (as follows).

In other words, an electric field buffering means is provided for relaxing the electric field generated between the source region and the end of the floating gate electrode when an erase voltage is applied.

In addition, the first
A conductive layer and a second isoelectric layer for forming a control gate electrode are formed, and at least one of the source region and the drain region is formed by self-alignment using the control gate electrode as a mask, and then the control gate electrode is formed. A floating gate electrode is formed by forming a sidewall spacer that extends laterally on the side of the gate electrode, and by self-aligning the sidewall spacer and the control gate electrode as a mask.

Further, arsenic ions are implanted into the floating gate electrode and the control gate electrode in a self-aligned manner to form a source region, and then thermal oxidation treatment is performed.

[Effect]

The above means prevents the applied electric field during erasing from concentrating on the edge of the floating gate electrode, and allows electron tunneling to occur in a flat part away from the edge of the gate electrode. .

As a result, it is possible to achieve the objectives of reducing variations in erase characteristics between memory cells, increasing the number of times that the memory cell can be repeatedly erased, and realizing a highly reliable nonvolatile memory cell.

In addition, the above-mentioned method makes it possible to increase the overlapping area between the source region or drain region and the floating gate while using self-alignment microfabrication technology without forcing unnecessary stretching and diffusion processing. I can do it.

As a result, by using a process that has excellent reproducibility and controllability and allows microfabrication through self-alignment, it is possible to reduce variations in erase characteristics, increase the number of times that can be rewritten, and create highly reliable nonvolatile memory cells. The purpose of making it possible is achieved.

Furthermore, the above-described means can reduce redundant bonds in the insulating film between the end of the floating gate electrode and the source region.

This makes it possible to prevent a decrease in breakdown voltage between the floating gate electrode and the source region, increase the number of rewriting cycles, and achieve the purpose of preventing variations in erase characteristics between memory cells.

〔Example〕

FIG. 1 is an equivalent circuit diagram of a part of the memory cell array and O/peripheral circuit of an EEFROM to which the present invention is applied;
The figure is a plan view of a part of the memory cell play.

An outline of the EEPROM will be explained using FIG.

Memory cell Qm consists of a MISFET having a floating gate electrode and a control gate electrode. M.I.
The control gate electrode of SFETQm is connected to the word line WL.
connected to. The drain region of MISFETQm is connected to data line DL, and the source region of MISFETQm is connected to ground potential line GL. Data line DL and ground line G
L are parallel to each other, and in the direction intersecting the word line WL,
It is formed. In other words, the memory cell array includes a memory cell Qm, a word line WL, a data line DL, and a ground line GL.
Consisting of

One end of the word line WL is connected to an X decoder X-DEC, which is a word line selection circuit. One end of the data line DL is
The data line DL is connected to the drive circuit DR, and the other end of the data line DL is connected to the drive circuit DR.
n-channel MISFET that forms a column switch circuit
It is connected to input/output circuits DOB and DIB through Qc. The output of a Y-decoder, Y-DEC, which is a data line selection circuit, is supplied to the gate electrode of the M, ISFETQc.

The ground line GL has a p-channel M I S F E T
Q B and n-channel M I S F E T Q B
The output of a CMOS inverter circuit IV consisting of t is supplied. Input terminal of inverter circuit IV -) MIS
An erase signal φE is supplied to the gate electrodes of FETQ s I and Qst. Output circuit D including sense amplifier circuit
OB is a selected data line DL in a read operation.
It amplifies the signal given to and outputs it to the input/output external terminal I10. In a write operation, the input circuit DIB supplies the signal supplied to the external terminal to the data line DL.

Circuits other than the memory cell array, that is, peripheral circuits, are comprised of 0M08 circuits, such as the inverter circuit (IV), and operate statically.

Writing, reading, and erasing of this EEPROM are performed as follows.

The inverter circuit IV is turned on by the high level of the signal φE.
n L, through MISFET QS2, the circuit ground potential VSS, for example Ov, is applied to the ground line GL during information write and read operations, and when information is erased, the erase potential Vp p @ is applied through MISFET QsI, which is turned on by the low level of signal φE. , -z applies 12V.

When erasing information, for example, 1 is applied to VPP of inverter circuit IV.
With 2V applied and the ground line GL set to 12V, all the word lines WL and all the data lines DL are brought to a low level by the circuits X-DEC and Y-DEC that receive the signal φE.

That is, in this embodiment, the contents of all memory cells Qm are erased at once.

In the write operation, the power supply potential VC is applied from the write circuit DIB to one data line DL selected by Y-DEC.
C (for example, 5V) is supplied. Prior to this, all data lines DL are precharged to the circuit ground potential Vss (for example, Ov) by the drive circuit DR. In the read operation, all data lines DL are connected to the drive circuit DR.
It is precharged to the power supply potential VCC in advance. Thereafter, a potential according to the memory of the selected memory cell Qm appears on the data line DL.

In a write operation, one selected word line WLK
, a high m voltage Vpp (for example, 12 .mu.) with a power supply voltage of 700 or more is supplied from the decoder X-DEC.

In the read operation, a no-level signal of power supply voltage VCC (or lower) is applied from the decoder X-DEC to the selected word line WL.

When the threshold 11α of the MISFET of the memory cell Qm is lower than the selection level of the word line WL, M I S i”
By turning on ET Qm, the potential of the data line DL or the potential v
Decrease from cc. If the threshold value of MISFETQm is higher than the selection level of word line WL, MISFETQm
By turning off the data line DL, the data line DL maintains the precharge level.

Note that the favorable operation, that is, injection of hot carriers, is performed when the word line W L Vc potential VPP and the data line DL have a potential V
This is performed only in one memory cell to which CC is applied. No hot carriers are injected into other memory cells.

Further, the voltage VPP may be supplied from an external terminal during a write operation, or may be generated from the power supply voltage VCC by a built-in booster circuit.

FIG. 3 shows the P channel and N channel constituting the memory cell and peripheral circuit of the EBPROM in the first embodiment of the present invention
3 is a cross-sectional view of the channel MISFET, and the memory cell portion is a cross-sectional view taken along the line A-AK in FIG. 2. FIG.

As shown in FIG. 3, the EEPROM is composed of a p-type semicircular substrate 1 made of single crystal silicon.

In the formation region of the flash type nonvolatile memory cell Qm and the N-channel MISFET Qn, a p-type well region 3 is provided on the main surface of the semiconductor substrate 1, and a p-type well region 3 is provided in the formation region of the P-channel MISFET Qp. ('i, an n-type well region 2 is provided.

In the element formation region [↑;j, the n-type well region 2゜p
An insulating film 4 for element isolation is provided on each main surface of the mold well region 3.
is not thrown. A p-type channel stopper region 5 is provided on the main surface of the p-type well region 3 under the element isolation insulating film 4, and is located at +-.

The Franchy type nonvolatile memory element Qm is formed on the main surface of the p-type well region 3 in a region defined by the element isolation insulating film 4 and the channel hole region 5. In other words, the flash type non-volatile memory element Q
m is the p-type well region 3° first gate insulation moon Q6. )・
-・- ding gate electrode 7, second gate insulating film 8. Control gate electrode 9. It consists of a source region and a drain region. This flash type nonvolatile memory element Qm is composed of an n-channel field effect transistor, and is composed of one element.

The p-type well region 3 is used as a channel forming region.

The first gate insulating film 6 is formed of a silicon oxide film formed by oxidizing the surface of the p-type well region 3.

The first gate insulating film 6 is, for example, 100 to 15 o[:A]
It is formed with a film thickness of approximately

The floating gate electrode 7 is formed of, for example, a polycrystalline silicon film doped with n-type impurities.

The second gate insulation film 8 is formed of, for example, a silicon oxide film obtained by oxidizing the surface of the floating gate electrode 7 (polycrystalline silicon film). The second gate insulating film 8 is, for example, 200 to 25
The film thickness is approximately 0.0 (A).

The control gate electrode 9 is formed of, for example, a polycrystalline silicon film doped with n-type impurities. Also :ln)
Low/l/gate electrode 9 is made of W, Ta, Ti
.

It may be formed of a single layer of a high melting point metal film such as Mo or a high melting point metal silicide film, or a composite film in which these metal films are laminated on a polycrystalline silicon film, that is, polycide. This control gate electrode 9 is formed integrally with the control gate electrodes 9 of other seven Lanci type non-inductive memory elements Qm arranged adjacently in the gate width direction, and forms a word line (WL). ing.

The source region is composed of an n-type semiconductor region 11 with a high impurity concentration and an n-type semiconductor region 12 with a low impurity concentration.

The n-type semiconductor region 12 is provided around the outer periphery of the n + -type semiconductor region 11 . In other words, the source region has a so-called double diffusion structure. The high impurity concentration n+ type semiconductor region 11 is configured mainly to increase the impurity concentration and deepen the junction depth. The n-type semiconductor region 12 with a low impurity concentration is mainly configured to increase the junction depth. In other words, the source region has a high voltage applied between it and the control gate electrode 9 during an information erasing operation. SaJ
In this case, the impurity concentration is increased in the n+ type semiconductor region 11 to prevent the surface from becoming depleted. Also, the source area is
By using the high impurity concentration n+ type semiconductor region 11 or the low impurity concentration n type semiconductor region 12 or both, the amount of diffusion (diffusion distance) toward the channel forming region side is increased, and the overlapping area (overlapping area) of the 70-ding gate electrode 7 is increased. 71→ is increased to increase the tunnel area during the information erasing operation. Each of the semi-regions 11 and 12 is formed in self-alignment with the gate electrodes 7 and 9.

The drain region is an n+ type semiconductor region 1 with high impurity concentration.
It consists of 4. This n+ type semiconductor region 14 includes a floating gate electrode 7 and a control gate electrode 9.
It is formed by self-alignment.

A p-type semiconductor region 13 with a high impurity concentration is provided on the main surface of the semiconductor substrate 1 along the outer periphery of the drain region. The p-type semiconductor region 13 is configured to increase the electric field strength near the drain region, particularly to promote the generation of hot electrons in the flash type nonvolatile memory element Qm in the selected state during the information write operation, and to improve the information write efficiency. has been done.

The peripheral circuit is composed of an 0M08 circuit in which an N-channel MISFETQn and a P-channel MISFETQp are connected in series. N-channel MISFETQn and P-channel MISFETQP each have a low impurity concentration region 15.
(n), 16 (p) and high impurity concentration region 18
(n”) p 19 (p”) Additional source
LDD (Lightly
-Doped -Drain).

The low impurity concentration regions 15 (6) and 16 (P) are formed in self-alignment with each gate electrode 9, and the high impurity concentration regions 18 (n'') and 19 (p'') are formed as follows.
It is formed in self-alignment with each gate electrode 9 and the sidewalls 170 provided at both ends thereof. Furthermore, the gate electrodes 9 of these N-channel MIsFETQn and P-channel MISFETQp are formed in the same layer as the control gate electrode 9 of the Franchy type transistor [[memory cell Qm.

A wiring 23 made of an aluminum alloy film is connected to the n+ type conductor region 14, which is the drain region of the flash type 2 nonvolatile memory cell Qm, and this wiring 23 functions as a data line DL.

Furthermore, wiring 23 is also connected to the source/drain regions of the N-channel and P-channel MI 5FETB Qn, Qp forming the peripheral circuit, as necessary. The wiring 23 extends on the interlayer insulating films 20 and 21 and passes through the connection hole 22 formed in the interlayer insulating films 20 and 21 to connect p+ type,
It is attached to the n+ type semiconductor region.

FIG. 4 shows an enlarged view of the flash type nonvolatile memory cell Qm shown in FIG. 3. Although ψJ is not precise in FIG. 3, the lower corner portions 7E of both ends of the floating gate electrode 7 are rounded. By forming the corner portions 7E of the floating gate electrode 7 into a rounded structure as described above, electric field concentration at the corner portions can be prevented, and dielectric breakdown of the insulating film at the edge portions of the floating gate electrode 7 can be prevented. , EEPROMI17) The number of times of erasing and writing can be increased.

Further, a method for rounding the corner portion 7E in this manner will be described later.

Next, a method for manufacturing the EEF ROM will be briefly explained using FIGS. 5 to 19 (cross-sectional views of main parts shown for each backing process).

First, a p-type semiconductor substrate l is prepared.

Next, an n-type well region 2 is formed on the main surface of the semiconductor substrate 1 in the formation region of the p-channel MISFET Qp. The n-type well region 2 has, for example, 1 x 10 to 3
It is formed by ion implantation of an impurity of approximately X 1013 (atoms/i), for example p+, at an energy of 10 t) to 150 KeV. Thereafter, in the formation regions of the Furanosee type non-volatile memory element Qm and the n-channel MISFET Qn, for example, 5X 101
2 to I.times.1013 (atoms/CI!: 3) impurity, for example BF2+, is ion-implanted at an energy of 50 to 70 KeV to form the p-type Riel region 3.

Next, n-type well region 2. An element isolation insulating film 4 of about 6000 to 8000 Å is formed on each main surface of the p-type well region 3, and a p-type channel stopper region 5 is formed on the main surface of the p-type well region 3.

Next, as shown in FIG. 5, in the semiconductor element formation region, an n-type well region 2. A first gate insulating film 6 having a thickness of about 100 to 150× is formed on each main surface of the p-type well region 3 .

Next, a conductive film 7 is formed on the entire surface of the substrate including the top of the first gate insulating film 6.
A is formed to about 2000 to 3000A. Conductive film 7
A is formed of, for example, a polycrystalline silicon film deposited by the CVD method. An n-type impurity, such as P, is introduced into this polycrystalline silicon film to lower its resistance. Thereafter, as shown in FIG. 6, the conductive film 7A is patterned into a predetermined shape. The conductive film 7A remains only in the formation region of the flash type nonvolatile memory cell Qm, and the conductive film 7A has a defined dimension in the channel width direction.

Next, a second gate insulating film 8 is deposited on the surface of the conductive film 7A in the formation region of the 7-layer nonvolatile memory cell Qm.
Approximately 00 to 2508 is formed. By substantially the same manufacturing process as this step, a second gate insulator IDA 8 is formed on each main surface of the p-type well region 3 in the formation region of the n-channel MISFETQn and the n-type well region 2 in the formation region of the P-channel MISFETQP. Form. Thereafter, as shown in FIG.
A of about 1000 to 1500A is formed. The conductive film 9A is formed of, for example, a polycrystalline silicon film deposited by a CVD method. An n-type impurity, such as P, is introduced into this polycrystalline silicon film to lower its resistance.

Next, in the formation region of the flash type nonvolatile memory cell Qm, the conductive films 9A and 7A are sequentially patterned to form the control gate 14119 and the floating gate electrode 7. This patterning is RIE
This is done using a so-called overlap cutting technique using anisotropic etching such as. Thereafter, the conductive area [9A] of the peripheral circuit element formation region is patterned to form the control gate electrode 9.

Here, this control gate electrode 9 is connected to the word line WL
Since it is formed integrally with the polycrystalline silicon film, Ta and Ti are used instead of the polycrystalline silicon film to reduce the resistance of the word and IJWL.

It may be formed by a single layer of a high melting point metal such as W, M (, etc.) or a silicide film of these high melting point metals, or a polycide film in which a high melting point metal silicide film is laminated on polycrystalline silicon IIQ. The entire surface is subjected to oxidation treatment, and as shown in FIG. 8, an insulating film 10 of about 70 to 80 Å is formed on the semiconductor substrate to cover each surface of each gate electrode 7.9.

Next, an impurity introduction mask 30 is formed in which the region for forming the source region of the flash type nonvolatile memory cell Qm is opened. The impurity introduction mask 30 is formed of, for example, a photoresist film. Thereafter, as shown in FIG. 9, using the impurity introduction mask 30, an n-type impurity 12n is introduced into the main surface of the p-type well region 3, which will be the formation region of the source region. The n-type impurity 12n is, for example, 1×10 14 to I
X1olsCatOmS/c! ] impurity concentration of about P
It is introduced by an ion implantation method using ions with an energy of about 50 [KeV:]. This n-type impurity 12n is
It is introduced in self-alignment with respect to the floating gate electrode 7 and the control gate electrode 9.

Then, the impurity introduction mask 30 is removed.

Next, a mask 31 for impurity introduction is formed in which a region for forming the drain region of the seven Lashini type nonvolatile memory cell Qm is opened. The impurity introduction mask 31 is formed of, for example, a photoresist film. After that, as shown in FIG. 10, using the impurity introduction mask 31, a p-type impurity 13 is injected into the main surface of the p-type well region 3, which will be the formation region of the drain region.
Introducing p. The p-type impurity 13p is, for example, 5×1
Using BF and ions with an impurity concentration of about 0" to 1.s x 1014 (atoms/i), 60 (KeV)
It has been introduced by ion implantation method with a certain amount of energy. The p-type impurity 13p is introduced into the floating gate electrode 7 and the control gate electrode 9 in a self-aligned manner. Then, the impurity introduction mask 31 is removed.

Next, the introduced n-type impurity 12n is subjected to heat treatment at about 1000 ('C) in a nitrogen gas atmosphere.

Stretching and diffusion is applied to each of the p-type impurities 13p.

Due to the diffusion of the n-type impurity 12n, the n-type semiconductor region 1
2 can be formed. The n-type semiconductor region 12 has approximately 0
．． It is formed with a deep junction depth of about 5 [μm].

Due to the diffusion of the p-type impurity 13p, a low impurity concentration p
A type semiconductor region 13 can be formed. The p-type semiconductor region 13 is formed with a deep junction depth of about 0.3 to 0.5 [μm].

Next, an impurity introduction mask 32 having an opening in the formation region of the flash type nonvolatile memory element Qm is formed. The impurity introduction mask 32 is formed of, for example, photoresist l. Thereafter, as shown in FIG. 11, using an impurity introduction mask 32 in which a region for forming the source region of the flash type nonvolatile memory cell Qm is opened, the main surface of the p-type well 3, which will be the region for forming the source region, is An n+ type impurity 11n+ is introduced into. The n+ type impurity 11n+ is, for example, 5X10"
Using ~1x1016 atoms/i of As ions, 6
It is introduced by ion implantation with an energy of about 0 KeV. The n+ type impurity 11n+ is introduced into the floating gate electrode 7 and the control gate electrode 9 in a self-aligned manner. Then, the impurity introduction mask 32 is removed.

Next, as shown in FIG. 12, using the impurity introduction mask 33 in which the drain region formation region of the flash type nonvolatile memory cell Qm is opened, the main surface of the p-type well 3, which will be the drain region formation region, is exposed. An n+ type impurity 14n+ is introduced. The n+ type impurity 14n+ is, for example, I
A of about 15-5 x 10”atoms/cIft
S ions are introduced by ion implantation with an energy of about 60 KeV. ? The molded blunt material 4n+ is introduced in self alignment with the floating gate electrode 7 and the control gate electrode 9.

Here, we have explained the case where the n+ type impurity 11n'' 14n+ is introduced in a separate process.
In order to make 14n+ equal impurity concentration,
They may be introduced at the same time.

Next, heat treatment is performed at about 1000° C. in a nitrogen gas atmosphere to stretch and diffuse each of the introduced n+ type impurities 11n+14n+. By this heat treatment, the n-type impurity regions 11 (n") and 14 (n") have a junction depth of about 0.3 μm.

Next, as shown in Fig. 13, the N-channel MISFET
An n-type impurity 15n is introduced into the main surface of the p-type well 3 at both ends of the gate electrode 90 of the N-channel MISFET Qn in self-alignment with the gate electrode 9 using an impurity introduction mask 34 with an opening in the Qn formation region. This n-type impurity 15n
For example, I X 1013-5 X 10I3ato
P ions of rns/7 are introduced by ion implantation with an energy of about 50 KeV.

Next, as shown in FIG.
Using an impurity introduction mask 35 with an opening in the QP formation region, a p-type impurity 16p is introduced into the main surface of the N-type well 2 at both ends of the gate vL pole 9 of the P-channel MISFET QP in self-alignment with the gate electrode 9. This p-type impurity 16
P is, for example, 5×1012 to I×1013at
oms/cr! BF2 ion wo 60 K e V 8
It is introduced by implanting ions with a certain amount of energy.

Next, as shown in FIG. 15, the insulating film 10 on the surface is removed by wet etching. This etching solution is, for example, a mixture of hydronic acid and water, with a mixing ratio of 1:99. Through this process, the flash type non-volatile memory cell Q
The insulating film on the surface of the source/drain region of m, where a dangling bond is formed by the ion implantation of As ions of n+ type impurity 11n+14n+, is removed.

Next, as shown in FIG. 16, a new insulating film 10', for example, an oxide film, is applied to the flash type nonvolatile memory cell Qm by performing oxidation treatment for about 20 minutes while supplying oxygen in a furnace at a temperature of about 900°C. A thickness of approximately 400 to 500 mm is formed on the surfaces of the source/drain regions of the insulating film, and at this time, an insulating film of approximately the same thickness is also formed on the surfaces of the floating gate electrode 7 and the control electrode 9.

Through this oxidation process, the flash type non-volatile memory cell Q
The corner portions at both ends of the floating gate electrode 70 are rounded as shown in FIG.

In addition, M I S F E'l' by heat treatment
Qn, QpOn type impurity 15n, and p type impurity 16p are stretched and diffused, and both have a junction depth of about 01 to 02 μm.

Next, as shown in FIG. 17, sidewall spacers 17 are formed on each sidewall of each gate electrode 7.9. The side wall spacer 17 is CV I on the entire surface of the board.
) method to deposit a silicon oxide film, and perform anisotropic etching such as RIE over the entire substrate by a thickness corresponding to the thickness of the deposited film.

Next, by the anisotropic etching, the n-type well region 2
．． Since the main surfaces of the p-type well region 3 and the like are exposed, oxidation treatment is performed to cover those surfaces with a thin silicon oxide film.

Furthermore, as shown in FIG.
A mask for impurity concentration with an opening in the TQn portion is formed, and the n
Introduce + type impurity. This n+ type impurity is, for example, 5
By using an ion implantation method using As ions with a high impurity concentration of about X 10 '' [atoms/CrI) and an energy of about 60 [K e V ), .↓λ people have been achieved.

Next, an impurity introduction mask with an opening in the formation region of the p-channel MISFETQp is formed. Then, using this unspecified substance introduction mask, a p-type impurity 19p+ is introduced into the main surface portion of the p-type semiconductor region 16. The p-type impurity is
For example, BF and ions with a high impurity concentration of about 2×101s [atoms/ff1] are used and are introduced by an ion implantation method with an energy of 60[KeVI8 degrees]. ? 'fJ p+ type semi-integrated region 19 is formed in self-alignment with gate electrode 9 and sidewall 17.

Furthermore, after this, by annealing at about 850°C, the n+ type impurity 18n" and the p type impurity 19p+ are stretched and diffused to form an n+ type having a junction depth of about 0.2 to 03 μm, as shown in FIG. Semiconductor region 18 (n”
)* A p+ type semi-dedicated region 19 (p+) is formed.

Next, interlayer insulating films 20 and 21 are formed on the entire substrate. Interlayer insulation +1! ,! 20 is an oxide film with a thickness of about 1500A formed by thermal decomposition of Mankisilane, and the interlayer insulation film 21 is an oxide film with a thickness of 5000 to 6000A formed by CVD method, for example.
o) BPSGJIA. And said! - After forming the connection hole 22 in the interlayer insulating film 0.21 and applying glass flow to the interlayer insulating film 21, as shown in FIG.
Form 3 begs. By performing these series of manufacturing steps, the EEFROM of this embodiment is completed. Although not shown, a passivation film is provided above the wiring 23.

In this example, as explained in Fig. 15 and Fig. 16, after the insulating film was removed, oxidation was performed and an insulating film was formed again. Just go. The reason for this is thought to be that oxygen is supplied by the oxidation treatment to the dangling bonds generated by ion implantation, and the dangling bonds disappear or decrease.

Furthermore, leakage current can be similarly prevented or suppressed even if the film is partially removed and then incubated.

FIG. 20 does not show a schematic structure of a flood-type nonvolatile memory cell according to a second embodiment of the present invention.

To explain the differences from the first embodiment described above,
In the flash S-type nonvolatile memory cell according to the second embodiment shown in the figure, the floating gate voltage la! , 7 in the vicinity of the surface of the source region 110, the electric field generated between the source region 11 and the end of the floating gate electrode 7 when an erase voltage is applied is reduced. An electric field buffer means for relaxing the electric field is formed.

In other words, the electric field is relaxed by making it easier for the depletion layer to extend on the surface of the source region 11 under the end of the pole 7 of the floating gate.

This low-concentration region 24 may partially reduce the amount of doping of fine particles without imparting conductivity within the source region 11, or as shown in FIG.
It is formed by selectively implanting ions of impurity imparting charge to a depth of about 0.15 μm.

When the low concentration region 24 as described above is provided, a large depletion layer only partially expands in the low concentration region 24 under the end of the floating gate electrode 7 due to the electric field applied during erasing. This expansion of the depletion layer corrects the tendency for the electric field to concentrate near the end of the floating gate 'FJfL pole 7.

As in the case of the first embodiment described above, this allows a structure obtained through a relatively simple manufacturing process to reduce variations in erasing characteristics between memory elements.
It becomes possible to increase the number of times that it can be repeatedly rewritten.

FIG. 22 shows a third embodiment of the present invention, which differs from the first embodiment in the structure of a flash type nonvolatile memory cell Qm. The structure and manufacturing method of the peripheral circuits are the same.

Therefore, parts corresponding to those in the first embodiment are denoted by the same reference numerals.

The flash type non-volatile memory cell shown in the figure is a MISFET similar to the first embodiment, and includes a floating gate electrode 7 provided on a semiconductor substrate 1 with a first gate insulating film 6 in between, and a A control gate electrode 9 is provided on the gate electrode 7 with a second gate insulating film 8 in between, and a control gate electrode 9 is formed below the floating gate electrode 7 and is spaced apart from each other and partially overlaps with the floating gate electrode 7. source area 1
1.12, the drain region 14, etc. Here, a sidewall spacer 17 is provided on the side of the control gate electrode 9. The floating gate electrode 7 is formed using the end of the sidewall spacer 17 as a reference. This results in
The side part of the control gate electrode 9 is formed to be set back from the side part of the floating goo 1 pole 7.

In this way, the side portions of the control gate electrode 9 are formed to be recessed inward from the side portions of the floating gate electrode 7, and the tips of the source region 11, 12 and the drain region 14 are respectively connected to the control gate electrode. By reaching below the sides of 9, the source region 11
．． A relatively large overlapping portion is formed between the floating gate electrode 12 and the drain region 14 and the floating gate electrode 7 with good reproducibility and controllability.

In this case, the dimension of the floating gate electrode 70 at one end is 0.2 to 0.3 larger than the dimension of the control gate electrode 9 due to the sidewall spacer 17.
As thick as μm (set).

Further, the film thickness of each layer of the flash type nonvolatile memory cell Qm is the same as in the first embodiment.

In the nonvolatile memory element configured as above, first,
Since the overlapping area between the source region 61 and the drain region 62 and the 70-ting gate electrode 3 is ensured, the influence of the side shape of the floating gate electrode 3 can be avoided during erasing. It becomes possible to ensure a stable tunnel current. Thereby, variations in erasing characteristics can be reduced. At the same time, the concentration of the electric field at the edge is alleviated, making it possible to increase the erasing voltage and thereby increasing the erasing speed.

Next, an embodiment of the method for manufacturing the above-mentioned nonvolatile memory element will be explained.

23 to 30 will be used to illustrate a method for manufacturing the 7-latch type nonvolatile memory cell shown in FIG. 22.

Similarly to FIG. 7 of the first embodiment, a conductive film 9A of polycrystalline silicon is formed on a semiconductor substrate.

Next, as shown in FIG. 24, in the formation region of the flood-type nonvolatile memory cell Qm, conductivity 11i1i! 9
The conductive TiM9A in the N-channel and P-channel MISFET 5 formation regions constituting the A and peripheral circuits is patterned to form control gate electrodes and gate electrodes of the N-channel and P-channel M-ISFETs.

Next, the surface is subjected to oxidation treatment to form a perfect grain 10.

The steps up to the next FIG. 25 and FIG. 28 correspond to FIGS. 9 to 12 of the first embodiment, so their explanation will be omitted. However, each ion implantation is performed through the polycrystalline silicon film for forming the floating gate electrode in a self-aligned manner with respect to the control gate electrode 9. Therefore, the efficiency of ion implantation must be higher than that in the first embodiment.

For example, the n-type impurity 12n has p+ of about 150Ke■,
The p-type impurity 13p is B+ at about 50 K e V, n+
The type impurities 11n" and 14n+ are formed by ion implantation of As+ with an energy of about 250 KeV. After that, the type impurities 11n" and 14n+ are formed by ion implantation with an energy of about 250 KeV.
type, p-type impurity 15n.

Ion implant 16p.

Next, as shown in FIG. 29, in the same manner as in FIG. 17 of the first embodiment, the control gate electrode 9 of the flash type nonvolatile memory cell Qm and the gate electrode 9 side of the N-channel and P-channel MI 5FETs are connected. A side wall 17 is formed in the portion.

Next, as shown in FIG. 30, the gate electrode 70 is processed in a self-aligned manner with respect to the control gate electrode 9 and sidewall 17 described above.

Hereinafter, the EEPROM of this embodiment is completed by the same process as that shown in FIG. 17 and subsequent figures of the first embodiment.

Next, FIG. 31 shows a modification of the third embodiment described above,
The floating gate electrode 7 and the control gate electrode 9 are connected to the source region 11.12 and the drain region 1.
It is asymmetrical with the 4 sides.

In this case, the source region 11.12 side of the floating gate electrode 7 is moved 0.2 to 0.3 μm laterally than the control gate electrode 1dJ1.9 by the sidewall spacer 17, as in the embodiment described above. It is formed to protrude. However, on the drain region 14 side, the respective ends of the floating gate electrode 7 and the control gate electrode 9 are aligned at substantially the same position.

With such an asymmetric structure, it is possible to increase the overlap between the source region 11° 12 and the floating gate electrode 7 and improve the erasing characteristics, while the drain region 1
At the same time, it is possible to reduce the overlap between the floating gate electrode 4 and the floating gate electrode 7 and improve the write characteristics.

The above invention made by the present inventor is a flash type EE.
An explanation ROM or an E
It can also be applied to microcontrollers with built-in E F ROM.

For example, in FIG. 32, 25 is a semiconductor substrate (chip) made of p-type single crystal silicon, and a plurality of bonding bands 26 are arranged around the semiconductor substrate (chip).

Input/output circuit area I10 inside the bonding pad 26
is provided. The microcomputer chip 25 shown in FIG. 32 is a μ (micro) ItOM.

CPU (Central Processing Unit), SCI (Serial Communication Interface), A/D (Analog)
digital conversion) circuit, dual-RAM (dual port Random Access Memo)
ry), RAM, ROM, timer 1, timer 2, and timer 3.

The present invention can be applied to the μRO84, 110M, and RAM units.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) By rounding the lower corner of the end of the floating gate electrode, it is possible to prevent the electric field from concentrating on the corner, and to prevent damage or deterioration of the gate insulation at the end of the floating gate electrode. Since this can be prevented, the number of rewrites can be increased.

(2) By rounding the lower corner of the end of the floating gate electrode, electric field concentration at the corner can be prevented, and the electric field during erasing is applied almost uniformly to the gate insulating film, which improves the erase characteristics between bits. Variations can be prevented. Furthermore, even if there are variations in the shape of the ends of the floating goo 1 pole, tunneling during erasing occurs closer to the channel than at the ends, so it is possible to prevent variations in erase percentage between bits.

(3) After the ion implantation 4 of As ions of =g degree for forming the source region, the oxidized film on the surface is removed and the oxide group is reattached, so that the gap between the floating gate electrode and the source region Since leakage current can be prevented, variations in erase percentage can be prevented. Also,
By performing the oxidation treatment after the silicon implantation described above, redundant bonds in the oxide film can be reduced, and the leakage current can be prevented or reduced.

(4) Since the overlap between the source region and the floating gate electrode can be reliably obtained, variations in erase characteristics can be eliminated.

(5) Since the # degree of the conductivity-imparting substance in the source region under the floating gate electrode can be increased with good controllability, the influence of the formation of an inversion layer or the spread of a depletion layer on the surface of the semiconductor substrate can be avoided during erase operation. The tunnel ↑h current is increased by applying the erase electric field only through the gate insulating film, thereby increasing the erase characteristics, especially the erase speed.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a part of the memory cell array section and peripheral circuit of EEF ROM by Kienri, and Fig. 2 is
FIG. 3 is a plan view of the memory cell array section showing the N-channel and P-channel side I5 for memory cells and peripheral circuits.
A cross-sectional view of the FET, FIG. 4 is an enlarged view of the gate portion of the memory cell, FIGS. 5 to 19 are cross-sectional views showing the manufacturing process of EEF ROM, and FIG. 20 and FIG. FIG. 22 is a sectional view showing the third embodiment of the present invention; FIG. 23 is a sectional view showing the third embodiment of the present invention;
30 is a sectional view showing the manufacturing process of the EEFROM of the third embodiment, FIG. 31 is a sectional view showing a modification of the third embodiment, and FIG. 32 is a sectional view of the EEFROM of the present invention. FIG. 2 is a layout diagram of a microcomputer chip to which the method is applied. Qm...Memory cell, Qp, Qn...M for peripheral circuits
I 5FET, 1... Semiconductor substrate, 4... Insulating layer for element isolation, 6... First gate insulating film, 7... Floating gate electrode, 8... Second gate insulating film, 9
...Control gate electrode (memory cell capital), gate box. Pole (peripheral circuit section), 11.12... Source region (memory cell), 14... Drain region (memory cell), 1
7... Side wall, 20.21... jd insulation film 23... Wiring, 15.18... Source/drain region of N-channel MISFET for peripheral circuit, 16° 19... Peripheral circuit p-channel MISI”
Source/drain region of ET, 24...Low concentration region. Agent: Patent Attorney Katsuo Ogawa

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device having a MISFET-type nonvolatile memory cell that erases information from a source region using a tunneling phenomenon, (2) forming a second conductive film on the first conductive film via a second insulating film; (3) forming the second conductive film on the first conductive film through the second insulating film; Step (4) of forming a floating gate electrode and a control gate electrode of a nonvolatile memory cell by patterning the first and second conductive films. Step (5) of forming a first oxide film on the surface of the semiconductor substrate at both ends; 1st
An n-type impurity is ion-implanted through the oxide film of the first
Step (6) of forming an n-type semiconductor region: A method for manufacturing a semiconductor device, comprising the step of oxidizing the surface of the semiconductor substrate after the ion implantation step. 2. Between steps (5) and (6), the first oxide film is removed and a new second oxide film is added to the M
2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, further comprising the step of forming a source region of an ISFET. 3. Claim 2 further comprising the step of forming a second n-type semiconductor region in the drain formation region of the MISFET in a self-aligned manner with respect to the floating gate electrode and the control gate electrode. A method for manufacturing a semiconductor integrated circuit device as described in 1. 4. Furthermore, a p-type semiconductor region is formed on the drain region side of the MISFET in a self-aligned manner with respect to the floating gate electrode and the control gate electrode so as to surround the n-type second semiconductor region in the drain formation region of the MISFET. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, further comprising the step of forming the semiconductor region No. 3. 5. Forming an n-type fourth semiconductor region having a lower concentration than the first n-type semiconductor region on the source region side of the MISFET in a self-aligned manner with respect to the floating gate electrode and the control gate electrode. 5. A method of manufacturing a semiconductor integrated circuit device according to claim 4, further comprising the steps of: 6. Furthermore, in the peripheral circuit formation region on the surface of the semiconductor substrate before and after the step (3), a second
MISF for peripheral circuit formation by patterning the conductive film of
6. The method of manufacturing a semiconductor integrated circuit device according to claim 5, further comprising the step of forming first and second gate electrodes of ET. 7. Between steps (4) and (6) above, introduce n-type impurities into both ends of the first gate electrode in a self-aligned manner with respect to the first gate electrode to form a fifth semiconductor region. and the second gate electrode is formed on both ends of the second gate electrode.
7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising the step of forming a sixth semiconductor region by introducing a p-type impurity into the gate electrode in a self-aligned manner. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, further comprising: forming a sidewall insulating film at both ends of the first and second gate electrodes. 9. Further, introducing an n-type impurity into the first gate electrode and the sidewall insulating film in a self-aligned manner to form a seventh semiconductor region, and introducing an n-type impurity into the second gate electrode and the sidewall insulating film in a self-aligned manner. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein a p-type impurity is introduced in a self-aligned manner to form an eighth semiconductor region. 10. In a semiconductor integrated circuit device having a MISFET-type nonvolatile memory cell that erases information from a source region using a tunneling phenomenon, (1) a semiconductor integrated circuit device provided on the surface of a semiconductor substrate via a first insulating film Floating gate electrode (2) provided on the floating gate electrode with a second insulating film interposed therebetween;
A control electrode (3) having substantially the same length in the channel direction of the MISFET; a control electrode (3) serving as a source and drain region of the MISFET provided at both ends of the floating gate electrode and the control gate electrode on the surface of the semiconductor substrate; A semiconductor integrated circuit comprising first and second n-type semiconductor regions, and further comprising means for relaxing electric field concentration at corner portions of the floating gate electrode between the floating gate electrode and the source region. circuit device. 11. The semiconductor integrated circuit device according to claim 10, wherein the floating gate electrode has rounded corners to alleviate electric field concentration. 12, the first n-type semiconductor region in the source region near the corner of the floating gate electrode;
11. The semiconductor integrated circuit device according to claim 10, further comprising a third n-type semiconductor region having a lower concentration than the n-type semiconductor region. 13. In a semiconductor integrated circuit device having a MISFET type nonvolatile memory cell that erases information from a source region using tunneling phenomenon, (1) Floating gate electrode (2) A control gate electrode provided on the floating gate electrode via a second insulating film. (3) A control gate electrode provided on both ends of the floating gate electrode and the control gate electrode on the surface of the semiconductor substrate. It has first and second n-type semiconductor regions that serve as source and drain regions of the MISFET, and the floating gate electrode is in the channel direction of the MISFET,
A semiconductor integrated circuit device, wherein the first semiconductor region of the source region is larger than the control gate electrode and overlaps the control gate electrode in the channel direction of the MISFET. 14. The semiconductor integrated circuit device according to claim 13, further comprising a sidewall insulating film formed on both ends of the control gate electrode. 15. The semiconductor integrated circuit device according to claim 14, wherein both ends of the floating gate electrode are located at equal distances from corresponding ends of each of the control gate electrodes. 16. The semiconductor integrated circuit device according to claim 13, wherein the second n-type semiconductor region of the drain region overlaps the control gate electrode. 17. The semiconductor integrated circuit device according to claim 13, wherein a p-type semiconductor region is provided so as to surround the second n-type semiconductor region. 18. The semiconductor integrated device according to claim 13, wherein ends of each of the floating gate electrode and the control gate electrode are located at the same position in the channel direction of the MISFET on the side of the drain region. circuit device. 19. The semiconductor integrated circuit device according to claim 18, wherein a sidewall insulating film is present only at the end of the control gate electrode on the source region side. 20. In a semiconductor integrated circuit device having a MISFET-type nonvolatile memory cell that erases information from a source region using a tunneling phenomenon, (1) a first insulating film is provided in a memory cell formation region on the surface of a semiconductor substrate; (2) forming a second conductive film on the first conductive film via a second insulating film; (3) forming the second conductive film on the first conductive film; Step (4) of forming a control gate electrode by patterning (4) Step of forming first and second n-type semiconductor regions that will become the source/drain regions of the MISFET in a self-aligned manner with respect to the control gate electrode ( 5) A method for manufacturing a semiconductor integrated circuit device, comprising the step of forming a floating gate electrode longer than the control gate electrode in the channel direction of the MISFET. 21. Between the steps (4) and (5) above, a sidewall insulating film is formed on both ends of the control gate electrode, and a floating gate is formed in a self-aligned manner with respect to the control gate electrode and the sidewall insulating film. 21. The semiconductor integrated circuit device according to claim 20, further comprising the step of forming electrodes.