JPS60116061A - 入出力処理方式 - Google Patents

入出力処理方式

Info

Publication number
JPS60116061A
JPS60116061A JP58224690A JP22469083A JPS60116061A JP S60116061 A JPS60116061 A JP S60116061A JP 58224690 A JP58224690 A JP 58224690A JP 22469083 A JP22469083 A JP 22469083A JP S60116061 A JPS60116061 A JP S60116061A
Authority
JP
Japan
Prior art keywords
transfer
adapter
controller
input
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58224690A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6253864B2 (enExample
Inventor
Toshiharu Oshima
大島 俊春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58224690A priority Critical patent/JPS60116061A/ja
Publication of JPS60116061A publication Critical patent/JPS60116061A/ja
Publication of JPS6253864B2 publication Critical patent/JPS6253864B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Bus Control (AREA)
JP58224690A 1983-11-29 1983-11-29 入出力処理方式 Granted JPS60116061A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58224690A JPS60116061A (ja) 1983-11-29 1983-11-29 入出力処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58224690A JPS60116061A (ja) 1983-11-29 1983-11-29 入出力処理方式

Publications (2)

Publication Number Publication Date
JPS60116061A true JPS60116061A (ja) 1985-06-22
JPS6253864B2 JPS6253864B2 (enExample) 1987-11-12

Family

ID=16817705

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58224690A Granted JPS60116061A (ja) 1983-11-29 1983-11-29 入出力処理方式

Country Status (1)

Country Link
JP (1) JPS60116061A (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120458A (ja) * 1983-12-05 1985-06-27 Nec Corp デ−タ転送装置
JPS6275861A (ja) * 1985-09-30 1987-04-07 Fujitsu Ltd チヤネル処理装置
JPS6410372A (en) * 1987-07-03 1989-01-13 Nec Corp Direct memory access restart system
US5333274A (en) * 1991-10-15 1994-07-26 International Business Machines Corp. Error detection and recovery in a DMA controller

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60120458A (ja) * 1983-12-05 1985-06-27 Nec Corp デ−タ転送装置
JPS6275861A (ja) * 1985-09-30 1987-04-07 Fujitsu Ltd チヤネル処理装置
JPS6410372A (en) * 1987-07-03 1989-01-13 Nec Corp Direct memory access restart system
US5333274A (en) * 1991-10-15 1994-07-26 International Business Machines Corp. Error detection and recovery in a DMA controller

Also Published As

Publication number Publication date
JPS6253864B2 (enExample) 1987-11-12

Similar Documents

Publication Publication Date Title
US5802398A (en) Method and apparatus for allowing communication between a host computer and at least two storage devices over a single interface
US5740466A (en) Flexible processor-driven SCSI controller with buffer memory and local processor memory coupled via separate buses
US6330626B1 (en) Systems and methods for a disk controller memory architecture
US6408369B1 (en) Internal copy for a storage controller
US6105076A (en) Method, system, and program for performing data transfer operations on user data
JP2770901B2 (ja) ディスク制御方法
JPH04367023A (ja) 二重化ディスク制御装置
US7340551B2 (en) Bridge permitting access by multiple hosts to a single ported storage drive
US20030172229A1 (en) Systems and methods for detecting and compensating for runt block data transfers
JPS60116061A (ja) 入出力処理方式
US5974530A (en) Integrated PCI buffer controller and XOR function circuit
JPH01140326A (ja) 磁気ディスク装置
US6233628B1 (en) System and method for transferring data using separate pipes for command and data
US5954806A (en) Method to handle SCSI messages as a target
JPH04373054A (ja) ファイル装置制御装置
JPS6027014A (ja) 磁気デイスク制御装置
JP3259095B2 (ja) データ転送方法
JPH0519181B2 (enExample)
JP2826780B2 (ja) データ転送方法
JP2541158B2 (ja) 情報処理システム
JPH10214247A (ja) 外部記憶装置インタフェース
JPH11338644A (ja) ディスク制御装置及び記憶装置
JPS5960623A (ja) バツフア制御装置
JPH04321121A (ja) 情報記憶装置
JPS61285566A (ja) 入出力制御装置