JPS60116051A - Memory - Google Patents

Memory

Info

Publication number
JPS60116051A
JPS60116051A JP58223716A JP22371683A JPS60116051A JP S60116051 A JPS60116051 A JP S60116051A JP 58223716 A JP58223716 A JP 58223716A JP 22371683 A JP22371683 A JP 22371683A JP S60116051 A JPS60116051 A JP S60116051A
Authority
JP
Japan
Prior art keywords
parity
error
parity error
output
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58223716A
Other languages
Japanese (ja)
Inventor
Etsuro Yamauchi
山内　悦朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58223716A priority Critical patent/JPS60116051A/en
Publication of JPS60116051A publication Critical patent/JPS60116051A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G06F11/0775—Content or structure details of the error report, e.g. specific table structure, specific error fields

Abstract

PURPOSE:To perform parity error processing accurately and simply by providing a device that stores parity error address at the time of occurrence of the parity error. CONSTITUTION:When a read signal MEMR' of a memory is inputted, values of addresses A0-A7 are latched by a D-FF4 by a rise edge of output of an NAND gate 5 inputted to clock input CLK of a 8-bit D type flip-flop (D-FF)4 of a rise edge trigger. At this time, parity check is made on the read data in a parity chacker and generator circuit 3, and when parity error is generated, an output signal Error' is lowered to a low level. When the output signal Error' becomes active, a clock input CLK of the D-FF4 is inhibited. Accordingly, even if the next read signal MEMR' is inputted, an output of the D-FF4 is not influenced by that, and parity error addresses PAR0 to PAR7 are maintained.

Description

【発明の詳細な説明】 本発明は記憶装置に係シ、特に情報処理装置における記
憶装置のデータの人力時に発生するパリティエラー処理
部に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage device, and more particularly to a parity error processing section that occurs when data in a storage device is manually input in an information processing device.

従来のこの種の記憶装置を用いた情報処理装置では、記
憶装置へのデータの大出力時に発生したハリティエラー
の処理を本記憶装置よシバリティエラー割込信号等を発
生し５、その割込信号により中央処理装置に於いてパリ
グイエラーの割込処理を行なっていた。しかし、中央処
理装置が割込禁止状態になっていた場合等に於いては、
割込禁止状態が解除されるまで割込が受付けられず、そ
の間に中央処理装置は他のアドレスをアクセスするため
の時間を持つため、パリティエラー発生アドレスを再生
することは不可能であった。In a conventional information processing device using this type of storage device, the storage device generates a harness error interrupt signal, etc. 5 to process a harness error that occurs when a large amount of data is output to the storage device. The interrupt signal caused the central processing unit to perform interrupt processing for parity errors. However, in cases such as when the central processing unit is in an interrupt-disabled state,
Since no interrupts are accepted until the interrupt-disabled state is released, and during that time the central processing unit has time to access other addresses, it has been impossible to reproduce the address where the parity error has occurred.

本発明の目的は、前記欠点を解決し、羅実なパリティエ
ラー処理を行なわせることができるようにした記憶装置
を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a storage device that solves the above-mentioned drawbacks and allows for thorough parity error processing.

本発明は、パリティ機能を俯えた記憶装置において、記
憶データの大出力時にパリティエラーの発生したアドレ
スを記憶しておくだめの手段を設けたことを特徴とする
記憶装置にある。The present invention resides in a storage device with a parity function, characterized in that it is provided with means for storing an address where a parity error occurs when a large amount of storage data is output.

次に、本発明の実施例について図面を参照して詳細に説
明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.

第１図は本発明の実施例の記憶装置を部分的に示すブロ
ック図である。同図において、本発明の実施例の記憶装
置は８ｂｉｔ　Ｘ　２５６のメモリアレイ１と、１ｂｉ
ｔ　Ｘ２５６のパリティビット２と、パリティチェッカ
及びジェネレータ回路３と、立上が９エツジトリガの８
ビツトＩ）型フリップ串フユップ（Ｄ−ＦＦ）４と、Ｎ
ＡＮＤゲート５とを備えておシ、人出力信号としては・
＜リオイエラー発生時の出力信号Ｅｒｒｏｒと、メモリ
及びノクリデイピットに対する読出し信号ＭＥＭＲと、
メモリ及びパリティビットに対する書込み信号ＭｇＭＷ
と、メモリ及びパリティビットに対するアドレス信号１
０、　ＡＩ、　Ａ２．　Ａ３．　Ａ、４．　Ａ５．　Ａ
６゜Ａ７と、メモリアレ（］又はパリティチェッカ及び
ジェオ１／−メ回路３に対するデータバスＤＯ。FIG. 1 is a block diagram partially showing a storage device according to an embodiment of the present invention. In the figure, the storage device according to the embodiment of the present invention has a memory array 1 of 8 bits x 256, and a memory array 1 of 1 bit x 256.
Parity bit 2 of tX256, parity checker and generator circuit 3, and 8
Bit I) type flip skewer (D-FF) 4 and N
It is equipped with an AND gate 5, and as a human output signal,
<The output signal Error when an error occurs, the read signal MEMR for the memory and the nokri day pit,
Write signal MgMW for memory and parity bits
and address signal 1 for memory and parity bits.
0, AI, A2. A3. A, 4. A5. A
6.A7 and data bus DO for memory array () or parity checker and geo1/-me circuit 3.

ＤＩ、Ｄ２．Ｄ３．］）４．Ｌ’）５．］）６．Ｄ７と
、パリグイビットの人田力に使用するノ（スＤＰと、ハ
リティエラーアドレスの出力信号ＰＡ、ＲＯ。DI, D2. D3. ])4. L')5. ])6. D7, the output signals PA and RO of the error address, and the output signals PA and RO used for the pariguibit Hitada force.

ＰＡＡｌ１ＰＪ’１２．ＰＡ、Ｒ３，ＰＡＲ４，ＰＡＲ
５，ＰＡＲ６゜ＰＡＲ７と、８ビットＤ−ＦＦ４のクロ
ック入力ＣＣＴ、　Ｋ等がある。PAAl1PJ'12. PA, R3, PAR4, PAR
5, PAR6°PAR7, 8-bit D-FF4 clock input CCT, K, etc.

次に動作の説明を行う。メモリアレイ１及び）くリティ
ビット２に対して型造信号ＭＥＭＷが入力されると、デ
ータバスＤ・０乃至ＤＩよシ与えられたデータがアドレ
スＡＯ乃至人７で指定された番地に書込まれる。またデ
ータはパリティチェッカ及びジェネレータ回路３にも加
えられ、より生成されたパリティがパリティビット２に
書込まれる。Next, the operation will be explained. When the molding signal MEMW is input to the memory array 1 and the quality bit 2, the data given from the data buses D.0 to DI are written to the addresses specified by the addresses AO to 7. . The data is also applied to the parity checker and generator circuit 3, and the generated parity is written to the parity bit 2.

メモリアレイ１及びパリグイビット２に対して読出し信
号ＭＥＭＲが人力されると、アドレスＡＯ乃至Ａ７で指
定された番地よシデータ及びノ＜リテイが読出されデー
タバスＤｏ乃至Ｄ７及びバスＤＰを通してパリティチェ
ッカ及びジェネレータ回路３のパリティチェッカに加え
られる。バＩＪ　ｒイチェッカ及びジェネレータ回路３
においてバＩＪ　フイチェックが行なわれ、パリティエ
ラーが発生した場合は出力信号Ｅｒｒｏｒを低レベルに
して中央処理装置等にパリティエラーが発生した事を知
らせると同時に、ＮＡＮＤゲート５を通してＤ−ＦＦ４
に加えられる。このＤ−ＦＦ４　は通常読出し信号ＭＥ
ＭＲの立下がシエッジによってアドレスＡＯ乃至Ａ７を
ラッチしているが、パリティエラー発生時には出力信号
ＥｒｒｏｒによりアドレスＡＱ乃至Ａ７ラツチ後Ｄ−Ｆ
Ｆ４　のクロック人力ＣＬＫが禁止され、Ｄ−ＦＦ４に
ラッチされたパリティエラーアドレスＰＡＲＯ乃至ＰＡ
Ｒ７は、パリティエラー処理が終了し出力信号Ｅｒｒｏ
ｒがクリアされるまで保持されるため、パリティエラー
アドレスが失われることなく、適確なエラー処理ができ
る。When the read signal MEMR is input to the memory array 1 and the parity bit 2, the data and information at the addresses specified by the addresses AO to A7 are read out and sent to the parity checker and generator circuit through the data buses Do to D7 and the bus DP. It is added to the parity checker of 3. Checker and generator circuit 3
When a parity error occurs, the output signal Error is set to low level to notify the central processing unit that a parity error has occurred.
added to. This D-FF4 is the normal read signal ME
The falling edge of MR latches addresses AO to A7, but when a parity error occurs, the output signal Error causes addresses AQ to A7 to be latched and then D-F.
The clock CLK of F4 is disabled and the parity error addresses PARO to PA latched in D-FF4
R7 outputs the output signal Erro after parity error processing is completed.
Since r is held until cleared, the parity error address is not lost and appropriate error processing can be performed.

第２図は本発明の実施例の記憶装置のタイミングチャー
トである。メモリの胱出し信号ＭＥＭＲが人力されると
、Ｄ−ＦＦ４のクロック人力ＣＬＫに人力されたＮＡＮ
Ｄゲート５の出力の立上がシエッジによって、アドレス
ＡＯ乃至Ａ７の値がＤ−ＦＦ′４にラッチされる。その
時読出されたデータによって、パリティチェックが行な
われ、パリティエラーが発生した場合、出力信号Ｅｒｒ
ｏｒｆ低レベルに落す。出力信号Ｅｒｒｏｒがアクティ
ブになると、Ｄ−ＦＦ４のクロック人力ＣＬＫが禁止さ
れるため、次の読出し信号ＭＥＭＲが入力されてもＤ−
ＦＦ４の出力は影響を受けず、パリティエラーアドレス
ＰＡＲＯ乃至ＰＡＲ７を保持する。FIG. 2 is a timing chart of a storage device according to an embodiment of the present invention. When the bladder output signal MEMR of the memory is manually input, the input NAN is input to the clock CLK of D-FF4.
When the output of the D gate 5 rises, the values of addresses AO to A7 are latched into the D-FF'4. A parity check is performed based on the data read at that time, and if a parity error occurs, the output signal Err
orf lower to low level. When the output signal Error becomes active, the clock CLK of D-FF4 is prohibited, so even if the next read signal MEMR is input, the D-FF4 clock CLK is disabled.
The output of FF4 is not affected and holds the parity error addresses PARO to PAR7.

本発明によれば、以上説明したように、パリティエラー
発生時におけるパリティエラーアドレスを記憶しておく
手段を設ける事によシ、適確に且つ簡単なハリティエラ
ー処理が可能となる等の効果が得られる。According to the present invention, as explained above, by providing a means for storing a parity error address when a parity error occurs, it is possible to accurately and easily process a parity error. is obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の実施例の記憶装置を部分的に示すブロ
ック図、第２図は第１図に示した本発明の一実施例の記
憶装置のタイミングチャートである。面図において、 １・・・・・・Ｂｂｉｔｘ２５６メモリアレイ、２・・
・・・・１ｂｉｔＸ２５６のパリティビット、３・・・
・・・パリティチャツカ及びジェネレータ回路、４・・
・・・・立上がりエツジトリガの８ビットＤ−ＦＦ、５
・・・・・・２人力ＮＡＮＤゲート、Ｅｒｒｏｒ　・・
・・・・パリティエラーの発生を知らせる出力信号、Ｍ
ＥＭＩ（、・・・・・読出し信号、ＭＥＭ′ｗ−・・・
・・書込み信号、ＡＯ乃至Ａ７・・・・・・アドレス信
号、ＤＯ乃至ＤＩ・・・・・・データバス、Ｉ）Ｐ・・
・・・・パリティビットの人出力用バス、１０乃至１７
・・・・・・Ｄ−ＦＦのデータ入力端子、２０乃至２７
・・・・・・Ｄ−ＦＦのデータ出力端子、ＣＬＫ・・・
・・・Ｄ−ＦＦのクロック入力端子、ＰＡＲＯ乃至ＰＡ
Ｆｔ７・・・・・・パリティエラーアドレス信号。FIG. 1 is a block diagram partially showing a storage device according to an embodiment of the present invention, and FIG. 2 is a timing chart of the storage device according to the embodiment of the invention shown in FIG. In the top view, 1...Bbitx256 memory array, 2...
...1 bit x 256 parity bits, 3...
...Parity chatka and generator circuit, 4...
...rising edge trigger 8-bit D-FF, 5
...Two-person NAND gate, Error...
... Output signal that notifies the occurrence of a parity error, M
EMI (,... Read signal, MEM'w-...
...Write signal, AO to A7...Address signal, DO to DI...Data bus, I)P...
...Parity bit human output bus, 10 to 17
...D-FF data input terminals, 20 to 27
...D-FF data output terminal, CLK...
...D-FF clock input terminal, PARO to PA
Ft7...Parity error address signal.

Claims (1)

【特許請求の範囲】[Claims] パリティ機能を備えた記憶装置において、記憶データの
大出力時にパリティエラーの発生したアドレスを記憶し
ておく手段を設けたことを特徴とする記憶装置。A storage device equipped with a parity function, characterized in that the storage device is provided with means for storing an address where a parity error occurs when a large amount of storage data is output.
JP58223716A 1983-11-28 1983-11-28 Memory Pending JPS60116051A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58223716A JPS60116051A (en) 1983-11-28 1983-11-28 Memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58223716A JPS60116051A (en) 1983-11-28 1983-11-28 Memory

Publications (1)

Publication Number Publication Date
JPS60116051A true JPS60116051A (en) 1985-06-22

Family

ID=16802548

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58223716A Pending JPS60116051A (en) 1983-11-28 1983-11-28 Memory

Country Status (1)

Country Link
JP (1) JPS60116051A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08123749A (en) * 1994-10-27 1996-05-17 Fuji Electric Co Ltd Bus controller
JP2019526845A (en) * 2016-06-29 2019-09-19 マイクロン テクノロジー，インク． Error correction code event detection

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08123749A (en) * 1994-10-27 1996-05-17 Fuji Electric Co Ltd Bus controller
JP2019526845A (en) * 2016-06-29 2019-09-19 マイクロン テクノロジー，インク． Error correction code event detection
US10949300B2 (en) 2016-06-29 2021-03-16 Micron Technology, Inc. Error correction code event detection
JP2022009444A (en) * 2016-06-29 2022-01-14 マイクロン テクノロジー，インク． Error correction code Event detection

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