JPS60111599U - decoder circuit - Google Patents
decoder circuitInfo
- Publication number
- JPS60111599U JPS60111599U JP20259583U JP20259583U JPS60111599U JP S60111599 U JPS60111599 U JP S60111599U JP 20259583 U JP20259583 U JP 20259583U JP 20259583 U JP20259583 U JP 20259583U JP S60111599 U JPS60111599 U JP S60111599U
- Authority
- JP
- Japan
- Prior art keywords
- input
- decoder circuit
- circuit
- input combination
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Static Random-Access Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデコーダ回路の一例の回路図、第２図は
本考案の一実施例の回路図である。
１．２．．３．４・・・デコーダ回路、１１，２１゜３
１．４１・・・ＮＯＲ回路、１２，２２．３２．４２・
・・バッファ部、１０１〜４０９−トランジスタ、Ａ１
．Ａ１．Ａ２．Ａ２・・・入力信号、Ｎ１〜Ｎ４・・・
節点、０□〜０４・・・出力端、φ１〜φ４・・・制御
信号。FIG. 1 is a circuit diagram of an example of a conventional decoder circuit, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1.2. ．． 3.4...Decoder circuit, 11,21゜3
1.41...NOR circuit, 12,22.32.42.
...Buffer part, 101-409-transistor, A1
．． A1. A2. A2...Input signal, N1-N4...
Nodes, 0□~04... Output ends, φ1~φ4... Control signals.
Claims (1)
上の整数）個の入力組合せ回路と、該入力組合せ回路の
各々に１個づつ接続し該入力組合せ回路の出力信号を増
幅するＮ個のバッファ部と、前記バッファ部のそれぞれ
の出力端と接地間にソースとドレインが接続し該接続し
ているバッファ部以外のバッファ部の入力端にゲートが
接続する（Ｎ−１’）ＸＮ個のトランジスタとを含むこ
とを特徴とするデコーダ回路。N (N is an integer of 2 or more) input combination circuits that input, combine, and select input signals; and N that connect one input combination circuit to each of the input combination circuits to amplify the output signal of the input combination circuit. (N-1') A decoder circuit comprising: transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20259583U JPS60111599U (en) | 1983-12-27 | 1983-12-27 | decoder circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20259583U JPS60111599U (en) | 1983-12-27 | 1983-12-27 | decoder circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60111599U true JPS60111599U (en) | 1985-07-29 |
Family
ID=30765035
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20259583U Pending JPS60111599U (en) | 1983-12-27 | 1983-12-27 | decoder circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60111599U (en) |
-
1983
- 1983-12-27 JP JP20259583U patent/JPS60111599U/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS60111599U (en) | decoder circuit | |
| JPS583612U (en) | amplifier circuit | |
| JPS58164339U (en) | Signal switching circuit | |
| JPS60101832U (en) | Complementary MOS integrated circuit | |
| JPS59177240U (en) | Output circuit | |
| JPS59121943U (en) | logic level setting circuit | |
| JPS59104248U (en) | Transmission redundant circuit | |
| JPS6055129U (en) | Output circuit | |
| JPS6025281U (en) | mixing circuit | |
| JPS6119859U (en) | diagnostic circuit | |
| JPH01122629U (en) | ||
| JPS6079822U (en) | transistor circuit | |
| JPS591235U (en) | signal input circuit | |
| JPS5988923U (en) | differential amplifier | |
| JPS59171410U (en) | Muting circuit | |
| JPS5976136U (en) | delay circuit | |
| JPS5866713U (en) | amplifier | |
| JPS59119644U (en) | Gate array IC | |
| JPS5823433U (en) | noise suppression circuit | |
| JPS6066110U (en) | Amplifier muting circuit | |
| JPS6056098U (en) | Reverberation adding device with analog mixer circuit | |
| JPS6088634U (en) | Signal switching circuit | |
| JPS6030498U (en) | echo circuit | |
| JPS601081U (en) | Monitor switching circuit | |
| JPS6145707U (en) | Signal switching circuit |