JPS60111474A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form an inverted trapezoid gate shape (the reduction of gate resistance) and shorten space between a gate and a source (the reduction of source resistance) by forming a window for the gate to an silicon oxide film and an silicon nitride film in a region as a gate electrode through a carbon tetrafluoride group reactive ion etching method. CONSTITUTION:An silicon oxide film 3 and an silicon nitride film 4 are deposited on a semi-insulating GaAs semiconductor substrate 1 with an N type active layer 2 in succession. When a resist mask 5 is formed and the insulating films 3, 4 are dry-etched through a RIE method in which hydrogen is added to carbon tetrafluoride, the silicon nitride film layer 4 is side-etched more than the silicon oxide film layer 3. When the resist 5 is removed, a gate metallic film 6 is shaped while using a resist 5' as a mask and the silicon nitride film 4 and the silicon oxide film layer 3 are processed through the RIE method by employing hydrocarbon trifluoride, the silicon oxide film 3 is etched at a rate faster than the silicon nitride film 4. An ohmic metal 7 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, particularly a Schottky gate field effect transistor using a ■-■ group compound semiconductor. The present invention can reduce gate resistance and reduce source and drain tjfI! without damaging the semiconductor substrate surface during gate electrode processing. , by a self-alignment method, the occurrence of short-circuits between the gate electrode and the source and drain electrodes can be reduced as much as possible, and the distance between the source and drain electrodes can be narrowed.

The present invention will be explained below based on examples.

FIGS. 1 to 7 show schematic diagrams of the device manufacturing process according to the present invention. First, as shown in FIG. 1, a silicon oxide film 3 by chemical vapor deposition or the like and a silicon nitride film by plasma chemical vapor deposition are deposited on a semi-insulating GaAs semiconductor substrate 1 having an N-type active layer 2 in a predetermined region. Film 4 is deposited in this order.

Next, as shown in FIG. 2, a resist mask 5 for processing the base insulating films 3 and 4 is formed on the region that will become the gate electrode by optical exposure, photobeam exposure, or the like. Next, the P film 3.4 was dry-etched using carbon tetrafluoride with 5% to 20% hydrogen added and an active ion etching method to form the substrate 1.
expose the surface of In such dry etching, the etching rate of the silicon nitride film 4 is 30 to 50% faster than the silicon oxide film 3 (the selection ratio can be further increased depending on the dry etching conditions), so as shown in FIG. The side etching of No. 4 is more advanced than the silicon oxide film layer 3.

Next, after removing the resist 5, in order to remove the Freon polymer formed during dry etching and the damaged parts during dry etching, hydrochloric acid treatment at 70 to 100°C was followed by heat treatment at 200 to 400°C in hydrogen for about 30 minutes. administer. Thereafter, as shown in FIG.
500A, about 2000 to 5000X deposition 1-1 A resist 5' is formed again for gate electrode processing. Next, the titanium nitride/gold layer of the gate metal 6 is processed by ion milling using an Ar ion beam, using the resist 5' as a mask, and the tantalum silicide layer is processed by reactive ion etching using Freon gas. It is processed to have the structure shown in FIG.

Next, among the above-mentioned 7-Leon gases, carbon tetrafluoride was used for the gate opening shown in Figure 2, but this time, hydrocarbon trifluoride was used to dry-etch the tantalum silicide layer. When silicon nitride film 4 and silicon oxide spread layer 3 are etched by reactive ion etching, it is different from carbon tetrafluoride based silicon oxide film because it is etched 50 to 200 times faster than silicon nitride film. The structure will be as shown in the figure. At this time, in order to deposit an ohmic metal and realize a good contact resistance layer as a subsequent step, hydrochloric acid treatment is performed at 70 DEG C. to 100 DEG C. to clean the surface of the semiconductor substrate.

After that, A u Ge/Nt as ohmic metal 7
(Fig. 6), remove the ohmic metal 7 on the cedar metal 6 and the non-WIJI area by the commonly used 2-to-7 method, and then 4
Heat-treated for several minutes in a hydrogen atmosphere at 00 to 450°C,
Forms ohmic contact. Therefore, a layer 8 of Ti, Pt, Au, etc. is formed on the inside of the ohmic metal by a conventional optical exposure method, etc. on the source and drain using a conventional method for forming the source and drain. Get the picture.

Furthermore, the present invention is not limited to the above-mentioned embodiments; for example, as shown in FIG. 8 in addition to the process shown in FIG.
After dry etching 3 and 4, the semiconductor substrate 1 can be applied to a so-called recessed structure by using a liquid mixture of sodium hydroxide and violet peroxide, etc. In this case, the Schottky gate electric field shown in FIG. Obtain the effect transistor. in this way,
By applying the present invention, not only can the withstand voltage be improved, but also the resistance on the source and drain sides can be reduced, an inverted trapezoidal gate shape can be formed (reduction in gate resistance), and the gate-source spacing can be reduced by the self-alignment method. By making full use of lithography technology, it is possible to form an extremely short structure in a short time, thereby reducing the source resistance and realizing a high-performance device.

According to the present invention, as shown in FIGS. 5 and 6, even when the ohmic metal 7 approaches the gate metal 6 side during ohmic metal evaporation and heat treatment using the self-alignment method, the silicon nitride film and Since a silicon oxide film is attached, it has the advantage that short circuits are unlikely to occur.

[Brief explanation of drawings]

FIGS. 1 to 7 are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps. FIGS. 8 and 9 are cross-sectional views showing the manufacturing process of another embodiment of the present invention. 1...Semi-insulating GaAs substrate, 2...
...N-type active layer, 3...Silicon oxide film, 4
...Silicon nitride film, 5.5'...Photoresist, 6...Gate metal, 6- 7...Ohmic metal, 8... ...electrode metal. -7- 4 wards -,, N ℃ decrease K acupuncture opening mouth box size Fumiatsu acupuncture decrease

Claims (1)

[Claims] A silicon oxide film and a silicon nitride film are formed on the surface of a semiconductor substrate, and the silicon oxide film and silicon nitride film in a region that will become a gate electrode are etched by active ion etching using a carbon tetrafluoride adhesive to form a gate. A fenestration is formed, and then a gate metal is formed within the gate fenestration and on the silicon nitride ridge to a width larger than the fenestration size for a multi-nucleated gate by an etching method using a resist mask, and then the silicon oxide film is and the silicon nitride film are removed by active ion etching using a carbon trifluoride based adhesive, and after that, the surface of the semiconductor substrate is cleaned with the resist mask attached, and then an ohmic metal is deposited, A method of manufacturing a semiconductor device, characterized in that a predetermined portion of the ohmic metal is removed by a self-line lift-off method using the resist, thereby forming source and drain electrodes.